CN113098483A - High-speed fully-differential boost conversion circuit - Google Patents
High-speed fully-differential boost conversion circuit Download PDFInfo
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- CN113098483A CN113098483A CN202110325873.XA CN202110325873A CN113098483A CN 113098483 A CN113098483 A CN 113098483A CN 202110325873 A CN202110325873 A CN 202110325873A CN 113098483 A CN113098483 A CN 113098483A
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention provides a high-speed fully-differential boost conversion circuit, which comprises: the boost conversion module is used for carrying out voltage boost on the low-voltage differential input signal so as to generate a high-voltage differential output signal; and the offset setting module is used for setting the direct-current working point of the high-voltage differential output signal. The high-speed fully-differential boost conversion circuit provided by the invention realizes the voltage boost at the I/O interface.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a high-speed fully-differential boost conversion circuit.
Background
The interface between the internal chip and the external chip is usually called an I/O interface, and the signal conversion between the external chip and the internal chip can be realized through the I/O interface to complete the corresponding control function.
However, in the signal conversion process, how to convert the input low power voltage signal into the high power voltage signal for the internal chip is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a high-speed fully differential boost converter circuit applied at an I/O interface for voltage boosting.
To achieve the above and other related objects, the present invention provides a high-speed fully-differential boost converter circuit, including:
the boost conversion module is used for carrying out voltage boost on the low-voltage differential input signal so as to generate a high-voltage differential output signal;
and the offset setting module is used for setting the direct-current working point of the high-voltage differential output signal.
Optionally, the boost conversion module includes:
the input control unit is used for generating a conversion control signal according to the low-voltage differential input signal;
the conversion output unit is connected between a high power supply voltage and the output end of the input control unit and used for performing voltage conversion according to the conversion control signal so as to generate the high-voltage differential output signal;
and the bias mirror image unit is connected between the high power supply voltage and the differential output end of the high-speed fully-differential boost conversion circuit and is used for mirroring the direct-current working point to the differential output end.
Optionally, the input control unit comprises: the input end of the first phase inverter and the input end of the second phase inverter are used as the differential input end of the high-speed fully differential boost conversion circuit, the output end of the first phase inverter is connected to the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is used as the first output end of the input control unit, the output end of the second phase inverter is connected to the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is used as the second output end of the input control unit; the working voltage of the first inverter and the second inverter is a low power supply voltage.
Optionally, the input control unit further comprises: the third NMOS tube is connected in series between the drain electrode of the first NMOS tube and the first output end of the input control unit, the fourth NMOS tube is connected in series between the drain electrode of the second NMOS tube and the second output end of the input control unit, and the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are both connected with bias voltage.
Optionally, the conversion output unit includes: the high-speed full-differential boost conversion circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein a source electrode of the first PMOS tube and a source electrode of the second PMOS tube are both connected with a high power supply voltage, a drain electrode of the first PMOS tube is connected with a grid electrode of the second PMOS tube and serves as a differential output end of the high-speed full-differential boost conversion circuit, the grid electrode of the first PMOS tube is connected with a second output end of the input control unit, a drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube and serves as another differential output end of the high-speed full-differential boost conversion circuit, and a grid electrode of the second PMOS tube is connected with a first output end of the input control unit.
Optionally, the conversion output unit further includes: the first resistor is connected in parallel to the two ends of the source and the drain of the first PMOS tube, and the second resistor is connected in parallel to the two ends of the source and the drain of the second PMOS tube.
Optionally, the offset mirroring unit includes: the third PMOS tube is connected in series between the high power supply voltage and one differential output end of the high-speed fully differential boost conversion circuit, the fourth PMOS tube is connected in series between the high power supply voltage and the other differential output end of the high-speed fully differential boost conversion circuit, and the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are both connected to the mirror image control end of the bias setting module.
Optionally, the offset setting module includes:
the bias setting unit is used for setting the size of the direct current working point according to a preset voltage and a preset resistor;
and the bias generating unit is connected to the output end of the bias setting unit and used for generating the direct current working point according to the self-feedback of the operational amplifier and mirroring the direct current working point to the differential output end of the high-speed fully-differential boost conversion circuit through mirroring.
Optionally, the offset setting unit includes: the bias setting circuit comprises a preset resistor and a current source, wherein one end of the preset resistor is connected to preset voltage, the other end of the preset resistor is connected to one end of the current source and serves as an output end of the bias setting unit, and the other end of the current source is grounded.
Optionally, the bias generating unit includes: an operational amplifier, a third inverter, a third resistor, a fifth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, the non-inverting input end of the operational amplifier is connected to the output end of the bias setting unit, the inverting input end of the operational amplifier is connected to the drain electrode of the fifth PMOS tube and the drain electrode of the sixth NMOS tube, the output end of the operational amplifier is connected to the gate electrode of the fifth PMOS tube, and is used as a mirror control end of the bias generation unit, the source electrode of the fifth PMOS tube is connected with high power supply voltage, the third resistor is connected in parallel with two ends of the source electrode and the drain electrode of the fifth PMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with bias voltage, the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected to the output end of the third phase inverter, and the input end of the third phase inverter is connected to the low level of the low power supply voltage.
As described above, the high-speed fully-differential boost converter circuit of the present invention can correctly boost and convert the low-voltage differential input signal received by the I/O interface into the high-voltage differential output signal for the internal chip to use; moreover, through the design of the third NMOS tube, the fourth NMOS tube, the first resistor and the second resistor, the rapid pull-down and lifting of the level can be realized, so that the level conversion speed of the high-speed fully-differential boost conversion circuit can even exceed 10 Gb/s.
Drawings
Fig. 1 is a schematic circuit diagram of a high-speed fully-differential boost converter circuit according to the present invention.
Description of the element reference numerals
100 boost conversion module
101 input control unit
102 conversion output unit
103 offset mirror cell
200 offset setting module
201 offset setting unit
202 bias generating unit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a high-speed fully differential boost converter circuit, which includes:
the boost conversion module 100 is configured to boost a voltage of the low-voltage differential input signal to generate a high-voltage differential output signal;
and an offset setting module 200, configured to set a dc operating point of the high-voltage differential output signal.
As an example, as shown in fig. 1, the boost conversion module 100 includes:
an input control unit 101 for generating a switching control signal according to the low voltage differential input signal;
a conversion output unit 102, connected between a high power voltage and an output terminal of the input control unit 101, for performing voltage conversion according to the conversion control signal to generate the high voltage differential output signal;
and the bias mirror image unit 103 is connected between a high power supply voltage and the differential output end of the high-speed fully-differential boost conversion circuit, and is used for mirroring the direct-current working point to the differential output end.
Specifically, as shown in fig. 1, the input control unit 101 includes: the high-speed full-differential boost conversion circuit comprises a first inverter INV1, a second inverter INV2, a first NMOS transistor MN1 and a second NMOS transistor MN2, wherein an input end of the first inverter INV1 and an input end of the second inverter INV2 are used as differential input ends (Inp and Inn) of the high-speed full-differential boost conversion circuit to access the low-voltage differential input signal, an output end of the first inverter INV1 is connected to a gate of the first NMOS transistor MN1, a source of the first NMOS transistor MN1 is grounded, a drain of the first NMOS transistor MN1 is used as a first output end of the input control unit 101, an output end of the second inverter INV2 is connected to a gate of the second NMOS transistor MN2, a source of the second NMOS transistor MN2 is grounded, and a drain of the second NMOS transistor MN2 is used as a second output end of the input control unit 101; the working voltages of the first inverter INV1 and the second inverter INV2 are low power voltage. More specifically, the low power supply voltage is a full swing voltage, and the voltage range is 0-1.1V; in a specific application, the specific value of the low power voltage may be set according to actual requirements, and the low power voltage is 1.1V in this example.
Further, as shown in fig. 1, the input control unit 101 further includes: a third NMOS transistor MN3 and a fourth NMOS transistor MN4, the third NMOS transistor MN3 is connected in series between the drain of the first NMOS transistor MN1 and the first output terminal of the input control unit 101, the fourth NMOS transistor MN4 is connected in series between the drain of the second NMOS transistor MN2 and the second output terminal of the input control unit 101, and the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 are both connected to a bias voltage Vb, so that the third NMOS transistor MN3 and the fourth NMOS transistor MN4 both work in a saturation region, thereby controlling the current of the third NMOS transistor MN3, facilitating the charging and discharging of the differential output terminal, accelerating the speed of voltage rising and pulling down, and realizing the fast voltage rising and fast pulling down.
Specifically, as shown in fig. 1, the conversion output unit 102 includes: a first PMOS transistor MP1 and a second PMOS transistor MP2, wherein a source of the first PMOS transistor MP1 and a source of the second PMOS transistor MP2 are both connected to a high power voltage, a drain of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2 and serves as a differential output terminal of the high-speed fully-differential boost converter circuit, a gate of the first PMOS transistor MP1 is connected to the second output terminal of the input control unit 101, a drain of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 and serves as another differential output terminal of the high-speed fully-differential boost converter circuit, and a gate of the second PMOS transistor MP2 is connected to the first output terminal of the input control unit 101. In this example, the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected in a cross-coupled manner, which not only ensures the voltage rise of the low-voltage differential input signal, but also ensures the consistency of the rising edge of the high-voltage differential output signal. More specifically, the voltage range of the high power supply voltage is 1.1-3.3V; for a specific application, the specific value of the high power voltage may be set according to actual requirements, and the high power voltage is 2.5V in this example.
Further, as shown in fig. 1, the conversion output unit 102 further includes: the first resistor R1 and the second resistor R2, the first resistor R1 is connected in parallel to the source and drain terminals of the first PMOS transistor MP1, and the second resistor R2 is connected in parallel to the source and drain terminals of the second PMOS transistor MP 2. In this example, through the design of the first resistor R1 and the second resistor R2, the first PMOS transistor MP1 and the second PMOS transistor MP2 always have current, so as to accelerate the voltage raising speed and realize the rapid voltage raising.
Specifically, as shown in fig. 1, the offset mirroring unit 103 includes: a third PMOS transistor MP3 and a fourth PMOS transistor MP4, the third PMOS transistor MP3 is connected in series between the high power voltage and a differential output terminal of the high-speed fully differential boost converter circuit, the fourth PMOS transistor MP4 is connected in series between the high power voltage and another differential output terminal of the high-speed fully differential boost converter circuit, and the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the mirror control terminal of the bias setting module 200. In this example, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 mirror the dc operating point to the differential output terminals (Outp, Outn) of the high-speed fully-differential boost converter circuit through a mirror effect, so as to set the dc operating point of the high-voltage differential output signal.
As an example, as shown in fig. 1, the offset setting module 200 includes:
a bias setting unit 201, configured to set a magnitude of the dc operating point according to a preset voltage Vs and a preset resistance Rs;
and the bias generating unit 202 is connected to the output end of the bias setting unit 201, and is configured to generate the dc operating point according to the self-feedback of the operational amplifier, and introduce the dc operating point to the differential output end of the high-speed fully-differential boost converter circuit through a mirror effect.
Specifically, as shown in fig. 1, the offset setting unit 201 includes: the bias setting unit comprises a preset resistor Rs and a current source, wherein one end of the preset resistor Rs is connected to a preset voltage Vs, the other end of the preset resistor Rs is connected to one end of the current source and serves as an output end of the bias setting unit 201, and the other end of the current source is grounded. It should be noted that, in a specific application, the size of the dc operating point may be set according to actual requirements, and the voltage of the dc operating point is 1.8V in this example.
Specifically, as shown in fig. 1, the bias generating unit 202 includes: an operational amplifier OP, a third inverter INV3, a third resistor R3, a fifth PMOS transistor MP5, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, wherein a non-inverting input terminal of the operational amplifier OP is connected to an output terminal of the bias setting unit 201, an inverting input terminal of the operational amplifier OP is connected to a drain of the fifth PMOS transistor MP5 and a drain of the sixth NMOS transistor MN6, an output terminal of the operational amplifier OP is connected to a gate of the fifth PMOS transistor MP5 and serves as a mirror control terminal of the bias generating unit 202, a source of the fifth PMOS transistor MP5 is connected to a high power voltage, the third resistor R3 is connected in parallel to both ends of a source and a drain of the fifth PMOS transistor MP5, a source of the sixth NMOS transistor MN6 is connected to a drain of the fifth NMOS transistor MN5, a gate of the sixth NMOS transistor MN6 is connected to a bias voltage Vb, a source of the fifth NMOS transistor MN5 is grounded, and a gate of the fifth NMOS transistor MN5 is connected to an output terminal INV3 of the third NMOS transistor MN3, an input end of the third inverter INV3 is connected to a low level of the low power supply voltage. In this example, the operational amplifier OP is connected based on self-feedback, so that the voltage at the inverting input terminal is equal to the voltage at the non-inverting input terminal, that is, the voltage at the inverting input terminal is equal to the voltage at the dc operating point; and then, the direct current level of the high-voltage differential output signal generated by the differential output ends (Outp and Outn) is fixed at a direct current working point through the mirror image effect.
Referring to fig. 1, the operation of the high-speed fully-differential boost converter circuit of the present embodiment will be described; in this case, the low power supply voltage is 1.1V, the high power supply voltage is 2.5V, and the voltage of the dc operating point is 1.8V.
When the level of the differential input terminal Inp is switched from 0 → 1, and the level of Inn is switched from 1 → 0, the level output by the first inverter INV1 is 1 → 0, and the level output by the second inverter INV2 is 0 → 1, then the first NMOS transistor MN1 is turned off, and the second NMOS transistor MN2 is turned on; at this time, the gate voltage of the first PMOS transistor MP1 is pulled down rapidly through the second NMOS transistor MN2 and the fourth NMOS transistor MN4, the first PMOS transistor MP1 is turned on, and the second PMOS transistor MP2 is turned off; the level at the differential output terminal Outp is quickly raised to a high power voltage through the first PMOS transistor MP1, the first resistor R1 and the third NMOS transistor MN3, and the level of the differential output terminal Outn is quickly pulled down to ground through the second NMOS transistor MN2 and the fourth NMOS transistor MN 4.
When the level of the differential input terminal Inp is switched from 1 → 0, and the level of Inn is switched from 0 → 1, the level output by the first inverter INV1 is 0 → 1, the level output by the second inverter INV2 is 1 → 0, the first NMOS transistor MN1 is turned on, and the second NMOS transistor MN2 is turned off; at this time, the gate voltage of the second PMOS transistor MP2 is pulled low rapidly through the first NMOS transistor MN1 and the third NMOS transistor MN3, the second PMOS transistor MP2 is turned on, and the first PMOS transistor MP1 is turned off; the level at the differential output terminal Outn is quickly raised to a high power voltage through the second PMOS transistor MP2, the second resistor R2 and the fourth NMOS transistor MN4, and the level of the differential output terminal Outp is quickly pulled down to ground through the first NMOS transistor MN1 and the third NMOS transistor MN 3.
In this process, the offset setting module 200 sets a dc operating point, and fixes the dc level of the high-voltage differential output signal generated by the differential output terminals (Outp, Outn) at the dc operating point through a mirror effect.
In summary, the high-speed fully-differential boost converter circuit of the present invention can correctly boost and convert the low-voltage differential input signal received by the I/O interface into the high-voltage differential output signal for the internal chip to use; moreover, through the design of the third NMOS tube, the fourth NMOS tube, the first resistor and the second resistor, the rapid pull-down and lifting of the level can be realized, so that the level conversion speed of the high-speed fully-differential boost conversion circuit can even exceed 10 Gb/s. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A high-speed fully differential boost converter circuit, comprising:
the boost conversion module is used for carrying out voltage boost on the low-voltage differential input signal so as to generate a high-voltage differential output signal; and the offset setting module is used for setting the direct-current working point of the high-voltage differential output signal.
2. The high-speed fully differential boost converter circuit according to claim 1, wherein said boost converter module comprises:
the input control unit is used for generating a conversion control signal according to the low-voltage differential input signal;
the conversion output unit is connected between a high power supply voltage and the output end of the input control unit and used for performing voltage conversion according to the conversion control signal so as to generate the high-voltage differential output signal;
and the bias mirror image unit is connected between the high power supply voltage and the differential output end of the high-speed fully-differential boost conversion circuit and is used for mirroring the direct-current working point to the differential output end.
3. The high-speed fully-differential boost converter circuit according to claim 2, wherein said input control unit comprises: the input end of the first phase inverter and the input end of the second phase inverter are used as the differential input end of the high-speed fully differential boost conversion circuit, the output end of the first phase inverter is connected to the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is used as the first output end of the input control unit, the output end of the second phase inverter is connected to the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is used as the second output end of the input control unit; the working voltage of the first inverter and the second inverter is a low power supply voltage.
4. The high-speed fully-differential boost converter circuit according to claim 3, wherein said input control unit further comprises: the third NMOS tube is connected in series between the drain electrode of the first NMOS tube and the first output end of the input control unit, the fourth NMOS tube is connected in series between the drain electrode of the second NMOS tube and the second output end of the input control unit, and the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are both connected with bias voltage.
5. The high-speed fully-differential boost converter circuit according to claim 2, wherein said conversion output unit comprises: the high-speed full-differential boost conversion circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein a source electrode of the first PMOS tube and a source electrode of the second PMOS tube are both connected with a high power supply voltage, a drain electrode of the first PMOS tube is connected with a grid electrode of the second PMOS tube and serves as a differential output end of the high-speed full-differential boost conversion circuit, the grid electrode of the first PMOS tube is connected with a second output end of the input control unit, a drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube and serves as another differential output end of the high-speed full-differential boost conversion circuit, and a grid electrode of the second PMOS tube is connected with a first output end of the input control unit.
6. The high-speed fully-differential boost converter circuit according to claim 5, wherein said conversion output unit further comprises: the first resistor is connected in parallel to the two ends of the source and the drain of the first PMOS tube, and the second resistor is connected in parallel to the two ends of the source and the drain of the second PMOS tube.
7. The high-speed fully differential boost converter circuit according to claim 2, wherein said bias mirroring unit comprises: the third PMOS tube is connected in series between the high power supply voltage and one differential output end of the high-speed fully differential boost conversion circuit, the fourth PMOS tube is connected in series between the high power supply voltage and the other differential output end of the high-speed fully differential boost conversion circuit, and the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are both connected to the mirror image control end of the bias setting module.
8. The high-speed fully differential boost converter circuit according to claim 1, wherein said bias setting module comprises:
the bias setting unit is used for setting the size of the direct current working point according to a preset voltage and a preset resistor;
and the bias generating unit is connected to the output end of the bias setting unit and used for generating the direct current working point according to the self-feedback of the operational amplifier and mirroring the direct current working point to the differential output end of the high-speed fully-differential boost conversion circuit through mirroring.
9. The high-speed fully-differential boost converter circuit according to claim 8, wherein said bias setting unit comprises: the bias setting circuit comprises a preset resistor and a current source, wherein one end of the preset resistor is connected to preset voltage, the other end of the preset resistor is connected to one end of the current source and serves as an output end of the bias setting unit, and the other end of the current source is grounded.
10. The high-speed fully differential boost converter circuit according to claim 8, wherein said bias generating unit comprises: an operational amplifier, a third inverter, a third resistor, a fifth PMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, the non-inverting input end of the operational amplifier is connected to the output end of the bias setting unit, the inverting input end of the operational amplifier is connected to the drain electrode of the fifth PMOS tube and the drain electrode of the sixth NMOS tube, the output end of the operational amplifier is connected to the gate electrode of the fifth PMOS tube, and is used as a mirror control end of the bias generation unit, the source electrode of the fifth PMOS tube is connected with high power supply voltage, the third resistor is connected in parallel with two ends of the source electrode and the drain electrode of the fifth PMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with bias voltage, the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected to the output end of the third phase inverter, and the input end of the third phase inverter is connected to the low level of the low power supply voltage.
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| CN106849937A (en) * | 2016-12-20 | 2017-06-13 | 深圳市紫光同创电子有限公司 | A kind of level shifting circuit |
| WO2020057138A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | Full swing voltage conversion circuit and operation unit, chip, hashboard, and computing device using same |
| CN112423436A (en) * | 2020-12-17 | 2021-02-26 | 北京集创北方科技股份有限公司 | Power supply circuit and display device |
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