CN102231598A

CN102231598A - Power supply circuit

Info

Publication number: CN102231598A
Application number: CN2011101520211A
Authority: CN
Inventors: 周翔; 姚洪涛; 罗轶峰
Original assignee: Sany Heavy Industry Co Ltd
Current assignee: Sany Heavy Industry Co Ltd
Priority date: 2011-06-08
Filing date: 2011-06-08
Publication date: 2011-11-02
Anticipated expiration: 2031-06-08
Also published as: WO2012167673A1; CN102231598B

Abstract

The invention relates to the technical field of electronics and discloses a power supply circuit. The power supply circuit comprises an MOS (Metal Oxide Semiconductor) transistor and a bias control circuit; the source and the drain of the MOS transistor are connected between a power supply and a load in series; and the bias control circuit controls the bias state between the grid and the source of the MOS transistor according to a received power-on time sequence signal. The power supply circuit disclosed in the embodiment of the invention controls the bias state between the grid and the source of the MOS transistor by receiving an external pulse control signal (power-on time sequence signal) via the bias control circuit, namely, whether a power source supplies power to the load is controlled by the external control signal in order to ensure that the power source normally supplies power to the load. Moreover, by accessing a piezoresistor and a TVS (Transient Voltage Suppressor) transistor, the invention realizes the anti-access protection and transient protection functions of the power source with less elements.

Description

A kind of power circuit

Technical field

The present invention relates to electronic technology field, particularly relate to a kind of power circuit.

Background technology

In the electronic controller system; existing anti-reverse protective circuit is usually at the Control System Design of plate level; general power consumption is lower; electric current is less, utilizes unidirectional on state characteristic of diode or little electric current resettable fuse and the unidirectional on state characteristic of diode to finish jointly the reversal connection of power supply object power supply is protected.But for the plate level power supply system that high-power driving is provided for load, especially vehicle-mounted power driving power supply system, its supply voltage often is 24V, so the single line load current up to tens amperes, utilize single diode oppositely by characteristic exist the power consumption loss big, can't resist problems such as transient impact.The reversal connection protection that little electric current resettable fuse and diode are finished jointly then can't realize at all.And existing large power supply protection scheme is often at big current system specialized designs independent protection module, and volume is big usually, device is many, circuit complexity, the protection of the especially vehicle-mounted plate level of uncomfortable plywood level power power-supply power power-supply.

Therefore, how developing a kind of power circuit that is applicable to the especially vehicle-mounted power power-supply of plate level power power-supply, is the technical barrier that those skilled in the art need to be resolved hurrily.

Summary of the invention

In order to overcome the above-mentioned defective of prior art, the invention provides a kind of power circuit.This power circuit comprises metal-oxide-semiconductor (metal-oxide-semiconductor, the Metal-oxide-semicondutor field effect transistor) and bias control circuit, the source electrode of described metal-oxide-semiconductor and drain electrode are serially connected with between power supply and the load, and described bias control circuit is according to the bias state between the electrifying timing sequence signal controlling metal-oxide-semiconductor grid source that receives.

Preferably, described bias control circuit comprises first electric capacity, second electric capacity, first diode, second diode, the 3rd diode, biasing NMOS pipe and bias PMOS pipe; Biasing NMOS pipe links to each other with the grid of bias PMOS pipe and receives the input of electrifying timing sequence signal as input, biasing NMOS pipe links to each other as output with the drain electrode of bias PMOS pipe, this output is connected with an end of first electric capacity, the source electrode of bias PMOS pipe is connected in the anode with the positive source and first diode, the source electrode of biasing NMOS pipe is connected in the anode of the 3rd diode, and the negative electrode of the 3rd diode is connected in power cathode; The other end of first electric capacity is connected in the negative electrode of first diode and the anode of second diode, and an end of the negative electrode of second diode and second electric capacity is connected in the grid of metal-oxide-semiconductor, and the other end of second electric capacity is connected in positive source or negative pole.

Preferably, be connected with piezo-resistance between positive source and the power cathode.

Preferably, be connected with TVS pipe (Transient Voltage Suppressor, Transient Voltage Suppressor) between the drain electrode of metal-oxide-semiconductor and positive source or the negative pole.

Preferably, described metal-oxide-semiconductor is the N channel power MOS pipe, and its source electrode is connected in positive source, and drain electrode is connected in load.

Preferably, the negative electrode of described TVS pipe is connected in the drain electrode of metal-oxide-semiconductor, and the anode of described TVS pipe is connected in power cathode.

A kind of power circuit provided by the invention; receive external pulse control signal (electrifying timing sequence signal) by bias control circuit and control bias state between the metal-oxide-semiconductor grid source; whether is power power-supply is controlled by the external pulse control signal to the power supply state of load; with the guaranteed output power supply is the load normal power supply; in addition; in preferred version,, realize the reverse connecting protection and the transient protective function of power power-supply with few device by inserting piezo-resistance and TVS pipe.

Description of drawings

Figure 1 shows that the schematic diagram of a kind of power circuit that the embodiment of the invention provides;

Embodiment

In order to make those skilled in the art understand technical scheme of the present invention better, the present invention is described in further detail below in conjunction with the drawings and specific embodiments.Should be pointed out that only be explanation to the description of concrete structure and description order in this part, should not be considered as that protection scope of the present invention is had any restriction specific embodiment.

Please refer to Fig. 1, Figure 1 shows that the schematic diagram of a kind of power circuit that the embodiment of the invention provides.

As shown in the figure, a kind of power circuit of the embodiment of the invention comprises piezo-resistance R1, TVS pipe D2, N channel power MOS pipe U2 (conducting resistance is between a few milliohm to tens milliohms), biasing metal-oxide-semiconductor U3 and U4 (U3 is the bias PMOS pipe, and U4 is biasing NMOS pipe), the first diode D3, the second diode D4, the 3rd diode D5, first capacitor C 1 and second capacitor C 2; The positive polarity of power power-supply meets VCC, minus earth line GND; The annexation of this power circuit is as follows:

Piezo-resistance R1 is parallel between positive source VCC and the ground wire GND, the source S of N channel power MOS pipe U2 meets positive source VCC (the perhaps end of piezo-resistance R1), the drain D of N channel power MOS pipe U2 connects the negative electrode of TVS pipe D2, the other end of TVS pipe D2 is connected with ground wire GND (or end of load), the grid G of N channel power MOS pipe U2 connects the negative electrode of the second diode D4 and an end of second capacitor C 2, the other end of second capacitor C 2 is connected with ground wire GND (if U2 is the P channel power MOS pipe, then be connected) with positive source, one end of first capacitor C 1 links to each other with the negative electrode of the first diode D3 and the anode of the second diode D4 respectively, the grid of bias PMOS pipe U3 and biasing NMOS pipe U4 links to each other as the electrifying timing sequence signal (be external pulse control signal P) of input reception from the outside, and the drain electrode of bias PMOS pipe U3 and biasing NMOS pipe U4 links to each other and is connected in the other end of first capacitor C 1 as output; The source electrode of bias PMOS pipe U3 links to each other with the anode of first diode with positive source VCC, biasing NMOS pipe U4 links to each other with the anode of the 3rd diode D5, the negative electrode of the 3rd diode D5 links to each other with ground wire GND, wherein, bias PMOS pipe U3 and biasing NMOS pipe U4, the first diode D3, the second diode D4, the 3rd diode D5, first capacitor C 1 and second capacitor C, the 2 common bias control circuits that constitute N channel power MOS pipe U2.

In the course of the work, when power power-supply correctly connects, it is infinitely great that the resistance of piezo-resistance R1 can be thought, be in open circuit, at this moment, the diode-built-in conducting in advance of N channel power MOS pipe U2, biasing metal-oxide-semiconductor U3 and U4 can be logical at the effect lower whorl conductance of electrifying timing sequence signal (being external pulse control signal P), by first capacitor C 1, second capacitor C 2 are discharged and recharged, make the grid source normal bias of N channel power MOS pipe U2, thereby the drain-source passage of N channel power MOS pipe U2 is opened, for load provides the operate as normal power supply;

In the course of the work, when power power-supply is in the reversal connection state, the resistance of piezo-resistance R1 still is infinitely great, be in open circuit, at this moment, TVS pipe D2 is in conducting state, can't normal bias between the grid source of N channel power MOS pipe U2, the drain-source passage of N channel power MOS pipe U2 is in closed condition all the time, and the path of reverse electrical source is cut off, and load is exerted an influence avoiding;

In the course of the work; when power circuit is subjected to outside glitch (as thunderbolt, surge etc.); piezo-resistance R1 resistance value sharply reduces; make between positive source VCC and the ground wire GND and constitute the low impedance path; simultaneously; TVS pipe D2 (being generally more high-power) can sponge the transient energy of the overwhelming majority, thereby the protection load is not subjected to glitch.

Need to prove, in the foregoing description, the grid source bias state of N channel power MOS pipe U2 is subjected to the control of bias control circuit, and bias control circuit is to carry out corresponding operating according to receiving the external pulse control signal, be whether power power-supply is opened the power supply of load and controlled by the external pulse control signal, do not have power output in the time of so can guaranteeing to power in the power power-supply system, prevented the abnormal operation of powered on moment, the form of external pulse control signal can be set output by the control circuit outside the power circuit, to satisfy various control needs, in addition, above-mentioned bias control circuit is when the power power-supply reversal connection, also can make reverse bias between the grid source of N channel power MOS pipe U2, thereby the drain-source passage of N channel power MOS pipe U2 is remained on closed condition;

Need to prove, bias control circuit in the foregoing description also can adopt other circuit that can realize corresponding function to replace, and the circuit of being made up of bias PMOS pipe U3 and biasing NMOS pipe U4 in for example bigoted control circuit also can replace with the TTL circuit that can realize similar functions.

Need to prove that the foregoing description uses N to link up power MOS pipe U2, in other embodiments of the invention, also can use the P channel MOS tube, then its source electrode links to each other with ground wire GND, and drain electrode links to each other with load, the arrangement of its bias control circuit is similar to the above embodiments, does not give unnecessary details now.

A kind of power circuit that the embodiment of the invention provides; by electrifying timing sequence signal (external pulse control signal) control bias control circuit with realize N link up power MOS pipe the drain-source passage conducting and close; and by cooperating of piezo-resistance and TVS pipe; not only prevented the abnormal operation of power power-supply at powered on moment; also make power power-supply have the reverse connecting protection function when being in the reversal connection state, when being subjected to surge impact, have the transient protective function.

The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. power circuit, it is characterized in that, described power circuit comprises metal-oxide-semiconductor and bias control circuit, and the source electrode of described metal-oxide-semiconductor and drain electrode are serially connected with between power supply and the load, and described bias control circuit is according to the bias state between the electrifying timing sequence signal controlling metal-oxide-semiconductor grid source that receives.

2. power circuit as claimed in claim 1 is characterized in that, described bias control circuit comprises first electric capacity, second electric capacity, first diode, second diode, the 3rd diode, biasing NMOS pipe and bias PMOS pipe; Biasing NMOS pipe links to each other with the grid of bias PMOS pipe and receives the input of electrifying timing sequence signal as input, biasing NMOS pipe links to each other as output and is connected in an end of first electric capacity with the drain electrode of bias PMOS pipe, the source electrode of bias PMOS pipe is connected in the anode with the positive source and first diode, the source electrode of biasing NMOS pipe is connected in the anode of the 3rd diode, and the negative electrode of the 3rd diode is connected in power cathode; The other end of first electric capacity is connected in the negative electrode of first diode and the anode of second diode, and an end of the negative electrode of second diode and second electric capacity is connected in the grid of metal-oxide-semiconductor, and the other end of second electric capacity is connected in positive source or negative pole.

3. as the described power circuit of claim 1 to 2, it is characterized in that, be connected with piezo-resistance between positive source and the power cathode.

4. power circuit as claimed in claim 3 is characterized in that, is connected with the TVS pipe between the drain electrode of metal-oxide-semiconductor and positive source or the negative pole.

5. power circuit as claimed in claim 4 is characterized in that, described metal-oxide-semiconductor is the N channel power MOS pipe, and its source electrode is connected in positive source, and drain electrode is connected in load.

6. power circuit as claimed in claim 5 is characterized in that, the negative electrode of described TVS pipe is connected in the drain electrode of metal-oxide-semiconductor, and the anode of described TVS pipe is connected in power cathode.