CN114356013A

CN114356013A - Integrated electronic fuse circuit for preventing reverse current

Info

Publication number: CN114356013A
Application number: CN202210274462.7A
Authority: CN
Inventors: 杨国江; 王海波
Original assignee: Jiangsu Changjing Technology Co ltd
Current assignee: Jiangsu Changjing Technology Co ltd
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2022-04-15
Anticipated expiration: 2042-03-21
Also published as: CN114356013B

Abstract

An integrated electronic fuse circuit for preventing reverse current is characterized in that on the basis of a traditional electronic fuse efuse circuit, a control circuit comprising PMOS tubes PS1 and PS2, an NMOS tube NS, an output power NMOS tube Npower and a reverse current protection module for detecting the voltage of a power supply VIN and the output voltage VOUT is arranged, the reverse current protection module outputs control signals V +, V-and substrate potentials VS and VS2 to control the PS1, PS2, NS switches and the substrate potentials of the Npower, PS1 and PS2, the substrate potential of the Npower is switched to the lowest potential of the two, a body diode is formed for reverse bias, and reverse current is avoided.

Description

Integrated electronic fuse circuit for preventing reverse current

Technical Field

The invention relates to a power management chip of an integrated circuit, in particular to an integrated anti-reverse current electronic fuse circuit (efuse).

Background

As portable electronic products are widely used in various aspects of work and life, which put higher demands on the performance of power supplies, modern electronic systems adopt a high integration design to provide excellent performance and various functions. These systems use multiple voltage distribution to support various types of power supplies to ensure that the load is operating properly. One of the main desires is to minimize system downtime to any transient abnormal event, such as an overload or short circuit condition. For example, when a hot-swappable hard disk drive enters a storage system, the large inrush current can cause a voltage dip on the connecting bus and ultimately affect other operational loads on the same bus. To overcome this situation, today's system designers use protection devices to manage surge, overload, short circuit and overvoltage events, and protect sensitive loads, ensuring reliable operation of the system, the key requirement being to reduce the fault rate current within limits and to restore the system to an active state after the fault is cleared, without any manual intervention of the fault.

The electronic fuse efuse is an integrated power path protection device, and is used for limiting circuit current and voltage within a safe range. efuse is an "active circuit protection device" that integrates FETs to limit current and voltage to safe levels under fault conditions. It has embedded various functions to protect the system against inrush current, overcurrent, overvoltage, reverse current, reverse polarity and short circuit faults. Additionally efuses are more accurate, faster, and can "repair" themselves without user intervention.

Fig. 1 is a schematic diagram of a conventional electronic fuse efuse without reverse current protection, in which a diode connected in parallel with a power NMOS transistor is a parasitic body diode. It will not conduct when VCC > source voltage, but will conduct when VCC < source. Therefore, when the voltage at the output end is higher than that at the input end, the parasitic diode of the power NMOS tube is conducted to form a reverse current channel, and reverse current can flow through the system. If unrestricted, the current can damage the internal circuitry or the system power supply, and therefore a reverse current prevention device needs to be introduced to avoid such damage.

Several devices for preventing the output voltage from flowing backward are listed below.

Fig. 2(a) can block a reverse current by connecting diodes in series, using the unidirectional conduction characteristic of the diodes, but may cause severe power loss in the system due to an excessively high conduction voltage of the diodes, which may result in a reduction in system efficiency and battery life.

Fig. 2(b) is a more efficient external MOSFET with an ideal diode controller IC, where the diode in parallel with the MOSFET is a parasitic body diode. By detecting the input and output voltages, reverse connection prevention of the control switch tube is realized, and flexibility is provided in the current design. However, it takes up more system board space and does not provide as full protection as does efuse.

FIG. 2(c) is an eFuse that incorporates a blocking switch FET and a conduction tube pass FET, and a fast reverse comparator to provide reverse current blocking. The diode connected in parallel with each FET is a parasitic body diode, and two reverse diodes connected in series cannot be conducted by utilizing the unidirectional conduction characteristic of the diode, so that reverse current can be avoided by controlling the internal blocking FET under an abnormal condition. The internal blocking FET is activated and turned off (typically) when an input power failure condition is detected. Reverse current blocking helps multiplexing to simplify the design. And the conduction tube pass FET is controlled by an internal protection circuit to provide protection against overcurrent, overvoltage, undervoltage, temperature, short circuit and the like.

Fig. 3 is another conventional anti-reverse current efuse function circuit, in which two power NMOS transistors N1 and N2 are directly connected in series and gates are connected together and controlled by a gate control module. Parasitic body diodes of the two power NMOS are reversely connected, and because the diodes are in one-way conduction, series diodes in reverse connection cannot be conducted. VIN, VOUT, EN, dV/dt, gnd and RILIM in the circuit are all ports of the chip and are used for connecting components outside the chip. The internal function module comprises a charge pump, an overvoltage protection module, an enabling module, an undervoltage protection module, an output slope control module, a temperature protection module, a current-limiting protection module and a grid controller. In order to improve the driving capability of the power NMOS, a charge pump circuit is arranged in the chip to increase the VIN voltage and supply power to the gate controller. The overvoltage protection module detects the VIN voltage, and when the VIN voltage exceeds a rated high voltage value, a closing signal is output to the grid electrode for control, so that the power NMOS is closed. The enabling circuit detects the EN potential and is used for controlling the switch of the whole circuit to be started. The under-voltage protection also detects VIN, and is used for outputting a turn-off signal to the gate control to turn off the power NMOS when the input voltage is lower than the rated low voltage value. The temperature protection is used for detecting the temperature of the chip, and when the temperature exceeds the rated temperature, a closing signal is output to the grid electrode for control, so that the power NMOS is closed. The current-limiting protection circuit is used for detecting the output current of the power tube, when the output circuit exceeds a rated value, a closing signal is output to the grid control, the power NMOS is further closed, and the rated value of the current limiting of the current-limiting protection circuit can be used for setting resistance regulation through an external port RILIM. And (3) output slope control, namely setting a capacitance value through an external port dV/dt, adjusting the power-on rate of vout, and outputting a control signal to a grid electrode for control so as to control the output current of the power tube.

The disadvantage of the anti-reverse current efuse circuit shown in fig. 2(a), 2(b), 2(c) and 3 is that: two large power NMOS transistors are used, with their body diodes in reverse series to prevent back-flow. Because efuse is to realize large current capability, the on-resistance of the internal switch is generally less than 50 milliohm, and then the two serially connected NMOS transistors need the same area to realize low on-resistance, for example, to realize 30 milliohm, two NMOS power transistors of 15 milliohm need to be serially connected and added to realize low on-resistance, which consumes huge chip area and significantly increases chip volume and cost.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides the electronic fuse circuit (efuse) integrated with the reverse current prevention, which can reduce the area of a chip, is beneficial to the miniaturization and packaging of the chip, reduces the cost and is beneficial to large-scale popularization and application.

In order to realize the purpose, the invention adopts the following technical scheme: an integrated electronic fuse circuit for preventing reverse current is provided, a chip is provided with a power supply voltage port VIN, an output voltage port VOUT, a current-limiting resistor port RILIM, an enable port EN, an output voltage power-on slope control port dV/dt and a chip grounding port gnd, the chip comprises a charge pump circuit for increasing the voltage of the power supply VIN and supplying power to a grid controller, an overvoltage protection module for detecting whether the voltage of the power supply VIN exceeds a rated high voltage value, an enable module for detecting the potential of the EN, an undervoltage protection module for detecting whether the voltage of the power supply VIN is lower than the rated low voltage value, a temperature protection module for detecting the temperature of the chip, a current-limiting protection module for detecting the output current of a power tube, an output slope control module for adjusting the power-on rate of the output voltage VOUT so as to control the output current of the power tube, and a grid control circuit; the input end of the overvoltage protection module is connected with a power supply voltage port VIN, the input end of the enabling module is connected with an enabling port EN, the input end of the output slope control module is connected with a dV/dt port, and the input end of the current-limiting protection module is connected with a RILIM port; the output of the charge pump supplies power to the grid control circuit, and the output of the overvoltage protection module, the output of the enabling module, the output of the undervoltage protection module, the output of the output slope control module, the output of the temperature protection module and the output of the current-limiting protection module are all used as input signals of the grid control circuit;

the power supply protection circuit is characterized in that a control circuit comprising a PMOS tube PS1, a PMOS tube PS2, an NMOS tube NS, an output power NMOS tube Npower and a reverse current protection module for detecting the voltage of a power supply VIN and the output voltage VOUT is arranged, the source electrode of the PMOS tube PS2 and the drain electrode of the output power NMOS tube Npower are connected with a power supply voltage port VIN of a chip and a power supply voltage supply end VIN of the reverse current protection module, the drain electrode of the PMOS tube PS2 is connected with the source electrode of the PMOS tube PS1, the drain electrode of the NMOS tube NS and the grid electrode of the output power NMOS tube Npower, the substrate of the PMOS tube PS1 and the substrate of the PMOS tube PS2 are connected with a substrate potential VS2 output by the reverse current protection module, the drain electrode of the PMOS tube PS1 and the source electrode of the NMOS tube NS are connected with the output of a grid control circuit, the substrate of the NMOS tube NS is connected with a chip ground connection port gnd, the grid electrode of the PMOS tube PS2 and the grid electrode of the NMOS tube NS are connected with the voltage V output of the reverse current protection module, the output of the reverse current protection module, and the voltage V + of the output protection module of the PS tube 1 are connected with the reverse current protection module, the voltage VS output by the reverse current protection module is connected with the substrate of the output power NMOS tube Npower, and the reverse current protection module is connected with the source electrode of the output power NMOS tube Npower and is connected with an output voltage port VOUT of the chip;

the reverse current protection module comprises PMOS tubes P1-P12, NMOS tubes N1-N11 and resistors R1 and R2, the source and the substrate of the PMOS tube P2 are interconnected with the source and the substrate of the PMOS tube P3 and connected with the output end of the output voltage VOUT of the reverse current protection module, the source and the substrate of the PMOS tube P4 are interconnected with the drain of the PMOS tube P9 and the drain of the PMOS tube P11 and connected with the supply voltage supply end VIN of the reverse current protection module, the source and the substrate of the PMOS tube P5 are interconnected with the source and the substrate of the PMOS tube P8, the substrate of the PMOS tube P7 and the substrate of the PMOS tube P6 and connected with the output end of the substrate potential VS2 of the reverse current protection module, the grid and the drain of the PMOS tube P869 are interconnected with the grid of the PMOS tube P3 and the grid of the PMOS tube P4 and connected with the source and the substrate of the PMOS tube P1, the drain of the PMOS tube P3 is connected with the grid of the drain tube N2 and the grid of the NMOS tube N867 and the NMOS tube N4, a source of the NMOS tube N2 is connected to a drain of the NMOS tube N1 and a drain of the NMOS tube N3, a drain of the NMOS tube N4 is connected to a drain of the PMOS tube P4, a gate of the NMOS tube N4 and a gate of the NMOS tube N4, a source of the NMOS tube N4 is connected to a drain of the NMOS tube N4 and a drain of the NMOS tube N4, a source of the NMOS tube N4 is connected to a drain of the NMOS tube N4 and a source of the NMOS tube N4, a drain of the NMOS tube N4 is connected to a source of the PMOS tube P4, a gate of the NMOS tube N4, a gate of the PMOS tube P4, a gate of the NMOS tube N4 and a gate of the PMOS tube P4 and a drain of the PMOS tube P4 as a reverse current protection module output voltage V +, a drain and a drain of the PMOS tube P4, a drain of the PMOS tube P4 is connected to a drain of the PMOS tube N4, a drain of the PMOS tube P4, a drain protection module, a drain of the PMOS tube P4, a drain protection module is connected to a drain of the PMOS tube P4, a reverse current output resistor, a drain of the PMOS tube P4, a reverse current output resistor 4, a drain of the PMOS tube P4 is connected to a drain of the PMOS tube P4, a reverse current output module, a drain of the PMOS tube P4, a negative resistance of the PMOS tube P4, a negative resistance module 4, a negative resistance of the PMOS tube P4 is connected to a negative resistance module 4, a negative resistance, a, the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N10, the drain electrode of the NMOS tube N11, the grid electrode of the PMOS tube P9, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N1 and serves as the output end of the output voltage V & lt- & gt of the reverse current protection module, the source electrode and the substrate of the PMOS tube P9 are connected with the source electrode and the substrate of the PMOS tube P10 and serve as the output end of the output voltage VS, the source electrode and the substrate of the PMOS tube P11 are connected with the source electrode and the substrate of the PMOS tube P12 and serve as the output substrate potential VS2, the drain electrode of the PMOS tube P10 and the drain electrode of the PMOS tube P12 are connected with the output voltage VOUT, and the drain electrode of the PMOS tube P9 and the drain electrode of the PMOS tube P11 are connected with the input voltage VIN.

Further, the PMOS tube PS1 and the PMOS tube PS2 are enhancement type PMOS tubes; the NMOS transistor NS is an enhanced isolation NMOS transistor.

Furthermore, the PMOS tube P1 is an enhanced PMOS tube with an inverse size ratio, and the PMOS tubes P2-P12 are enhanced PMOS tubes; the NMOS transistors N1-N11 are enhancement type NMOS transistors.

Further, the PMOS transistor P2, the PMOS transistor P3 and the PMOS transistor P4 are the same in size; the NMOS transistor N2, the NMOS transistor N3, the NMOS transistor N4 and the NMOS transistor N5 are the same in size.

The invention has the advantages and obvious effects that: compared with the prior art, the invention only needs one power NMOS tube Npower and one substrate switching circuit, detects the VIN and VOUT voltages through the substrate switching circuit, switches the substrate potential to the lowest potential of the two, can form the body diode reverse bias, and avoids reverse current. And further, on the basis of realizing all the performances of the traditional electronic fuse efuse circuit, the chip area and the cost are obviously reduced. For example, in the same 30 milliohm efuse circuit, the traditional efuse circuit needs to be connected with two NMOS power tubes in series, and the total resistance is realized by adding two resistors in series, so that the resistance of each NMOS tube can only be 15 milliohms, and the occupied area is large. The invention can realize the function of preventing reverse current only by 1 NMOS transistor of 30 milliohms, and the performance of the capability of preventing reverse current and driving current is completely the same, so that the area of the power tube is saved by 3/4 compared with the traditional efuse circuit for preventing reverse current, namely the cost of the power tube is reduced to 1/4. By adding a small-scale substrate switching circuit, the scale of the reverse connection prevention efuse circuit can be remarkably reduced, the area reduction is favorable for the miniaturization packaging of a chip, and the cost reduction is favorable for large-scale popularization and application.

Drawings

Fig. 1 is a schematic diagram of a conventional electronic fuse efuse without reverse current protection.

Fig. 2(a) is a first prior art efuse circuit for preventing reverse current.

Fig. 2(b) is a second prior art efuse circuit for preventing reverse current.

FIG. 2(c) is a third prior art efuse circuit that prevents reverse current.

Fig. 3 is another conventional efuse circuit for preventing reverse current.

Fig. 4 is an efuse function circuit for preventing reverse current according to the present invention.

Fig. 5 is a specific circuit of the reverse current protection module according to the present invention.

Detailed Description

Referring to fig. 4, the electronic fuse efuse circuit diagram for preventing reverse current according to the present invention includes a conventional electronic fuse efuse circuit portion, where VIN, VOUT, RILIM, EN, dV/dt, and gnd are all ports of a chip for connecting components outside the chip, and functional modules inside the chip include a charge pump, an overvoltage protection module, an enable module, an undervoltage protection module, an output slope control module, a temperature protection module, a current-limiting protection module, and a gate controller. The dashed boxes in fig. 4 mark the content of the invention added to the prior art. The reverse current protection module is used for detecting VIN and VOUT signals and outputting substrate bias switching control signals V + and V-and substrate potentials VS and VS2 of the power NMOS transistor Npower. The PMOS tubes PS1 and PS2 are enhancement type PMOS tubes, and the NMOS tube NS is an enhancement type isolation NMOS tube. The PMOS tube PS1, the NMOS tube NS and the PMOS tube PS2 are used for controlling the potential of the Npower grid electrode of the power NMOS tube.

In order to improve the driving capability of the power NMOS transistor Npower, a charge pump circuit is arranged in the chip and used for increasing the VIN voltage and then supplying power to the grid controller. The overvoltage protection module detects VIN voltage, and when the VIN voltage exceeds a rated high voltage value, a closing signal is output to the grid electrode for control, so that the NMOS tube Npower is closed. The enabling module detects the EN potential and is used for controlling the switch of the whole circuit to be started. The undervoltage protection module is also used for detecting VIN and outputting a closing signal to the grid control when the input voltage is lower than the rated low voltage value so as to close the Npower of the power NMOS tube. The temperature protection module is used for detecting the temperature of the chip, and when the temperature exceeds the rated temperature, a closing signal is output to the grid electrode for control, so that the power NMOS tube Npower is closed. The current-limiting protection module is used for detecting the output current of the power tube, when the output circuit exceeds a rated value, a closing signal is output to the grid control, then the power NMOS tube Npower is closed, and the rated value of the current limiting of the power NMOS tube Npower can be regulated through a resistor which is externally connected with a current-limiting resistor port RILIM. And the output slope control module is used for setting a capacitance value through an external port dV/dt and adjusting the power-on rate of VOUT, and outputting a control signal to the grid electrode for control so as to control the output current of the power tube.

The connection relationship of the circuit of the present invention within the dashed box in fig. 4 is as follows: the control circuit comprises a PMOS tube PS1, a PMOS tube PS2, an NMOS tube NS, an output power NMOS tube Npower and a reverse current protection module for detecting the voltage of a power supply VIN and the output voltage VOUT, wherein the source electrode of the PMOS tube PS2 and the drain electrode of the output power NMOS tube Npower are connected with a power supply voltage port VIN of a chip and a power supply voltage supply end VIN of the reverse current protection module, the drain electrode of the PMOS tube PS2 is connected with the source electrode of the PMOS tube PS1, the drain electrode of the NMOS tube NS and the grid electrode of the output power NMOS tube Npower, the substrate of the PMOS tube PS1 and the substrate of the PMOS tube PS2 are connected with the substrate potential VS2 output by the reverse current protection module, the drain electrode of the PMOS tube PS1 and the source electrode of the NMOS tube NS are connected with the output of a grid electrode control circuit, the substrate of the NMOS tube NS is connected with a chip ground connection port gnd, the grid electrode of the PMOS tube PS2 and the NS grid electrode of the NMOS tube PS1 are connected with the voltage V + output by the reverse current protection module, and the grid electrode of the PMOS tube PS1 is connected with the voltage V + output by the reverse current protection module, the voltage VS output by the reverse current protection module is connected with the substrate of the output power NMOS tube Npower, and the reverse current protection module is connected with the source electrode of the output power NMOS tube Npower and connected with the output voltage port VOUT of the chip.

Referring to FIG. 5, the reverse current protection module includes PMOS transistors P1-P12, NMOS transistors N1-N11, and resistors R1 and R2, the source and substrate of PMOS transistor P2 are interconnected with the source and substrate of PMOS transistor P3 and serve as the output terminal of the reverse current protection module output voltage VOUT, the source and substrate of PMOS transistor P4 are interconnected with the drain of PMOS transistor P9 and the drain of PMOS transistor P11 and serve as the supply voltage supply terminal VIN of the reverse current protection module, the source and substrate of PMOS transistor P5 are interconnected with the source and substrate of PMOS transistor P8, the substrate of PMOS transistor P7 and the substrate of PMOS transistor P6 and serve as the output terminal of the substrate potential VS2 of the reverse current protection module, the gate and drain of PMOS transistor P2 are interconnected with the gate of PMOS transistor P3 and the gate of PMOS transistor P4 and with the source and substrate of PMOS transistor P1, the drain of PMOS transistor P3 is connected with the gate of NMOS transistor P2 and the gate of NMOS transistor N867 and the drain of NMOS transistor N4 and NMOS 4, a source of the NMOS tube N2 is connected to a drain of the NMOS tube N1 and a drain of the NMOS tube N3, a drain of the NMOS tube N4 is connected to a drain of the PMOS tube P4, a gate of the NMOS tube N4 and a gate of the NMOS tube N4, a source of the NMOS tube N4 is connected to a drain of the NMOS tube N4 and a drain of the NMOS tube N4, a source of the NMOS tube N4 is connected to a drain of the NMOS tube N4 and a source of the NMOS tube N4, a drain of the NMOS tube N4 is connected to a source of the PMOS tube P4, a gate of the NMOS tube N4, a gate of the PMOS tube P4, a gate of the NMOS tube N4, a gate of the PMOS tube P4 and a drain of the PMOS tube P4 are connected to a drain of the PMOS tube P4 and a drain of the PMOS tube P4, a reverse current protection module, a drain of the PMOS tube P4, a drain protection module is connected to a drain of the PMOS tube P4, a drain protection module, a drain of the PMOS tube P4, a drain protection module, a drain of the PMOS tube P4, a drain protection module, a drain of the PMOS tube P4, a drain protection module is connected to a drain of the PMOS tube P4, a drain protection module, a drain of the PMOS tube P4, a resistor, a drain of the PMOS tube P4, a drain protection module, a resistor, a drain protection module, a resistor, a, the drain of the PMOS tube P8 is connected with the drain of the NMOS tube N10, the drain of the NMOS tube N11, the gate of the PMOS tube P9, the gate of the PMOS tube P12 and the gate of the NMOS tube N1 and serves as the output end of the reverse current protection module output voltage V-, the source and the substrate of the PMOS tube P9 are connected with the source of the PMOS tube P10 and the substrate and are interconnected and connected with the output end of the output voltage VS of the resistor R2, the source and the substrate of the PMOS tube P11 are connected with the source of the PMOS tube P12 and the substrate and are interconnected with the source and the substrate of the PMOS tube P5, the source and the substrate of the PMOS tube P8, the substrate of the PMOS tube P7 and the substrate of the PMOS tube P6 are connected together to output the substrate potential VS2, and the drain of the PMOS tube P10 and the drain of the PMOS tube P12 are connected with the source and the substrate of the PMOS tube P2 and the source and the substrate of the PMOS tube P3 to output the voltage VOUT; the grid and the drain of the PMOS pipe P1 are interconnected and grounded gnd, and the sources and the substrates of the NMOS pipes N1, N3, N5, N6, N7, N10 and N11 are all interconnected and grounded gnd; the substrates of the NMOS transistors N2, N4, N8 and N9 are all grounded.

In fig. 5, the PMOS transistor PS1 and the PMOS transistor PS2 are enhancement PMOS transistors; the NMOS transistor NS is an enhanced isolation NMOS transistor. The PMOS tube P1 is an enhanced PMOS tube with inverse size ratio, and the PMOS tubes P2-P12 are enhanced PMOS tubes; the NMOS transistors N1-N11 are enhancement type NMOS transistors. The PMOS tube P2, the PMOS tube P3 and the PMOS tube P4 are the same in size; the NMOS transistor N2, the NMOS transistor N3, the NMOS transistor N4 and the NMOS transistor N5 are the same in size.

The operation principle of the invention combining fig. 4 and 5 is as follows: the output signals V + and V-and the potential VS and the substrate VS2 in the reverse current protection module are used to control the substrate potentials of the PS1, PS2, NS switches and the Npower, PS1 and PS2 in the anti-reverse circuit. P1 is an enhanced PMOS transistor with inverse size ratio, which is used as a high value linear resistor to provide bias current. As is well known, the grid source of the PMOS tube is connected, and the equivalent diode can be used as a current source to provide mirror current for the PMOS tubes connected with other grids. P2, P3, P4 were set to the same size, and N2, N3, N4, N5 were also the same size.

When VIN = VOUT, the P3, P4 currents are the same due to the mirroring effect of P2, while N2 and N3 are the same as the N4 and N5 currents due to the mirroring effect of N2 and N3 on N4 and N5. Thus P4 and N4 and N5 output an intermediate potential of about VIN/2.

When VIN > VOUT, the P3 bias current is unchanged, and neither N2 nor N3 nor their mirrored N4 and N5 currents are changed, since the gate-source voltage of P3 is unaffected. As is well known, the gate-source voltage of a MOS transistor increases, and the output current thereof increases; and vice versa. And P4 is due to VIN > VOUT, the absolute value | VSG | of the gate-source voltage difference is increased, so that the bias current of P4 is increased, the current of P4 is larger than the current of N4 and N5, and the drain of P4 outputs high potential VIN. Since P5, P6, P7, R1, N7, N8, N9, and R2 constitute an inverting schmitt trigger for shaping, V + outputs a low potential gnd. P8 and N10 form an inverter, and the output V-is high potential VS 2. While N11 is turned on, introducing a lag in positive feedback for P8 and N10. The V + low turns off N6 and the V-high turns on N1, introducing a positive feedback lag for the current comparison of P4 with N4 and N5. The voltage window provided by the two hysteresis circuits ensures that oscillations do not occur near the switching point. At the same time, the low potential of V + and the high potential of V-will cause P10 and P11 to turn on, P9 and P12 to turn off, and the output voltage VS = VOUT, VS2= VIN. Corresponding to VS = VOUT in fig. 4 for Npower, since VIN > VOUT, the body diode is reverse biased with respect to VIN, and no current flows from VIN to VOUT through the body diode by utilizing the unidirectional conduction characteristic of the diode. PS2 VS2= VIN, connected to the highest potential, no current flows from VIN to the Npower gate through the body diode. PS1 has VS2= VIN, connected to the highest potential, and NS has its substrate gnd connected to the lowest potential, and no current flows from the gate control module to the Npower gate through the body diode. Meanwhile, since V + is low and V-is high, PS2 is turned off, i.e., gates of VIN and Npower are turned off, and PS1 and NS are turned on, i.e., output signals of the gate control module are sent to Npower gates. Therefore, the efuse circuit always works normally under the control of the grid electrode and is not influenced by the reverse protection current module.

When VIN < VOUT, the P3 bias current is unchanged, and the N2 and N3, and their mirrored N4 and N5 currents are unchanged, since the gate-source voltage of P3 is not affected. And the P4 reduces the absolute value | VSG | of the gate-source voltage difference due to VIN < VOUT, resulting in the P4 bias current being reduced, so that the P4 current is smaller than the N4 and N5 currents, and the P4 drain outputs the low potential gnd. Since P5, P6, P7, R1, N7, N8, N9, and R2 constitute an inverting schmitt trigger for shaping, V + outputs a high potential VS 2. P8 and N10 form an inverter, the output V-is low gnd. While N11 was off, there was no effect on P8 and N10. The V + high turns on N6 and the V-low turns off N1, introducing a positive feedback lag for the current comparison of P4 with N4 and N5. The voltage window introduced by the hysteresis circuit ensures that oscillations do not occur near the switching point. At the same time, the high potential of V + and the low potential of V-will cause P10 and P11 to turn off, P9 and P12 to turn on, and the output voltage VS = VIN and VS2= VOUT. Corresponding to VS = VIN in fig. 4 for Npower, since VIN < VOUT, the body diode is reverse biased with respect to VOUT, taking advantage of the unidirectional turn-on characteristic of the diode, without current flowing from VOUT to VIN through the body diode. PS2 VS2= VOUT, tied to the highest potential, no current flows from VOUT to the Npower gate through the body diode. PS1 has VS2= VIN, connected to the highest potential, and NS has its substrate gnd connected to the lowest potential, and no current flows from the gate control module to the Npower gate through the body diode. Since V + is high VS2= VOUT and V-is low gnd, PS2 is turned on, i.e., VIN is connected to the gate of Npower, Npower is turned off because the gate is connected to the source, and no current flows from VOUT to VIN. And PS1 and NS are off, i.e., the output signal of the gate control module and the Npower gate are disconnected. Thus, the efuse circuit does not experience reverse current from VIN to VOUT due to the gate of Npower being turned off.

The invention only needs one power NMOS tube Npower and one additional substrate switching circuit, and the substrate switching circuit detects the voltage of VIN and VOUT, and switches the substrate potential to the lowest potential of the two, thus forming the body diode with reverse bias and avoiding reverse current. And further, on the basis of realizing all the performances of the traditional electronic fuse efuse circuit, the chip area and the cost are obviously reduced. Compared with the traditional electronic fuse efuse circuit, the power tube area is 3/4 saved compared with the traditional anti-reverse current efuse circuit, namely the cost of the power tube is reduced to 1/4. The area reduction is beneficial to the miniaturization and the packaging of the chip, and the cost reduction is beneficial to the large-scale popularization and application.

Claims

1. An integrated anti-reverse current electronic fuse circuit, a chip is provided with a power supply voltage port VIN, an output voltage port VOUT, a current limiting resistance port RILIM, an enable port EN, an output voltage power-on slope control port dV/dt and a chip grounding port gnd, the chip comprises a charge pump circuit, an overvoltage protection module, an enable module, an undervoltage protection module, a temperature protection module, a current-limiting protection module, an output slope control module and a grid control circuit, wherein the charge pump circuit is used for supplying power to the grid controller after the voltage of a power supply VIN rises, the overvoltage protection module is used for detecting whether the voltage of the power supply VIN exceeds a rated high voltage value, the enable module is used for detecting an EN potential, the undervoltage protection module is used for detecting whether the voltage of the power supply VIN is lower than a rated low voltage value, the temperature protection module is used for detecting the temperature of the chip, the current-limiting protection module is used for detecting the output current of a power tube, the output slope control module is used for adjusting the power-on rate of the output voltage VOUT so as to control the output current of the power tube; the input end of the overvoltage protection module is connected with a power supply voltage port VIN, the input end of the enabling module is connected with an enabling port EN, the input end of the output slope control module is connected with a dV/dt port, and the input end of the current-limiting protection module is connected with a RILIM port; the output of the charge pump supplies power to the grid control circuit, and the output of the overvoltage protection module, the output of the enabling module, the output of the undervoltage protection module, the output of the output slope control module, the output of the temperature protection module and the output of the current-limiting protection module are all used as input signals of the grid control circuit;

2. The integrated reverse current prevention electronic fuse circuit according to claim 1, wherein the PMOS transistors PS1 and PS2 are enhancement type PMOS transistors; the NMOS transistor NS is an enhanced isolation NMOS transistor.

3. The integrated reverse current prevention electronic fuse circuit according to claim 1, wherein the PMOS transistor P1 is an enhanced PMOS transistor with inverse size ratio, and the PMOS transistors P2-P12 are enhanced PMOS transistors; the NMOS transistors N1-N11 are enhancement type NMOS transistors.

4. The integrated anti-reverse current electronic fuse circuit according to claim 1 or 3, wherein the PMOS transistor P2, the PMOS transistor P3 and the PMOS transistor P4 are the same size; the NMOS transistor N2, the NMOS transistor N3, the NMOS transistor N4 and the NMOS transistor N5 are the same in size.