GB2356504A

GB2356504A - A high side FET switch with a charge pump driven by a relatively low voltage CMOS inverter

Info

Publication number: GB2356504A
Application number: GB0024553A
Authority: GB
Inventors: Reinhard Rieger
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1999-10-09
Filing date: 2000-10-06
Publication date: 2001-05-23
Anticipated expiration: 2020-10-06
Also published as: FR2799591A1; JP2001160745A; DE19950023A1; GB0024553D0; GB2356504B; FR2799591B1

Abstract

The gate of a high-side FET T3 is supplied by a charge pump D1,D2,C1. The charge pump is driven by a CMOS inverter T1,T2 controlled by a gated clock signal from a processor or from an oscillator comprising a Schmitt logic gate. The CMOS inverter has a 12 volt supply K2 and the charge pump has a 42 volt supply K1. Instead of a rectangular waveform, the charge pump may be driven by triangular, trapezoidal, sawtooth or sinusoidal waveforms. No high voltage transistors are required in the drive circuit. The circuit may be used in a vehicle.

Description

2356504 CONTROL DEVICE FOR ELECTRONIC SWITCHING MEANS The present

invention relates to a control device for electronic switching means for a load.

An electronic switch for temporary connecting of two terminals is described in DE-A-195 48 612. This switch comprises at least two electrically controllable switching elements, which are arranged in a line between the two terminals. At least one of the electrically controllable switching elements is a field effect transistor or other bidirectional component with an external or integrated overload switching- off facility.

Further, it is known to use relays or so-called smart-power blocks (PROFET's) for the electronic switching-on of loads in a 12 volt on-board mains of a vehicle. These blocks have only a limited usable range for voltage and current. For higher operating voltages, electronic switching is possible only by power semiconductors, which are provided with a gate driver stage to charge up the gate.

The gate driver stage can be a high-side switch, which is provided for switching of loads lying at one pole at ground, for example at vehicle bodywork. Such a switch, which is preferably an N-channel power MOSFET, lies between the operating voltage and the load and needs a gate voltage above the supply voltage of, for example, + 12 v for switching on. This gate voltage can be produced with use of a charge pump and an oscillator.

In addition, charge pumps according to the Greinacher principle are known for the 12 volt range. These function on the basis of a voltage doubling or voltage tripling, which is achieved by cascading of diode-capacitor combinations. In that case, in principle only integral multiples of the input voltage, reduced by the diode flow voltages, can be set.

Moreover, charge pumps which operate according to the bootstrap method are known.

According to the present invention there is provided a drive control device for a switch for the electronic switching of a load, wherein the switch comprises one or more field effect transistors arranged in series between an operating voltage source and the load, wherein a semi-bridge circuit and a charge pump are provided for generation of the gate voltage of the field effect transistors, the semi-bridge circuit has a clock signal input terminal and the charge pump has a first supply voltage terminal for a supply voltage of 42 volts.

2 Preferably, the first supply voltage supply terminal is connected by way of a first diode with a first terminal of a charging capacitor, the second terminal of which can be connected with the output of the circuit. In addition, the first terminal of the charging capacitor can be connected by way of a second diode with a first terminal of a storage capacitor, the first terminal of which can also be connected with the gate terminal of the field effect transistor. The second terminal of the storage capacitor is preferably connected with the first supply voltage terminal.

For preference, the clock signal input terminal is connected with the gate electrodes of two field effect transistors of the circuit, wherein one of these transistors is a high-side switch and the other transistor a low-side switch and the output of the circuit is provided between the two transistors. Expediently, the high-side switch is connected with a second supply voltage terminal for a second supply voltage of 12 volts and this second supply voltage can be tapped off at the output of the circuit when the high-side switch is conductive.

The clock signal input terminal can be connected with, for example, an output terminal of a processor or an output terminal of a pulse oscillator, the latter being, for example, a Schmitt trigger. In one embodiment, the oscillator is feed back-coup led NAND Schmitt trigger with an input for an activating signal.

Preferably, a rectangular, triangular, trapezium-shaped, sawtooth or sinusoidal output signal can be tapped off at the output of the circuit and preferably, also, the clock signal has a frequency in the order of magnitude of 100 kHz.

The drain terminal of the field effect transistor can be connected with a third supply voltage terminal, by way of which the field effect transistor is connected to a supply voltage of 42 volts.

By means of a control device embodying the invention a reduction in the number of necessary components and a reduction in the loading of the components may be able to be achieved by comparison with known devices, in which the potential of a storage capacitor charged up to 12 volts is increased by 42 volts. The components necessary for realisation of such a device are, for example, switching transistors suitable for 12 v, diodes suitable for 54 v and capacitors designed for 42 v. This means, for example, that by 3 comparison with known devices the necessity of high-voltage transistors is redundant and the latter can be replaced by a smaller number of cheaper low-signal transistors. Moreover, use of additional semiconductor valves for protection of the circuit is also not necessary.

An embodiment of the present invention will now be more particularly described by way of example with reference to the accompanying drawings, in which:

Fig. 1 is a schematic circuit diagram of a drive control device embodying the invention; and Fig. 2 is a diagram of a circuit for generation of a clock signal made available at an input terminal El of the circuit Fig. 1.

Referring now to the drawings there is shown a drive control device for an electronic switch for switching a load V, which is to be acted on with a supply voltage of 42 volts by way of the switch from the on-board mains of a motor vehicle, this supply voltage being applied to a connecting terminal K4.

The input switch comprises one or more field effect transistors T3, the drain-source paths of which are arranged between the connecting terminal K4 and the load V. In the case of the embodiment illustrated in Fig. 1, one field effect transistor of that kind is provided. The drain terminal D of this transistor is connected with the terminal K4 and the source terminal 3 is connected with the load V.

A sufficiently large voltage is required at the gate terminal G of the field effect transistor T3 for connecting it through or making it conductive and for maintaining the connectedthrough operation. This is produced with use of a drive control device, which comprises a halfbridge circuit HB and a charge pump L.

The drive control of the circuit HB is effected by a clock signal CK, which is made available to the circuit HB at an input terminal El. The clock signal CK is preferably a rectangular signal with a frequency in the order of magnitude of 100 kHz.

The clock signal CK is used for control of two field effect transistors T1 and T2, which alternately conduct and block.

4 A second supply voltage terminal K2, at which a supply voltage of 12 volts is present, is connected with the source electrode of the transistor T1, which is the high-side switch of the circuit HB. The source terminal of the transistor TZ which forms the low-side switch of the circuit HIB, lies at ground. The drain terminals of the two transistors T1 and T2 are connected together and form the output P1 of the circuit HB. An intermittent potential is produced at the circuit point or output PI through the alternating conductivity of the transistors T1 and T2.

When the transistor T2 is conductive, the circuit point P1 is applied to ground by way of the drain-source path of the transistor T2. A charging capacitor C1 of the pump L can thereby be charged up by way of a diode D1 to the supply voltage of 42 volts at the connecting terminal K1.

When the transistor T1 is conductive, the circuit point P1 is acted on, by way of the sourcedrain path of the transistor T1, by the second supply voltage of 12 volts present at the connecting terminal K2. This has the consequence that the diode D1 blocks and the charging capacitor C1 transfers its charge by way of the then-conductive diode D2 to the storage capacitor C2.

When next the transistor T2 is connected through, the circuit point P1 is again applied to ground by way of the transistor T2. The charging capacitor C1 is thereby again charged up by way of D1 to the supply voltage of 42 volts present at the terminal K1, wherein the diode D2 blocks.

If the transistor T2 is thereafter brought into the blocked state and the transistor T1 into the conductive state, a transfer of the charge stored in the charging capacitor C1 to the storage capacitor C2 takes place again.

The storage capacitor C2 is directly connected with the gate G of the field effect transistor T3. The consequence is that the voltage or potential at the gate G of the transistor T3 is raised to such an extent by the afore-described pumping up process that T3 is brought into the conductive state and held therein.

In the conductive state of the transistor T3 the supply voltage of 42 volts at the terminal K4 passes from the on-board mains of the motor vehicle to the load V, which is connected to the source terminal S of the field effect transistor T3.

By contrast to the known charge pumps, the charging capacitor C1 is charged up by way of the diode D1 to a supply voltage of 42 volts, less the forward voltage of the diode D1, when the transistor T2 is conductive. This voltage is then transferred to the charging capacitor C2 when the transistor T2 is blocked. By means of the pump L an increase in the voltage level at the storage capacitor C2 by a further 12 volts takes place thereafter, so that the voltage U2, which lies at the gate G of the transistor T3, relative to ground amounts to 42 v + 12 v = 54 v.

As the supply voltage of 42 volts lies at the source terminal of the transistor T3 when the transistor T3 is connected through, the potential difference between the drain and source electrodes of the transistor is sufficiently large in order to keep it in the conductive state, The clock signal CK present at the input terminal Ell can be provided by a processor, which is not shown. In addition, it is possible to generate the clock signal with use of a feed back-co upled inverting Schmitt trigger. If a feed back-cou pled NAND Schmitt trigger is used for generation of the clock signal CK as shown in Fig. 2, then the possibility exists of arranging generation of the clock signal by input of an activating or enable signal. In the form of clock signal generation shown in Fig. 2, the enable signal is fed to a first input of a NAND gate. This makes available the clock signal CK at its output, which is in turn coupled back to the second input of the NAND gate by way of a resistor Rt. The second input of the NAND gate is connected to ground by way of a capacitor Ct.

In the embodiment described above in conjunction with Fig. 1 it is advantageous, due to the large charging and discharging currents which flow by way of the diodes D1 and D2, to connect current-limiting resistors to the diodes.

Alternatively thereto the possibility exists of providing a constant signal for the voltage Us generated at the output P1 of the semi-bridge circuit HB, for example, a triangular, trapezium-shaped, sawtooth or sinusoidal signal. That requires the additional use of an operational amplifier, but has the advantage of saving charging resistors and reducing the loading of the diodes D1 and D2.

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Claims

A control device for electronic switching means in the form of a field effect transistor connected in series between a load and an operating voltage source for supplying operating voltage for the load, the device comprising a semi-bridge circuit and a charge pump for generating the gate voltage for the transistor, the circuit being controllable by a clock signal and the pump being operable with a 42 volt voltage supplied to an input thereof.
2. A device as claimed in claim 1, wherein the pump comprises a charging capacitor connected at one terminal thereof with a 42 volt voltage supply by way of a diode.
3. A device as claimed in claim 2, wherein the charging capacitor is connected at a further terminal thereof with an output of the circuit.
4. A device as claimed in claim 2 or claim 3, wherein the pump comprises a storage capacitor connected at a terminal thereof with said one terminal of the charging capacitor by way of a further diode.
5. A device as claimed in claim 4, wherein the storage capacitor is connected at said terminal thereof with the gate terminal of the transistor.
6. A device as claimed in claim 4 or claim 5, wherein the storage capacitor is connected at a further terminal thereof with the 42 volt voltage supply.
7. A device as claimed in any one of the preceding claims, wherein the circuit comprises two field effect transistors respectively coupled as a high-side switch and a lowside switch and has an output provided between the two transistors, each of the transistors being arranged to receive the clock signal at the gate terminal thereof.
8. A device as claimed in claim 7, wherein the transistor coupled as the high-side switch is connected with a 12 volt voltage supply and a voltage of 12 volts is provided at the circuit output when that transistor is conductive.

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9. A device as claimed in any one of the preceding claims, wherein the circuit is connectible to receive the clock signal from processing means.
10. A device as claimed in any one of claims 1 to 8, wherein the circuit is connectible to receive the clock signal from a pulse oscillator.
11. A device as claimed in claim 10, wherein the oscillator is a Schmitt trigger.
12. A device as claimed in claim 11, wherein the trigger is a feed ba ckcou pled NAND trigger with an input for an activating signal.
13. A device as claimed in any one of the preceding claims, wherein the circuit is arranged to provide a rectangular, triangular, trapeziumshaped, sawtooth or sinusoidal output signal.
14. A device as claimed in any one of the preceding claims, wherein the clock signal has a frequency of substantially 100 kilohertz.
A device as claimed in any one of the preceding claims, wherein the operating voltage source is a 42 volt source and the transistor connected between the load and that source is connected to the latter at the drain terminal of the transistor.
16. A control device substantially as hereinbefore described with reference to Fig. 1 of the accompanying drawings.
17. A device as claimed in claim 16 and substantially as hereinbefore described with reference to Fig. 2 of the accompanying drawings.