JP6939087B2 - Integrated circuit equipment - Google Patents

Description

The present invention relates to an integrated circuit device including a high withstand voltage element for synchronous rectification.

In a circuit that supplies power to an inductive load such as a motor with a high voltage, the terminals of the inductive load are connected to the power supply and the ground via semiconductor elements that can conduct bidirectionally. In this configuration, the commutation timing is detected by an external diode in order to shorten the dead time for avoiding that the semiconductor elements are turned on at the same time.

For this reason, in a configuration in which semiconductor elements are provided on the upper and lower arms, it is necessary to provide an external high withstand voltage diode corresponding to each semiconductor element. There is a problem of becoming.

Japanese Unexamined Patent Publication No. 2004-208407

The present invention has been made in consideration of the above circumstances, and an object of the present invention is an integrated circuit capable of detecting commutation timing without using an external diode for commutation detection and suppressing an increase in the number of parts. To provide the equipment.

The integrated circuit device according to claim 1 has a high-side element (2) to which a free-flowing diode (2a) is connected and a low-side element (3) to which a free-flowing diode (3a) is connected, thereby carrying an inductive load (3) from a midpoint. An integrated circuit device that drives and controls a power supply circuit that supplies and discharges power to 1), the high-side drive circuit (11) that gives a drive signal to the high-side element and the low-side drive circuit that gives a drive signal to the low-side element. (13), a level shift circuit (16) provided with a pair of level shift portions in which a level shift output resistor (19, 20), a switching element (17, 18) and a current limiting resistor (21, 22) are connected in series, and a level shift circuit (16). A displacement current that flows through a pair of switching elements of the level shift circuit during a period in which both the high-side element and the low-side element are turned off, which is caused by a change in the potential at the midpoint between the high-side element and the low-side element. A control circuit (12, 23, 31) that detects a current that charges and discharges the parasitic capacitance of the switching element and reverse-conducts the low-side element or the high-side element in which a current is flowing through the freewheeling diode. In the level shift circuit, a control signal for controlling the high side element is input to one of the switching elements of the pair of level shift units, and an inverted signal of the control signal is input to the other switching element. It is configured to output a signal for generating a drive signal of the high side element from a common connection point between the level shift output resistance of each of the pair of level shift units and the switching element.

By adopting the above configuration, it operates as follows. When the high-side element is turned off while a current is flowing from the power source to the inductive load via the high-side element, the current flows from the ground side by commutating to the freewheeling diode connected to the low-side element. At this time, the potential drops at the midpoint, which is the connection point between the high-side element and the low-side element, so that a displacement current flows through the parasitic capacitance between the drain and source of the switching element of the level shift circuit. The control circuit detects this displacement current from the terminal voltage of the level shift output resistor or current limiting resistor of the level shift circuit and turns on the low side element.

Similarly, when the low-side element is turned off while a current is flowing from the inductive load to the low-side element, the current flows to the power supply side by commutating to the freewheeling diode connected to the high-side element. At this time, the potential rises at the midpoint, which is the connection point between the high-side element and the low-side element, so that a displacement current flows through the parasitic capacitance between the drain and source of the switching element of the level shift circuit. The control circuit detects this displacement current from the terminal voltage of the level shift output resistor or current limiting resistor of the level shift circuit and turns on the high side element.

As a result, when the current flowing through the inductive load changes to flow through the freewheeling diode, the diode commutation timing is detected and the high-side element or low-side element is turned on to allow the current to flow, thereby reducing the loss due to the freewheeling diode. It can be reduced. As a result, it is not necessary to provide a high withstand voltage external diode for commutation detection, and an increase in the number of parts can be suppressed.

Electrical configuration diagram showing the first embodiment Time chart showing current, voltage and signal status of each part Electrical configuration diagram showing the second embodiment Time chart showing current, voltage and signal status of each part Electrical configuration diagram showing a third embodiment

(First Embodiment)
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
In FIG. 1, the circuit for supplying power to the coil 1 which is an inductive load has a configuration in which N-channel type MOSFETs 2 and 3 are connected in series and connected between both terminals of the high-voltage DC power supply 4. The MOSFET 2 is a high-side element, and the MOSFET 3 is a low-side element. One end of the coil 1 is connected with the common connection point of the MOSFETs 2 and 3 as the midpoint NP. Reflux diodes 2a and 3a are connected in antiparallel to MOSFETs 2 and 3, respectively. As the freewheeling diodes 2a and 3a, those built in the MOSFETs 2 and 3 may be used.

The high withstand voltage IC 5 as an integrated circuit device gives a gate signal to the MOSFETs 2 and 3 to perform on / off drive control. The high withstand voltage IC 5 includes nine terminals A to E and P to S. Here, the terminal E is connected to the ground together with the negative electrode terminal of the high-voltage DC power supply 4.

The high withstand voltage IC 5 is supplied with power from the DC power supply 6 via the terminals P and S to generate an internal power supply VD. The boosting capacitor 7 is connected between the terminals AC of the high withstand voltage IC5. The DC power supply 6 supplies power via the terminal P of the high withstand voltage IC 5. Further, the positive electrode terminal of the DC power supply 6 is connected to the terminal A via a diode 8 and a resistor 9 in series. The terminal C of the high withstand voltage IC 5 is connected to the midpoint NP. A high-side input signal INH is input from the PWM signal source PP to the terminal Q of the high withstand voltage IC 5, and a low-side input signal INL is input from the PWM signal source PN to the terminal R. The PWM signal sources PP and PN are input from a circuit such as an external ECU as PWM control signals in which high / low is inverted with respect to the high withstand voltage IC5.

Next, the internal configuration of the high withstand voltage IC 5 will be described. The high-side logic circuit 10 applies a gate voltage VGH from the terminal B to the gate of the MOSFET 2 via the drive circuit 11 based on a drive signal input from the outside. In the high-side logic circuit 10, two power supply terminals are connected between terminals A and C, and the terminal voltage of the capacitor 7 is given as a drive power supply.

In the high-side logic circuit 10, when signals OLSP and OLSN are given to the two input terminals, the signal OLSP is at a low level, and the signal OLSN is at a high level, a high-level gate voltage VGH is applied to the MOSFET 2 via the drive circuit 11. Give to the gate. Further, the high-side logic circuit 10 applies a low-level gate voltage VGH to the gate of the MOSFET 2 via the drive circuit 11 when the signal OLSP is at a high level and the signal OLSN is at a low level.

The low-side logic circuit 12, which also functions as a control circuit, applies a gate voltage VGL from the terminal D to the gate of the MOSFET 3 via the drive circuit 13 based on a drive signal input from the outside. The low-side logic circuit 12 includes a NAND circuit 12a, a one-shot pulse circuit 12b, and an OR circuit 12c, and an operating power supply is supplied from the internal power supply VD.

In the one-shot pulse circuit 12b, the trigger input terminal Tr is connected to the output terminal of the NAND circuit 12a, and the output terminal O is connected to one input terminal of the OR circuit 12c. The output terminal of the OR circuit 12c is connected to the terminal D via the drive circuit 13. The reset terminal Re of the one-shot pulse circuit 12b and the other input terminal of the OR circuit 12c are connected to the terminals R via the inverter circuits 14 and 15 in series, and the input signal INL on the low side is input.

The one-shot pulse circuit 12b outputs a high-level signal from the output terminal O for a certain period of time when the input signal INL of the reset terminal Re is low-level and the signal input to the trigger input terminal Tr becomes high-level. Further, when a high level signal is input to the reset terminal Re, the one-shot pulse circuit 12b resets the output signal of the output terminal O to a low level. The OR circuit 12c outputs a high-level gate signal VGL to the gate of the MOSFET 3 via the drive circuit 13 when either the output signal of the one-shot pulse circuit 12b or the low-side input signal INL is at a high level.

The level shift circuit 16 performs an operation of switching the operation level according to the high-side signal INH in order to switch the operation of the MOSFET 2 of the high-side logic circuit 10. The level shift circuit 16 includes N-channel type high withstand voltage MOSFETs 17 and 18 as two switching elements, and also includes level shift output resistors 19 and 20 and current limiting resistors 21 and 22. A series circuit of the level shift output resistor 19, MOSFET 17, and current limiting resistor 21 is connected between the terminal A and the terminal E. Similarly, a series circuit of the level shift output resistor 20, the MOSFET 18 and the current limiting resistor 22 is connected between the terminal A and the terminal E.

The common connection point between the source of the MOSFET 17 of the level shift circuit 16 and the current limiting resistor 21 outputs a voltage generated according to the operating state of the MOSFET 17 as a signal VSP. Similarly, the common connection point between the source of the MOSFET 18 and the current limiting resistor 22 outputs a voltage generated according to the operating state of the MOSFET 18 as a signal VSN. When the MOSFETs 17 and 18 are turned on, the signals VSP and VSN are at a high level due to the voltage generated by the current flowing through the current limiting resistors 21 and 22. A signal ILSP and a signal ILSN are given to the gates of the MOSFETs 17 and 18, respectively.

The common connection point between the drain of the MOSFET 17 of the level shift circuit 16 and the level shift output resistor 19 outputs a voltage generated according to the operating state of the MOSFET 17 as a signal OLSP. Similarly, the common connection point between the drain of the MOSFET 18 and the level shift output resistor 20 outputs a voltage generated according to the operating state of the MOSFET 18 as a signal OLSN. These signal OLSP and signal OLSN are input to the high-side logic circuit 10. When the MOSFETs 17 and 18 are turned on, the signals OLSP and OLSN are at a low level due to the voltage generated by the current flowing through the level shift resistors 19 and 20.

The level shift control circuit 23, which functions as a control circuit, drives and controls the level shift circuit 16 based on a drive signal input from the outside. The level shift control circuit 23 includes an AND circuit 23a, a one-shot pulse circuit 23b, and an OR circuit 23c, and an operating power supply is supplied from the internal power supply VD.

The signal VSS and the signal VSN are input from the level shift circuit 16 to the two input terminals of the AND circuit 23a, respectively. The signal VSS and the signal VSN are also input to the two input terminals of the NAND circuit 12a of the low-side logic circuit 12 described above. In the one-shot pulse circuit 23b, the trigger input terminal Tr is connected to the output terminal of the AND circuit 23a, and the output terminal O is connected to one of the input terminals of the OR circuit 23c. An input signal INH is input from the terminal Q to the reset terminal Re of the one-shot pulse circuit 23b and the other input terminal of the OR circuit 23c.

The output terminal of the OR circuit 23c is connected to the gate of the MOSFET 18 via the inverter circuit 24 and is connected to the gate of the MOSFET 17 via the inverter circuits 24 and 25. The output of the inverter circuit 24 is given to the gate of the MOSFET 17 as a signal ILSP, and the output of the inverter circuit 25 is given to the gate of the MOSFET 18 as a signal ILSN.

When the input signal INH of the reset terminal Re is at a low level and the signal input to the trigger input terminal Tr becomes high level, the one-shot pulse circuit 23b outputs a high level signal from the output terminal O for a certain period of time. Further, when a high level signal is input to the reset terminal Re, the one-shot pulse circuit 23b resets the output signal of the output terminal O to a low level.

In the OR circuit 23c, when either the output signal of the one-shot pulse circuit 23b or the high-side input signal INH is at a high level, the signal ILSP becomes a low level and the MOSFET 17 is turned off, and the signal ILSN becomes a high level. Then turn on the MOSFET 18. Further, in the OR circuit 23c, when both the output signal of the one-shot pulse circuit 23b and the high-side input signal INH are at a low level, the signal ILSP becomes a high level and the MOSFET 17 is turned on, and the signal ILSN becomes a low level. And turns off the MOSFET 18.

Next, the operation of the above configuration will be described with reference to the time chart of FIG. A current flows through the coil 1 constituting the inductive load such as a motor in either the forward direction or the reverse direction by the on / off control of the MOSFETs 2 and 3. Here, the direction indicated by the arrow in the figure in which the current flows from the midpoint NP side to the coil 1 side is the forward direction, and the direction in which the current flows from the coil 1 side to the midpoint NP side is the reverse direction.

In FIG. 2, (A) shows the direction of the current of the coil 1. In the first half including time t0 to t7, the current of the coil 1 is in the positive direction. When the MOSFET 2 is on, the current flows from the high-voltage DC power supply 4 side to the coil 1, and when the MOSFET 2 is off, the freewheeling diode 3a of the MOSFET 3 is pressed. Either the current flows from the ground side via the ground side, or the MOSFET 3 is turned on and becomes a reverse conduction state to flow from the ground side.

On the other hand, in the latter half of FIG. 2A including the times t8 to t17, in the case where the current of the coil 1 flows in the opposite direction, the current flows from the coil 1 to the ground side when the MOSFET 3 is on, and the MOSFET 3 moves. In the off state, either the current flows to the high-voltage DC power supply 4 side via the freewheeling diode 2a of the MOSFET 2 or the MOSFET 2 turns on and becomes a reverse conduction state and flows to the high-voltage DC power supply 4 side.

FIG. 2B shows an input signal INL for turning on the low-side MOSFET 3 by the PWM signal. On the other hand, FIG. 2C shows an input signal INH for turning on the high-side MOSFET 2 by the PWM signal. The input signals INL and INH are signals that turn on the low-side MOSFET 3 and the high-side MOSFET 2 alternately with a dead time in between.

Next, with respect to the current direction of the current IL of the coil 1, the signal change and operation of each part due to the change of the input signals INL and INH will be described. First, in FIG. 2, immediately before time t0, as shown in FIGS. 2 (B) and 2 (C), both the input signals INL and INH have a dead time at a low level. In the state where the MOSFET 3 before the dead time is on, the coil current IL flows to the coil 1 side via the MOSFET 3, and the MOSFET 3 is off during the dead time period, so that the coil current IL is the freewheeling diode 3a. It becomes a state of flowing through.

Further, in the state where the coil current IL is flowing to the coil 1 side via the MOSFET 3 or the freewheeling diode 3a in this way, the potential of the midpoint NP is a voltage that is lower than the ground level by the forward voltage of the freewheeling diode 3a. Since then, it is almost at the ground level. Therefore, in this state, the capacitor 7 is charged from the DC power supply 6 via the diode 8 and the resistor 9, and the voltage of the DC power supply 6 is applied to the terminal A.

Then, when the dead time ends and the input signal INH changes to a high level at time t0, the high level signal is output by the OR circuit 23c of the level shift control circuit 23. As a result, as shown in FIG. 2D, the signal ILSP output via the inverter circuits 24 and 25 becomes a high level, and the MOSFET 17 shifts to the on state. On the other hand, as shown in FIG. 2E, the signal ILSN output via the inverter circuit 24 becomes low level, and the MOSFET 18 shifts to the off state.

When the MOSFET 17 is turned on at time t0, the terminal voltage VSS of the current limiting resistor 21 changes to a high level as shown in FIG. 2 (F), and the level shift output is shown as shown in FIG. 2 (H). The terminal voltage OLSP of the resistor 19 changes to a low level. Further, when the MOSFET 18 is turned off at time t0, the terminal voltage VSN of the current limiting resistor 22 changes to a low level as shown in FIG. 2 (G), and the level changes as shown in FIG. 2 (I). The terminal voltage OLSN of the shift output resistor 20 changes to a high level.

As a result, at time t1, as shown in FIG. 2 (L), in the high-side logic circuit 10, a high-level gate signal VGH is output to the gate of the MOSFET 2 and turned on. As the MOSFET 2 shifts to the on state, the potential of the midpoint NP rises to the voltage VH of the high-voltage DC power supply 4 from time t1 to time t2, as shown in FIG. 2 (J).

Then, the potential of the midpoint NP rises from the time t1 so that the displacement current flows through the MOSFETs 17 and 18 via the capacitor 7, the terminal A, and the level shift output resistors 19 and 20. In the MOSFETs 17 and 18, a displacement current for charging the parasitic capacitance between the drain and the source flows, so that a voltage drop of the level shift output resistor 20 occurs at time t1, and the terminal voltage OLSN as shown in FIG. 2 (I). Changes to a low level, and the terminal voltage VSN of the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G).

As a result, both the terminal voltages VSP and VSN of the current limiting resistors 21 and 22 become high level, so that the AND circuit 23a outputs a high level signal in the level shift control circuit 23. However, in the one-shot pulse circuit 23b, since the high-level input signal INH is input to the reset terminal Re at this point, the output terminal O is in a state of outputting a low-level signal.

Further, when the midpoint NP rises to the vicinity of the voltage VH of the high-voltage DC power supply 4, the terminal C also rises to the vicinity of the voltage VH. At this time, a boost voltage obtained by adding the voltage between the terminals of the capacitor 7 to the voltage VH, that is, the voltage of the DC power supply 6 is applied to the terminal A. As a result, a state in which a voltage close to the voltage of the DC power supply 6 is applied is maintained between the terminals A and C.

After that, when the charging of the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 is completed, the displacement current becomes zero. At this time, since the MOSFET 18 is in the off state, at time t2, the terminal voltage VSN of the current limiting resistor 22 changes to a low level as shown in FIG. 2 (G), and as shown in FIG. 2 (I). , The terminal voltage OLSN of the level shift output resistor 20 changes to a high level.

Therefore, when the coil current IL is flowing in the positive direction, the MOSFET 2 is turned on at time t1 because the input signal INH changes to a high level at time t0, which was flowing through the freewheeling diode 3a. The coil current IL changes so as to flow from the high-voltage DC power supply 4 side.

Next, the operation when the input signal INH changes from the high level to the low level at time t3 will be described. As shown in FIG. 2C, when the input signal INH changes from high level to low level at time t3, the OR circuit 23c of the level shift control circuit 23 also changes the input signal from the one-shot pulse circuit 23b to low level. Because there is, it outputs a low level signal. As a result, as shown in FIG. 2D, the signal ILSP output via the inverter circuits 24 and 25 becomes low level, and the MOSFET 17 shifts to the off state. On the other hand, as shown in FIG. 2 (E), the signal ILSN output via the inverter circuit 24 becomes high level, and the MOSFET 18 shifts to the on state.

When the MOSFET 17 is turned off at time t3, the terminal voltage VSS of the current limiting resistor 21 changes to a low level as shown in FIG. 2 (F), and the level shift output is shown as shown in FIG. 2 (H). The terminal voltage OLSP of resistor 19 changes to a high level. Further, when the MOSFET 18 is turned on at time t3, the terminal voltage VSN of the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G), and the level changes as shown in FIG. 2 (I). The terminal voltage OLSN of the shift output resistor 20 changes to a low level.

As a result, as shown in FIG. 2 (L), in the high-side logic circuit 10, a low-level gate signal VGH is output to the gate of the MOSFET 2 at time t4 to turn it off. When the MOSFET 2 is turned off, the coil current IL continues to flow, so that commutation to the freewheeling diode 3a occurs, and the coil current IL flows through the freewheeling diode 3a. Then, when the MOSFET 2 shifts to the off state, as shown in FIG. 2 (J), the potential of the midpoint NP changes from the voltage VH of the high-voltage DC power supply 4 to the forward voltage of the freewheeling diode 3a from time t4 to time t5. It will drop to a negative potential by Vf.

Then, as the potential of the midpoint NP drops from the time t4, the charge of the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 is displaced via the level shift output resistors 19 and 20, the terminal A, and the capacitor 7. Current will flow. As a result, a voltage drop of the level shift output resistor 20 occurs at time t4, the terminal voltage OLSN changes to a high level as shown in FIG. 2 (I), and the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G). The terminal voltage VSN changes to a low level.

When both the terminal voltages VSP and VSN of the current limiting resistors 21 and 22 become low level, the NAND circuit 12a outputs a high level signal in the low side logic circuit 12. At this time, in the one-shot pulse circuit 12b, the low-level input signal INL is input to the reset terminal Re, so that the output terminal O outputs a high-level signal.

As a result, a high-level signal is output from the OR circuit 12c, and as shown in FIG. 2 (K), a high-level gate signal VGL is output to the gate of the MOSFET 3 via the drive circuit 13 at time t5. As a result, the MOSFET 3 is turned on at time t5, and the coil current IL flowing through the freewheeling diode 3a now flows through the MOSFET 3 in the on state, and the diode loss is eliminated.

Further, when the displacement currents of the MOSFETs 17 and 18 disappear at time t5 and the potential of the midpoint NP reaches a voltage −Vf which is lowered by the forward voltage of the diode from the ground level, the MOSFET 18 is in the ON state, so that the time t5 Then, as shown in FIG. 2 (G), the terminal voltage VSN of the current limiting resistor 22 changes to a low level, and as shown in FIG. 2 (I), the terminal voltage OLSN of the level shift output resistor 20 changes to a high level. Change.

After that, as shown in FIG. 2B, the dead time ends at time t6, the input signal INL changes to a high level, and a high level signal is input to the OR circuit 12c in the low side logic circuit 12 at time t7. Will be done. However, until this point is reached, the one-shot pulse circuit 12b outputs a high-level signal for a certain period of time even if the input signal from the input terminal Tr changes to a low level. As a result, as shown in FIG. 2 (K), since the high-level gate signal VGL is continuously applied to the gate of the MOSFET 3, the MOSFET 3 is kept in the ON state.

Therefore, when the MOSFET 2 changes from the on state to the off state at time t4 while the coil current IL is flowing in the positive direction, the charge charged to the parasitic capacitance between the drain and source of the MOSFETs 17 and 18 is charged. The MOSFET 3 can be turned on at time t5 by the displacement current due to the discharge. As a result, the commutation timing to the freewheeling diode 3a can be detected, and the flow to the freewheeling diode 3a is avoided during the dead time between the time t5 and the time t7 (the shaded area in FIG. 2 (K)). Therefore, the diode loss can be reduced by flowing in the opposite direction by the MOSFET 3 in the on state.

Next, unlike the period up to time t7, the operation in the state after time t8 will be described. Immediately before and after time t8, the current direction of the current IL of the coil 1 is in the opposite direction to the above case, that is, from the coil 1 side to the midpoint NP side. Here, immediately before the time t8, the MOSFET 3 is in the ON state, and the coil current IL is flowing from the coil 1 to the ground side through the MOSFET 3.

The operation when the input signal INL changes from the high level to the low level at time t8 will be described. As shown in FIG. 2B, when the input signal INL changes from high level to low level at time t8, the OR circuit 12c of the low side logic circuit 12 outputs a low level signal. As a result, as shown in FIG. 2 (K), a low-level gate signal VGL is given from the drive circuit 13 to the gate of the MOSFET 3 at time t9, and the MOSFET 3 shifts to the off state.

When the MOSFET 3 is turned off, the coil current IL continues to flow, so that commutation to the freewheeling diode 2a occurs, and the coil current IL flows to the high-voltage DC power supply 4 side through the freewheeling diode 2a. Then, as the MOSFET 3 shifts to the off state, as shown in FIG. 2 (J), the potential of the midpoint NP rises from the vicinity of the ground level to the voltage VH of the high-voltage DC power supply 4 from time t9 to time t10. become.

Then, the potential of the midpoint NP rises from the time t9, so that the displacement current flows through the MOSFETs 17 and 18 via the capacitor 7, the terminal A, and the level shift output resistors 19 and 20. In the MOSFETs 17 and 18, a displacement current for charging the parasitic capacitance between the drain and the source flows, so that a voltage drop of the level shift output resistor 19 occurs at time t9, and the terminal voltage OLSP as shown in FIG. 2 (H). Changes to a low level, and the terminal voltage VSP of the current limiting resistor 21 changes to a high level as shown in FIG. 2 (F).

As a result, both the terminal voltages VSP and VSN of the current limiting resistors 21 and 22 become high level, so that the AND circuit 23a outputs a high level signal in the level shift control circuit 23. In the one-shot pulse circuit 23b, since the low-level input signal INH is input to the reset terminal Re, the high-level signal is output from the output terminal O for a certain period of time.

As a result, the level shift circuit 16 is turned on by giving a high-level gate signal ILSP to the gate of the MOSFET 17 at time t9 as shown in FIG. 2 (D), and as shown in FIG. 2 (E), the level shift circuit 16 operates. A low-level gate signal ILSN is given to the gate of the MOSFET 18 to operate off. As a result, as shown in FIG. 2 (H), the output signal OLSP of the level shift output resistor 19 becomes low level at time t9, and as shown in FIG. 2 (I), the output signal OLSN of the level shift output resistor 20 becomes low level. The low level is maintained. In the high-side logic circuit 10, the high-level output signal OLSP and the low-level output signal OLSN output a high-level gate signal VGH at time t10, as shown in FIG. 2 (L). As a result, the MOSFET 2 is operated in the ON state, and the coil current IL flowing through the freewheeling diode 2a flows to the high-voltage DC power supply 4 side through the MOSFET 2.

Further, when the displacement currents of the MOSFETs 17 and 18 disappear at time t10 and the potential of the midpoint NP reaches the voltage VH, the MOSFET 18 is in the off state. Therefore, at time t10, the current is as shown in FIG. 2 (F). The terminal voltage VSN of the limiting resistor 22 changes to a low level, and as shown in FIG. 2H, the terminal voltage OLSN of the level shift output resistor 20 changes to a high level.

After that, as shown in FIG. 2B, the dead time ends at time t11, the input signal INH changes to a high level, and at time t12, a high level signal is sent to the OR circuit 23c in the level shift control circuit 23. Entered. However, until this point is reached, the one-shot pulse circuit 23b outputs a high-level signal for a certain period of time even if the input signal from the input terminal Tr changes to a low level. As a result, as shown in FIG. 2 (L), the gate of the MOSFET 2 is continuously given a high-level gate signal VGH, so that the MOSFET 2 is kept in the ON state.

Therefore, when the MOSFET 3 changes from the on state to the off state at time t8 while the coil current IL is flowing in the opposite direction from the coil 1, the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 is charged. The displacement current allows the MOSFET 2 to be turned on at time t10. Thereby, the commutation timing to the freewheeling diode 2a can be detected, and the diode loss is reduced by avoiding the flow to the freewheeling diode 2a during the dead time between the time t10 and the time t12 and flowing through the MOSFET2. You will be able to.

After that, as shown in FIG. 2C, when the input signal INH changes from high level to low level at time t13, it is output via the inverter circuits 24 and 25 as shown in FIG. 2D. The signal ILSP goes low and the MOSFET 17 goes off. Further, as shown in FIG. 2E, the signal ILSN output via the inverter circuit 24 becomes high level, and the MOSFET 18 shifts to the on state.

When the MOSFET 17 is turned off at time t13, the terminal voltage VSS of the current limiting resistor 21 changes to a low level as shown in FIG. 2 (F), and the level shift output is shown as shown in FIG. 2 (H). The terminal voltage OLSP of resistor 19 changes to a high level. Further, when the MOSFET 18 is turned on at time t13, the terminal voltage VSN of the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G), and the level changes as shown in FIG. 2 (I). The terminal voltage OLSN of the shift output resistor 20 changes to a low level.

As a result, at time t14, as shown in FIG. 2 (L), in the high-side logic circuit 10, a low-level gate signal VGH is output to the gate of the MOSFET 2 to turn it off. When the MOSFET 2 is turned off, the dead time period is reached, and the coil current IL flowing in the opposite direction through the MOSFET 2 flows through the freewheeling diode 2a. Here, the potential of the midpoint NP is slightly lowered by the coil current IL flowing through the freewheeling diode 2a, but since the potential close to the voltage VH is maintained with almost no change, no displacement current is generated.

After that, when the dead time ends and the input signal INL changes to a high level at time t15, the high level signal is output by the OR circuit 12c of the low side logic circuit 12. As a result, at time t16, the low-side logic circuit 12 outputs a high-level gate signal VGL to the gate of the MOSFET 3 to turn it on. As the MOSFET 3 shifts to the on state, the potential of the midpoint NP drops from the voltage VH to the ground level from time t16 to time t17, as shown in FIG. 2 (J).

Then, the potential of the midpoint NP drops from the time t16, and the charge charged to the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 via the level shift output resistors 19, 20, the terminal A, and the capacitor 7. Displacement current that discharges the current will flow. As a result, a voltage drop of the level shift output resistor 20 occurs at time t17, the terminal voltage OLSN changes to a high level as shown in FIG. 2 (I), and the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G). The terminal voltage VSN changes to a low level.

After that, when the discharge of the charge charged in the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 is completed, the displacement current becomes zero. At this time, since the MOSFET 18 is in the ON state, at time t17, the terminal voltage VSN of the current limiting resistor 22 changes to a high level as shown in FIG. 2 (G), and as shown in FIG. 2 (I). , The terminal voltage OLSN of the level shift output resistor 20 changes to a low level.

Therefore, when the coil current IL is flowing in the opposite direction, the one flowing through the freewheeling diode 2a is turned on at time t16 because the input signal INL changes to a high level at time t15. It changes to flow.

According to this embodiment, the potential of the midpoint NP to which the coil 1 is connected changes during the switching operation of the MOSFETs 2 and 3, and the level shift circuit 16 is displaced to the high withstand voltage MOSFETs 17 and 18. The state where the current flows is detected. As a result, the diode commutation timing can be detected without providing a diode for high withstand voltage in each of the energization directions of the coil 1, and the MOSFETs 2 and 3 can be prevented from being short-circuited vertically during the dead time period. The period of flow through the freewheeling diodes 2a and 3a can be shortened to reduce the loss.

Further, according to the above embodiment, the diode transfer of the low-side MOSFET 3 and the freewheeling diode 3a is performed by monitoring the terminal voltages VSP and VSN of the current limiting resistors 21 and 22 connected to the high withstand voltage MOSFETs 17 and 18 of the level shift circuit 16. Since the flow timing is detected, it can be realized with a simple configuration.

Further, according to the above embodiment, the terminal voltages VSS and VSS of the current limiting resistors 21 and 22 connected to the high withstand voltage MOSFETs 17 and 18 of the level shift circuit 16 are monitored, and the level shift circuit 16 is operated by the level shift control circuit 23. Since the diode commutation timing of the high-side MOSFET 2 and the freewheeling diode 2a is detected by driving the circuit, the high-side MOSFET 2 and the freewheeling diode 2a can be quickly operated with a simple configuration.

(Second Embodiment)
3 and 4 show the second embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the high withstand voltage IC 30 is provided with a high-side logic circuit 31 that also functions as a control circuit instead of the high-side logic circuit 10 and the level shift control circuit 23.

That is, in FIG. 3, an input signal INH is given to the gate of the MOSFET 17 of the level shift circuit 16 as a signal ILSP via the terminals Q and the inverter circuits 24 and 25. An input signal INH is given to the gate of the MOSFET 18 as a signal ILSN via the terminal Q and the inverter circuit 24.

Further, the high-side logic circuit 31 applies a gate voltage VGH from the terminal B to the gate of the MOSFET 2 via the drive circuit 11 based on a drive signal input from the outside. The high-side logic circuit 31 includes a NAND circuit 31a, a one-shot pulse circuit 31b, and an OR circuit 31c, and an operating power supply is supplied by the voltage between the terminals of the capacitor 7.

The signal OLSP and the signal OLSN, which are the terminal voltages of the level shift output resistors 19 and 20 of the level shift circuit 16, are input to the two input terminals of the NAND circuit 31a. In the one-shot pulse circuit 31b, the trigger input terminal Tr is connected to the output terminal of the NAND circuit 31a, and the output terminal O is connected to one input terminal of the OR circuit 31c. The output terminal of the OR circuit 31c is connected to the terminal B via the drive circuit 11. A high-side input signal INH is input from the terminal Q to the reset terminal Re of the one-shot pulse circuit 31b and the other input terminal of the OR circuit 31c via the inverter circuits 24 and 25 in series.

When the input signal INH of the reset terminal Re is at a low level and the signal input to the trigger input terminal Tr becomes high level, the one-shot pulse circuit 31b outputs a high level signal from the output terminal O for a certain period of time. Further, when a high level signal is input to the reset terminal Re, the one-shot pulse circuit 31b resets the output signal of the output terminal O to a low level. The OR circuit 31c outputs a high-level gate signal VGH to the gate of the MOSFET 2 via the drive circuit 11 when either the output signal of the one-shot pulse circuit 31b or the high-side input signal INH is at a high level.

Next, the operation of the above configuration will be described with reference to FIG. In this embodiment, the operation from time t0 to time t7 is the same as that in the first embodiment.
That is, in the period from time t0 to time t2, when the coil current IL was flowing in the positive direction, the input signal INH changed to a high level at time t0, which was flowing through the freewheeling diode 3a. Then, at time t1, the MOSFET 2 is turned on and changes so as to flow.

Further, in the period from time t3 to time t7, when the coil current IL is flowing in the positive direction and the MOSFET 2 changes from the on state to the off state at time t4, between the drain and the source of the MOSFETs 17 and 18. The MOSFET 3 can be turned on at time t5 by the displacement current due to the discharge of the electric charge charged in the parasitic capacitance. As a result, the commutation timing to the freewheeling diode 3a can be detected, and it is possible to avoid flowing to the freewheeling diode 3a during the dead time between the time t5 and the time t7 (the shaded area in FIG. 4 (K)). The loss can be reduced by flowing the current through the MOSFET 3.

Next, unlike the period up to time t7, the operation in the state after time t8 will be described. Immediately before and after time t8, the current direction of the current IL of the coil 1 is in the opposite direction to the above case, that is, from the coil 1 side to the midpoint NP side. Here, immediately before the time t8, the MOSFET 3 is in the ON state, and the coil current IL is flowing from the coil 1 to the ground side through the MOSFET 3.

The operation when the input signal INL changes from the high level to the low level at time t8 will be described. When the input signal INL changes from high level to low level, the OR circuit 12c of the low side logic circuit 12 outputs a low level signal. As a result, as shown in FIG. 4 (K), a low-level gate signal VGL is given from the drive circuit 13 to the gate of the MOSFET 3 at time t9, and the MOSFET 3 shifts to the off state.

As a result, commutation to the freewheeling diode 2a occurs, and the coil current IL flows from the coil 1 to the high voltage DC power supply 4 side via the freewheeling diode 2a. Therefore, the potential of the midpoint NP rises from the ground level to the voltage VH of the high-voltage DC power supply 4 from time t9 to time 10.

Then, the potential of the midpoint NP rises from the time t9, so that the displacement current flows through the MOSFETs 17 and 18 via the capacitor 7, the terminal A, and the level shift output resistors 19 and 20. In the MOSFETs 17 and 18, a displacement current for charging the parasitic capacitance between the drain and the source flows, so that a voltage drop of the level shift output resistor 19 occurs at time t9, and the terminal voltage OLSP is shown in FIG. 4 (H). Changes to a low level, and the terminal voltage VSP of the current limiting resistor 21 changes to a high level as shown in FIG. 4 (F).

As a result, the terminal voltages OLSP and OLSN of the level shift output resistors 19 and 20 both become low level, so that the NAND circuit 31a outputs a high level signal. In the one-shot pulse circuit 31b, since the low-level input signal INH is input to the reset terminal Re, the high-level signal is output from the output terminal O for a certain period of time.

As a result, the high-side logic circuit 31 outputs a high-level gate signal VGH at time t10. As a result, the MOSFET 2 is operated in the ON state, and the coil current IL flowing through the freewheeling diode 2a flows through the MOSFET 2.

At time t10, the terminal voltages VSP and VSN of the current limiting resistors 21 and 22 both become high level, so that the NAND circuit 12a outputs a low level signal in the low side logic circuit 12. In the one-shot pulse circuit 12b, since the low-level input signal INL is input to the reset terminal Re, the output signal of the output terminal O becomes low-level. However, at time t10, the MOSFET3 has already been given a low-level gate signal VGL to the gate by the input signal INL and has shifted to the off state, so that the operation does not change.

Further, when the displacement currents of the MOSFETs 17 and 18 disappear at time t10 and the potential of the midpoint NP reaches the voltage VH, the MOSFET 18 is in the off state. Therefore, at time t10, the current is as shown in FIG. 4 (F). The terminal voltage VSN of the limiting resistor 22 changes to a low level, and the terminal voltage OLSN of the level shift output resistor 20 changes to a high level as shown in FIG. 4 (H).

After that, as shown in FIG. 4B, the dead time ends at time t11, the input signal INH changes to a high level, and at time t12, a high level signal is sent to the OR circuit 31c in the high side logic circuit 31. Entered. However, until this point is reached, the one-shot pulse circuit 31b outputs a high-level signal for a certain period of time even if the input signal from the input terminal Tr changes to a low level. As a result, as shown in FIG. 4 (L), since the high-level gate signal VGH is continuously applied to the gate of the MOSFET 2, the MOSFET 2 is kept in the ON state.

Therefore, when the MOSFET 3 changes from the on state to the off state at time t8 while the coil current IL is flowing in the opposite direction from the coil 1, the parasitic capacitance between the drain and the source of the MOSFETs 17 and 18 is charged. The displacement current allows the MOSFET 2 to be turned on at time t10. As a result, the loss can be reduced by avoiding the flow to the freewheeling diode 2a during the dead time between the time t10 and the time t12 and allowing the flow through the MOSFET 2.

After that, when the input signal INH changes from high level to low level at time t13, as shown in FIG. 4D, the signal ILSP output via the inverter circuits 24 and 25 becomes low level, and the MOSFET 17 is turned off. Move to the state. Further, as shown in FIG. 4 (E), the signal ILSN output via the inverter circuit 24 becomes high level, and the MOSFET 18 shifts to the on state.

When the MOSFET 17 is turned off at time t13, the terminal voltage VSS of the current limiting resistor 21 changes to a low level as shown in FIG. 4 (F), and the level shift output is shown as shown in FIG. 4 (H). The terminal voltage OLSP of resistor 19 changes to a high level. Further, when the MOSFET 18 is turned on at time t13, the terminal voltage VSN of the current limiting resistor 22 changes to a high level as shown in FIG. 4 (G), and the level changes as shown in FIG. 4 (I). The terminal voltage OLSN of the shift output resistor 20 changes to a low level.

As a result, at time t14, as shown in FIG. 4 (L), in the high-side logic circuit 31, a low-level gate signal VGH is output to the gate of the MOSFET 2 to turn it off. When the MOSFET 2 is turned off, the dead time period is reached, and the coil current IL flowing in the opposite direction through the MOSFET 2 flows through the freewheeling diode 2a. Here, the potential of the midpoint NP is slightly lowered by the coil current IL flowing through the freewheeling diode 2a, but holds a potential close to the voltage VH with almost no change.

After that, when the dead time ends and the input signal INL changes to a high level at time t15, the coil current IL flows in the opposite direction by performing the same operation as in the first embodiment. The current flowing through the freewheeling diode 2a changes so that the MOSFET 3 turns on and flows at time t16 because the input signal INL changes to a high level at time t15.

Therefore, the same effect as that of the first embodiment can be obtained by such a second embodiment.
Further, according to the second embodiment, the high-side logic circuit 31 detects the state in which the displacement current flows through the high-voltage MOSFETs 17 and 18 of the level shift circuit 16 and turns on the high-side MOSFET 2. As a result, the conduction time of the freewheeling diode 2a can be further reduced as compared with the case where the operation of the level shift circuit 16 is waited for and detected as in the first embodiment.

(Third Embodiment)
FIG. 5 shows a third embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the high-voltage IC 40 is configured by incorporating the high-side element MOSFET 2 and the low-side element MOSFET 3 into the configuration of the high-voltage IC 5.

That is, in FIG. 5, the high withstand voltage IC 40 as an integrated circuit device includes eight terminals A to D and P to S. Here, the terminal D is connected to the ground together with the negative electrode terminal of the high-voltage DC power supply 4. One terminal of the coil 1, which is an inductive load, is connected to the terminal C of the high withstand voltage IC 40. The boosting capacitor 7 is connected between terminals AC of the high withstand voltage IC 40, and the positive electrode terminal of the DC power supply 6 is connected to terminal A via a diode 8 and a resistor 9 in series.

The high withstand voltage IC 40 has a configuration in which N-channel type MOSFETs 2 and 3 for supplying power to the coil 1 are built in. The common connection point of the MOSFETs 2 and 3 is connected to the terminal C as a midpoint NP. Other internal configurations of the high withstand voltage IC 40 are the same as those in the first embodiment.

Therefore, the same effect as that of the first embodiment can be obtained by such a third embodiment.
In this embodiment, the case where the configuration of the first embodiment is applied has been described, but the present invention is not limited to this, and the configuration of the second embodiment can also be applied.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof. For example, the present invention can be modified or extended as follows.

The high-side element and the low-side element have shown the cases of MOSFETs 2 and 3, but can also be applied to the case of an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or the like.

Although the present disclosure has been described in accordance with the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and modifications within a uniform range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.

In the drawing, 1 is a coil (inductive load), 2 is an N-channel MOSFET (high-side element), 3 is an N-channel MOSFET (low-side element), 2a and 3a are freewheeling diodes, and 4 is a high-voltage DC power supply. 5, 30 and 40 are high withstand voltage ICs (integrated circuit devices), 7 are boost capacitors, 10 high-side logic circuits, 12 are low-side logic circuits (control circuits), 12b, 23b and 31b are one-shot timer circuits, 16 Is a level shift circuit, 17 and 18 are N-channel type high withstand voltage MOSFETs (switching elements), 19 and 20 are level shift output resistors, 21 and 22 are current limiting resistors, 23 are level shift control circuits (control circuits), 31. Is a high-side logic circuit (control circuit).

Claims (7)

A high-side element (2) to which the free-flow diode (2a) is connected and a low-side element (3) to which the free-flow diode (3a) is connected provide a power supply circuit that feeds and discharges the inductive load (1) from the midpoint. An integrated circuit device that drives and controls
A high-side drive circuit (11) that gives a drive signal to the high-side element,
A low-side drive circuit (13) that gives a drive signal to the low-side element,
A level shift circuit (16) having a pair of level shift portions in which a level shift output resistor (19, 20), a switching element (17, 18) and a current limiting resistor (21, 22) are connected in series, and a level shift circuit (16).
A displacement current that flows through a pair of switching elements of the level shift circuit during a period in which both the high-side element and the low-side element are turned off, which is caused by a change in the potential at the midpoint between the high-side element and the low-side element. A control circuit (12, 23, 31) that detects a current that charges and discharges the parasitic capacitance of the switching element and reverse-conducts the low-side element or the high-side element in which a current is flowing through the freewheeling diode. With and
In the level shift circuit, a control signal for controlling the high-side element is input to one of the switching elements of the pair of level shift units, and an inverted signal of the control signal is input to the other switching element, so that the pair of levels An integrated circuit device configured to output a signal for generating a drive signal of the high-side element from a common connection point between each of the level-shift output resistors of the shift unit and the switching element. A high-side element (2) to which a free-wheeling diode (2a) is connected and a low-side element (3) to which a free-flowing diode (3a) is connected, which are provided so as to supply power to the inductive load (1) from the midpoint.
A high-side drive circuit (11) that gives a drive signal to the high-side element,
A low-side drive circuit (13) that gives a drive signal to the low-side element,
A level shift circuit (16) having a pair of level shift portions in which a level shift output resistor (19, 20), a switching element (17, 18) and a current limiting resistor (21, 22) are connected in series, and a level shift circuit (16).
A displacement current that flows through a pair of switching elements of the level shift circuit during a period in which both the high-side element and the low-side element are turned off, which is caused by a change in the potential at the midpoint between the high-side element and the low-side element. A control circuit (12, 23, 31) that detects a current that charges and discharges the parasitic capacitance of the switching element and reverse-conducts the low-side element or the high-side element in which a current is flowing through the freewheeling diode. With and
In the level shift circuit, a control signal for controlling the high-side element is input to one of the switching elements of the pair of level shift units, and an inverted signal of the control signal is input to the other switching element, so that the pair of levels An integrated circuit device configured to output a signal for generating a drive signal of the high-side element from a common connection point between each of the level-shift output resistors of the shift unit and the switching element. The control circuit (12, 23) detects the displacement current flowing through the pair of switching elements (17, 18) by detecting the potential of the current limiting resistor (21, 22) of the level shift circuit (16). The integrated circuit device according to claim 1 or 2. When the control circuit (12) detects the displacement current flowing through the pair of switching elements (17, 18) by detecting the potential of the current limiting resistors (21, 22), the low-side drive circuit (13) The integrated circuit device according to claim 3, wherein the drive signal of) is switched from off to on, and the low-side element (3) is controlled to be reverse-conducted. When the control circuit (23) detects the displacement current flowing through the pair of switching elements (17, 18) by detecting the potential of the current limiting resistors (21, 22), the level shift circuit (16) ) Is switched so as to invert the control signal input to the control terminal of the switching element, whereby the drive signal of the high-side drive circuit (11) is switched from off to on, and the high-side element (). The integrated circuit device according to claim 3, wherein 2) is controlled to be reverse-conducted. The control circuit (31) detects the displacement current flowing through the pair of switching elements (17, 18) by detecting the potential of the level shift output resistor (19, 20) of the level shift circuit (16). Item 2. The integrated circuit device according to Item 1 or 2. When the control circuit (31) detects the displacement current flowing through the pair of switching elements (17, 18) by detecting the potential of the level shift output resistor (19, 20), the high side element (31) The integrated circuit device according to claim 6, wherein the drive signal to 2) is switched from off to on, and the high-side element (2) is controlled to be reverse-conducted.

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