JP2014027345A - Semiconductor element drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit that implements high speed drive in a turn-on phase and reliable turning-off in a turn-off phase even if comprising a small capacity capacitor, and generates from only a unidirectional power supply (for example, positive power supply) both positive and negative voltages to be used for driving a control terminal of a switching element to be driven.SOLUTION: The capacitor is charged with a supply voltage Vcc in one direction, and the charge voltage is level-shifted up in the one direction and transiently applied as an on-driving voltage to a gate of a main transistor (Interval (4)). After that, the supply voltage Vcc is applied as an on-driving standard voltage (Intervals (5)-(7)). The capacitor is then charged with the supply voltage Vcc in the opposite direction, and the charge voltage is transiently applied as an off-driving voltage to the gate of the main transistor (Interval (11)). A ground potential is subsequently applied as an off-driving standard voltage (Intervals (12)-(14)). These operations are repeated.

Description

  The present invention relates to a semiconductor element drive circuit for driving a drive target switching element.

  Although electronic devices are required to be downsized year by year, for example, downsizing of a built-in power source of electronic devices is also required. A switching power supply circuit with high power conversion efficiency is widely used as a built-in power supply for electronic equipment. This power source converts energy by charging and discharging energy stored in passive components such as a reactor and a capacitor by switching. In general, passive components for storing energy generally occupy most of such a switching power supply circuit.

  Therefore, it is preferable to reduce the size of the passive component in order to reduce the size of the switching power supply circuit. The most effective method for downsizing passive components is to increase the switching frequency. However, when the switching frequency is increased, the switching loss increases. When the switching loss increases, the amount of heat generated by the switching element increases. For example, the size of the radiating fins must be increased. In order not to increase the switching loss, in order to increase the switching frequency, it is desirable to apply a drive signal to the control terminal of the drive target switching element at a high speed.

  However, in order to realize such high-speed switching with high reliability, it is necessary to drive while eliminating the possibility of false spots due to electromagnetic noise that increases during switching. Therefore, it is desirable to ignite at a voltage sufficiently higher than the threshold voltage at the time of turn-on, and it is desirable to ignite at a voltage sufficiently lower at the time of turn-off. When a highly complicated driving method is used, it leads to an increase in the physique of the driving circuit itself, so that it is also an important requirement for practical use to realize it using a simple circuit.

  For example, Patent Document 1 proposes a gate drive circuit. The gate drive circuit disclosed in Patent Document 1 creates a drive power source for a negative power source from a power source. In this system, positive and negative drive signals can be created using a plurality of transistors and one capacitor. Patent Document 2 also proposes a gate drive circuit. The gate drive circuit of Patent Document 2 is created by boosting a high voltage power supply for driving from a power supply by a charge pump, and a drive power supply for a negative power supply is created by another charge pump. In this system, a positive and negative drive power supply can be created using a transistor and two capacitors.

Japanese Patent No. 4682173 Japanese Patent No. 2888513

  However, although the technology described in Patent Document 1 can increase the driving speed at the time of turn-off, it is difficult to increase the driving speed of the switching element to be driven when turning on using a capacitor. Moreover, since the technique of patent document 2 requires a plurality of capacitors, it is not suitable for reducing the size of the capacitor.

  The amount of charge injected to the control terminal of the switching element to be driven is d (Vcc / (gate resistance Rge + gate oxide resistance Rgif) // where Vcc is the power supply voltage, Rge is the gate resistance, and Rgif is the resistance of the gate oxide film. dt × (charge accumulation time tg of gate electrode) If the technique of the above-mentioned patent document is adopted, a high voltage cannot be applied to the control terminal when the drive circuit is turned on, so that a large amount of charge cannot be injected into the control terminal. It should be noted that these problems are not limited to the switching power supply circuit, and exist as long as the circuit drives the switching element to be driven.

  The object of the present invention is to increase the drive speed at turn-on even when configured with a small-capacitance capacitor, to reliably turn off at turn-off, and to generate both positive and negative voltages with only a unidirectional power supply (for example, a positive power supply). Another object of the present invention is to provide a semiconductor element driving circuit which can be used for driving a control terminal of a driving target switching element.

  According to the first aspect of the present invention, since the capacitor can be driven by using a capacitor having a capacitance value comparable to that of the capacitor parasitic to the control terminal of the drive target switching element, even if the capacitor has a small capacitance value, the capacitance is not reduced. The drive target switching element can be sufficiently driven by charging and discharging. In addition, since the control circuit charges the drive voltage in one direction, shifts the charge voltage to the boost level in the one direction, and transiently applies it as an on drive voltage to the control terminal of the drive switching element. Even if a capacitor with a capacitance is used, a high voltage can be applied instantaneously, and the drive speed at turn-on can be increased. Further, since the driving voltage is applied as the on-drive standard voltage after the transient on-drive voltage is applied at the turn-on time, the drive target switching element can be held in the on state.

  In addition, after charging the driving voltage to the capacitor in the reverse direction, the charging voltage is transiently applied to the control terminal of the switching element to be driven as an off-driving voltage, so that for example, electromagnetic noise is superimposed on the control terminal. In addition, the driven switching element can be reliably turned off. In addition, since the voltage of the second power supply line is applied as the off-drive standard voltage after applying the transient off-drive voltage at the turn-off time, the drive target switching element can be held in the off state. As a result, both positive and negative voltages can be used for driving control of the drive target switching element using only a unidirectional power supply.

1 is a schematic electrical configuration diagram of a drive circuit showing a first embodiment of the present invention. Electrical configuration diagram showing a specific example of a drive circuit Timing chart for explaining the operation FIG. 1 equivalent view showing a second embodiment of the present invention (part 1) Figure 1 equivalent (part 2) FIG. 1 equivalent view showing a third embodiment of the present invention

(First embodiment)
The first embodiment will be described below with reference to FIGS. The drive circuit 1 is configured inside the semiconductor integrated circuit device A, operates by inputting the external DC power supply voltage Vcc, and the control terminal of the main transistor (drive target switching element) 2 is connected to the outside through the output terminal OUT. Yes.

  The drive circuit 1 drives the main transistor 2 by applying a gate potential Vg to the gate (control terminal) of the main transistor 2. As the main transistor 2, an N channel type MOS transistor having an IGBT or a vertical DMOS structure can be applied.

  Although not shown, a motor or the like may be applied as a drive target of the main transistor 2. Further, when applied to a switching power supply circuit or the like, it may be used as a low side drive transistor of a step-down DCDC converter. In this case, an inductive load is connected to the high side. Further, a resistor may be connected to the high side. In the following, a configuration in which the main transistor 2 is configured on the low side is shown, but a circuit in which the main transistor 2 is configured on the high side may be applied.

  The drive circuit 1 includes an H bridge circuit 3, a capacitor 4, and a bidirectional switch 5. A power supply voltage Vcc (for example, a DC power supply voltage such as Vcc = 3.3V, 5V, or 15V) is applied between the first and second power supply lines N1 and N2. At this time, the first power supply line N1 is supplied with the power supply potential Vcc, the second power supply line N2 is supplied with the ground potential GND, and the H bridge circuit 3 is connected to the first power supply line N1 and the second power supply line N2. Connected. As a result, the DC power supply voltage Vcc is applied to the H bridge circuit 3. This DC power supply voltage Vcc is set to the gate rated voltage of the main transistor 2. The H bridge circuit 3 is configured by connecting, for example, four voltage-driven semiconductor switching elements (for example, P or N channel type MOS transistors: transistors hereinafter) S1 to S4 in an H bridge form.

  A series circuit of transistors S1 and S2 is connected between the first power supply line N1 and the second power supply line N2, and further, a series of transistors S3 and S4 is connected between the first power supply line N1 and the second power supply line N2. The circuit is connected. Capacitor 4 is connected between common connection node N3 of transistors S1 and S2 and common connection node N4 of transistors S3 and S4.

  The bidirectional switch 5 is connected between the common connection node N4 of the transistors S3 and S4 and the output terminal OUT. The bidirectional switch 5 is configured by connecting two MOS transistors (hereinafter referred to as transistors) S5 to S6 connected in series between a node N4 and an output terminal OUT.

  Diodes are connected in reverse direction in parallel to the transistors S5 and S6 constituting the bidirectional switch 5, respectively. At this time, a diode is connected in parallel in the forward direction from the node N4 to the output terminal OUT side of the transistor S5, and is connected in parallel in the forward direction from the output terminal OUT to the transistor S5 side of the transistor S6. The control circuit 6 applies a target gate drive voltage to the main transistor 2 by applying an on / off drive control signal to each of the transistors S1 to S6.

  In the actual circuit configuration example of FIG. 2, P-channel MOS transistors are used as the transistors S1, S3, and S5, and N-channel MOS transistors are used as the transistors S2, S4, and S6. The operation will be described below. As long as the following operation can be realized, each of the transistors S1 to S6 may use a MOS transistor having a different conductivity type. The type of transistor is not limited to the above type.

  Hereinafter, the drive control operation of the main transistor 2 in the drive circuit 1 having the above-described configuration will be described. FIG. 3 is a timing chart showing the timing at which the transistors S1 to S6 are driven and controlled by the control circuit 6 and the voltage change of each part. Here, the potential V1 is the potential of the node N3, the potential V2 is the potential of the node N4, the potential V3 is the potential of the common connection node N5 of the transistors S5 and S6, and the gate potential Vg is the potential of the output terminal OUT. In the initial state, the transistors S1 to S6 are all assumed to be in the off state.

  First, the control circuit 6 turns on the transistors S2 and S3 (see (1) in FIG. 3). The turn-on order may be either first or simultaneously. Then, the capacitor 4 is charged and the potential V2 of the node N4 rises to the power supply potential Vcc. At this time, the potential V3 of the common connection node N5 of the transistors S5 and S6 also becomes substantially the same potential through the parallel connection diode of the transistor S5.

  Next, the control circuit 6 turns off the transistors S2 and S3 (see section (2) in FIG. 3). The turn-off order may be any of the transistors S2 and S3 first or simultaneously. In the section (3) of FIG. 3, the transistor S1 is controlled to be on. However, if the transistors S1 and S2 are simultaneously turned on, the power supply voltage Vcc is short-circuited, so the section (2) of FIG. Further, when the transistors S1 and S3 are simultaneously turned on, the charge of the capacitor 4 is regenerated to the power supply Vcc side, so the section (2) in FIG. 3 is also a section for preventing this operation abnormality.

  Next, the control circuit 6 turns on the transistor S1 (see (3) in FIG. 3). Then, power supply potential Vcc is energized to node N3, potential V2 of node N4 is shifted to the boosted level by approximately power supply potential Vcc, and potential V2 becomes boosted potential + 2Vcc. Along with this, the potential V3 of the node N5 also becomes substantially the potential + 2Vcc.

  Next, the control circuit 6 turns on the transistor S6 (see (4) in FIG. 3). Then, the potential V3 of the node N5 is energized to the gate of the main transistor 2, and the gate potential Vg of the main transistor 2 instantaneously rises to substantially the same potential as the potential V3 (see the gate potential Vg in the section (4) in FIG. 3). ). As a result, the main transistor 2 is turned on.

  Thereafter, the control circuit 6 turns on the transistor S3 (see (5) in FIG. 3). Then, both terminals of the capacitor 4 are forcibly set to the power supply potential Vcc. Therefore, the nodes N4 and N5 and the gate potential Vg are gradually lowered (see the section (5) in FIG. 3), and are lowered to the power supply potential Vcc. As a result, the voltage between the terminals of the capacitor 4 can be made substantially 0V, and the charge accumulation amount of the capacitor 4 can be made almost zero. Next, the control circuit 6 turns off the transistor S1 (see section (6) in FIG. 3). In these sections (5) and (6), since the power supply potential + Vcc is applied to the gate of the main transistor 2 through the transistors S3 and S6, the main transistor 2 is kept in the on state.

  Next, the transistors S3 and S6 are turned off (see section (7) in FIG. 3). Any of these transistors S3 and S6 may be turned off first or simultaneously. At this time, since no other current paths exist in the nodes N3 to N5, the potentials of the nodes N3 to N5 and the output terminal OUT remain almost the same as the power supply potential + Vcc. Therefore, the main transistor 2 is kept on.

  Next, the control circuit 6 turns on the transistors S1 and S4 (see (8) in FIG. 3). Any of these transistors S1 and S4 may be turned on first or simultaneously. Since a voltage is applied between the nodes N3 and N4, the capacitor 4 is charged. The potential V1 of the node N3 is maintained at the power supply potential + Vcc, and the potential V2 of the node N4 becomes the ground potential GND (0 V).

  Next, the control circuit 6 turns off the transistors S1 and S4 (see (9) in FIG. 3). The order in which these transistors S1 and S4 are turned off may be either first or simultaneously. Since there is no current conduction path in the section (9), the potentials V1 to V3 of the nodes N3 to N5 and the gate potential Vg at the output terminal OUT do not change from the potential in the section (8).

  Next, the control circuit 6 turns on the transistor S2 (see (10) in FIG. 3). Then, since the potential V1 of the node N3 becomes substantially the ground potential GND (0V), the potential V2 of the node N4 is stepped down to a potential −Vcc. Since both the transistors S5 and S6 are turned off, the potential V3 and the gate potential Vg of the node N5 are held at the potential + Vcc in the section (9) in FIG.

  Next, the control circuit 6 turns on the transistor S5 (see (11) in FIG. 3). Then, the potential V3 of the node N5 instantaneously becomes the same potential as the potential V2 (≈−Vcc) of the node N4, and the potential of the output terminal OUT also becomes substantially the same potential through the parallel connection diode of the transistor S6. As a result, the voltage of the gate capacitance of the main transistor 2 is discharged, and the main transistor 2 transitions to the off state.

  Next, the control circuit 6 turns on the transistor S4 (see (12) in FIG. 3). Then, the potential V2 of the node N4 and the potential V3 of the node N5 can be set to approximately 0 V, respectively, whereby the potential of the output terminal OUT can be set to the ground potential GND (see the section (12) in FIG. 3). Next, the control circuit 6 turns off the transistor S2 (see (13) in FIG. 3). During these (12) and (13) sections, the main transistor 2 is kept off.

  Next, the control circuit 6 turns off the transistors S4 and S5 (see (14) in FIG. 3). These transistors S4 and S5 may be turned off first or simultaneously. Even if both the transistors S4 and S5 are turned off, the main transistor 2 can maintain the off state. And it returns to the operation | movement of (1) area and repeats these operation states of (1)-(14). Among these, the control used to turn on the main transistor 2 from the off state and maintain the on state is the section (1) to (7), and the main transistor 2 is turned off from the on state to turn off. The control used to maintain is the section (8) to (14).

  According to the present embodiment, the capacitor 4 is charged with the power supply voltage Vcc in one direction, the boosted voltage is shifted in one direction, and is transiently applied to the gate of the main transistor 2 as the ON drive voltage (+2 Vcc). The power supply voltage Vcc is applied as the on-drive standard voltage (Vcc). Therefore, even if a small-capacitance capacitor 4 is used, a high voltage can be applied instantaneously and driving at turn-on can be speeded up. Further, since the power supply voltage + Vcc is applied as the on-drive standard voltage after the transient on-drive voltage (+2 Vcc) at the turn-on is applied, the main transistor 2 can be held in the on state.

  Thereafter, the capacitor 4 is charged with the power supply voltage Vcc in the reverse direction, and the charging voltage is applied transiently to the gate of the main transistor 2 as the off drive voltage (−Vcc), and then the ground potential GND is applied as the off drive standard voltage. doing. For example, even if electromagnetic noise or the like is superimposed on the control terminal of the main transistor 2, the main transistor 2 can be reliably turned off. In addition, since the ground potential GND is applied as the off-drive standard voltage after applying the transient off-drive voltage (−Vcc) at the turn-off time, the main transistor 2 can be held in the off state. Such control is repeated. By performing such control, both positive and negative voltages (+2 Vcc, + Vcc, −Vcc) can be generated only by the positive power supply voltage + Vcc, and both the positive and negative voltages can be used for driving control of the main transistor 2.

(Second Embodiment)
4 and 5 show a second embodiment of the present invention. The difference from the previous embodiment is that a gate resistor R1 is inserted as an energization limiting circuit 7 at the output terminal OUT in order to control the switching speed as shown in FIG. 4, and this energization limiting circuit 7 is inserted. It is desirable to do. In addition, as shown in FIG. 5, a series circuit (ON energization limiting circuit) of the gate resistor R2 and the diode D1 and a series circuit (OFF energization limiting circuit) of the gate resistor R3 and the diode D2 are bidirectional (turn-on direction, The power supply limiting circuit 7 may be configured by connecting in parallel so as to supply current in the turn-off direction). According to this embodiment, the same effect as that of the above-described embodiment can be obtained, and a surge generated at the gate of the main transistor 2 can be absorbed.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention. The difference from the previous embodiment is that a series connection 8 is further provided between the bidirectional switch 5 of the drive circuit 1 and the gate of the main transistor 2 as shown in FIG. This series connection body 8 is configured by connecting a capacitor C1 and a resistor R4 in series. One end of the series connection body 8 is connected between the bidirectional switch 5 and the gate of the main transistor 2, and the other end is connected to the main transistor. It is configured to be connected to two sources (on / off reference nodes of driving target switching elements).

  In this case, when the driving circuit 1 turns on the main transistor 2 and continues to apply a stable voltage Vg to the gate, the gate potential is held by the resistor R4 and the capacitor C1. Therefore, a stable voltage can be applied to the gate of the main transistor 2. For example, assuming that the gate driving circuit of the main transistor 2 in FIG. 6 is used on the high side and the low side, when a dead time interval in which both transistors 2 are turned off is provided, the main time is within the dead time interval. The gate potential of the transistor 2 can be stabilized.

  Further, for example, when the gate potential Vg of the main transistor 2 is sharply increased, a current flows through the series connection body 8 with a predetermined CR time constant, and a rapid increase in the amount of charge injected into the gate capacitance can be suppressed as much as possible. Therefore, the gate protection of the main transistor 2 can be achieved. In the present embodiment, the configuration of the energization limiting circuit 7 according to the second embodiment may be combined.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and for example, the following modifications or expansions are possible.
In the section (1) of FIG. 3, the transistor S3 is preferably turned on after the transistor S2 is turned on. Then, by turning on from the side close to the ground potential GND, each terminal potential can be stably fixed, and noise resistance can be improved.
In the section (8) of FIG. 3, it is preferable to turn on the transistor S1 after turning on the transistor S4. Then, by turning on from the side close to the ground potential GND, each terminal potential can be stably fixed, and noise resistance can be improved.

  In the sections (6) and (7) in FIG. 3, the transistor S1 is turned off and the transistors S3 and S6 are turned off, but this switching order is not limited to this order. As shown in the above embodiment, the power supply potential Vcc can be stably applied to the gate of the main transistor 2 by turning off the transistor S3 in FIG. 3 at a timing after the transistor S1. The same applies to the sections (13) and (14) in FIG.

  Further, the capacitor 4 is charged in the sections (1) and (8) in FIG. 3, and the voltage of the collector-emitter voltage (voltage between output terminals) Vce of the main transistor 2 is detected for the charging time of the capacitor 4, It is desirable to set the charging time of the capacitor 4 according to the detection voltage Vce. Then, switching loss can be reduced by setting the charging time. As an example of the detection method, a method of inserting a voltage dividing resistor between the collector and emitter of the main transistor 2 and detecting a divided voltage of the resistor is given as an example.

  In this case, even if a method of detecting and feeding back the signal one by one is applied, a divided voltage corresponding to the load is detected in advance at the design stage, for example, a storage table is prepared in the control circuit 6 and the divided voltage is stored in the storage table. And the load energization state may be stored in association with each other and controlled. In the case of detection one by one, feedback control may be performed with reference to the detection voltage Vce one cycle before in consideration of the effect of signal propagation delay.

  3, the charging voltage of the capacitor 4 is controlled by controlling the charging time of the capacitor 4, and the gate potential Vg applied to the gate of the main transistor 2 is controlled. It is desirable. Then, the level of the gate potential Vg can be controlled. In this case, the length of the section (1) in FIG. 3 is a charging time depending on the turn-on operation, and the length of the section (8) in FIG. 3 is a charging time depending on the turn-off operation. May be individually controlled. That is, the lengths (1) and (8) in FIG. 3 may be different from each other. Then, on / off control of the main transistor 2 can be easily performed.

  For example, by controlling the charging voltage so as not to apply a predetermined voltage (for example, twice) of a rated voltage (for example, + Vcc) that is a gate breakdown voltage as the gate voltage Vg, it is possible to prevent energization breakdown of the gate and suppress deterioration. In the initial stage of energization of the gate to the main transistor 2, since the gate resistance is large, even when a voltage about twice the rated voltage is applied, breakdown of energization of the gate can be prevented and deterioration can be suppressed.

  It is desirable that the capacitance value of the capacitor 4 is set to be approximately equal to the gate capacitance value of the main transistor 2 or smaller than the gate capacitance value of the main transistor 2. An example will be described. Consider a case where, for example, an IGBT having a withstand voltage of 600 V is applied to the main transistor 2. At this time, the gate-collector parasitic capacitance Ccg, the gate-emitter parasitic capacitance Cge, and the collector-emitter parasitic capacitance Cce are respectively defined, and gate capacitance Cies = Cgc + Cge, collector capacitance Coes = Cce + Ccg, Cres = Ccg. , For example, values such as Cies = 4000 pF, Coes = 400 pF, Cres = 200 pF are assumed.

  In this case, the capacitance value of the capacitor 4 may be equal to or less than the parasitic capacitance value of the capacitance Cies. When the capacitor 4 having such a capacitance value is used, the capacitance value of the capacitor 4 can be reduced, so that heat generation can be suppressed. For example, even if a radiator is provided, the physique can be reduced.

  In the drawings, 1 is a drive circuit, 2 is a main transistor (drive target switching element), 3a is a first series circuit, 3b is a second series circuit, 4 is a capacitor, 5 is a bidirectional switch, 6 is a control circuit, and 7 is N1 is a first power supply line, N2 is a second power supply line, N3 to N5 are nodes, and OUT is an output terminal.

Claims (12)

A semiconductor element driving circuit for energizing and driving a control terminal of a driving target switching element,
A first series circuit (3a) configured by connecting first and second switches (S1 and S2) in series between a first power supply line (N1) and a second power supply line (N2) to which a driving voltage is applied; ,
A second series circuit (3b) configured by connecting third and fourth switches (S3 and S4) in series between the first and second power supply lines (N1 and N2);
A first node (N3) commonly connecting the first and second switches (S1 and S2) of the first series circuit and a third node and a fourth switch (S3 and S4) of the second series circuit are commonly connected. A capacitor (4) connected between the second node (N4) and set to a capacitance value comparable to a capacitance parasitic to the control terminal of the drive target switching element;
A bidirectional switch (5) connected between a control terminal of the drive target switching element and a second node (N4) between the third and fourth switches (S3 and S4);
An on / off control of the first to fourth switches (S1 to S4), and a control circuit (6) for switching and controlling energization on / off and energization direction of the bidirectional switch (5),
The control circuit (6) performs on / off control of the first to fourth switches (S1 to S4) and energizes the bidirectional switch (5) during one cycle in which the driving target switching element is driven on and off. By switching on / off and energizing direction,
The capacitor (4) is charged with the driving voltage in one direction, the charging voltage is boosted in the one direction, and the voltage is boosted and applied transiently to the control terminal of the driving target switching element as the second driving voltage. The drive voltage (Vcc) of the first power supply line (N1) with respect to the power supply line (N2) is applied as an on-drive standard voltage, and then the drive voltage is applied to the capacitor (4) in a direction opposite to the one direction. And the charging voltage is transiently applied to the control terminal of the driving target switching element as an off driving voltage, and then the voltage (GND) applied to the second power supply line (N2) is applied as an off driving standard voltage. A semiconductor element driving circuit characterized by repeating the above. The semiconductor element driving circuit according to claim 1,
A semiconductor element drive circuit, wherein the on / off control of the drive target switching element is performed by repeating the following controls (A) to (H).
(A) The voltage at which the second node (N4) becomes a high voltage with respect to the first node (N3) under the condition that the potential of the first node (N3) matches the potential of the second power supply line (N2). Charging the capacitor (4),
(B) The potential of the second node (N4) is shifted by a boost level by controlling the potential of the first node (N3) to the positive side.
(C) Transiently applying the boosted potential of the second node (N4) to the control terminal of the drive target switching element by switching the bidirectional switches (S5 to S6);
(D) holding the drive target switching element in an on state by applying an on drive standard voltage lower than the boosted potential to the control terminal of the drive target switching element;
(E) A voltage at which the second node (N4) becomes a low voltage with respect to the first node (N3) under the condition that the potential of the second node (N4) is matched with the potential of the second power supply line (N2). Charging the capacitor (4);
(F) By controlling the potential of the first node (N3) to the negative side, the potential of the second node (N4) is stepped down to a low potential,
(G) Transiently applying the low potential of the second node (N4) to the control terminal of the drive target switching element by switching the bidirectional switches (S5 to S6);
(H) Applying an off drive potential higher than the low potential to the control terminal of the drive target switching element to turn the drive target switching element off. The control circuit (6)
After transiently applying a voltage twice as high as the power supply voltage between the first and second power supply lines as the on drive voltage shifted in the boosting level in one direction, applying the power supply voltage as the on drive standard voltage,
A voltage that is -1 times the power supply voltage between the first and second power supply lines is applied as the off drive voltage, and a voltage applied to the second power supply line as the off drive standard voltage is applied as the off drive standard voltage. 3. The semiconductor element driving circuit according to claim 1, wherein   4. The semiconductor element driving circuit according to claim 2, wherein the control circuit (6) turns on the third switch (S3) after turning on the second switch (S2) in (A). .   The control circuit (6) according to any one of claims 2 to 4, wherein the control circuit (6) turns on the first switch (S1) after turning on the fourth switch (S4) in the step (E). Semiconductor element drive circuit.   The said control circuit (6) sets the applied voltage of the control terminal of the said drive object switching element according to the charge time which charges the said capacitor | condenser (4). The semiconductor element driving circuit described. The drive target switching element is one in which an energization state between a plurality of output terminals is set according to an applied voltage applied to a control terminal,
The said control circuit (6) sets the charging time of the said capacitor | condenser (4) according to the voltage (Vce) between the several output terminals of the said drive object switching element, The any one of Claims 1-6 characterized by the above-mentioned. A semiconductor element driving circuit according to claim 1. The drive target switching element is one in which an energization state between a plurality of output terminals is set according to an applied voltage applied to a control terminal,
The control circuit individually sets the charging time of the capacitor (4) at the time of turn-on and the charging time of the capacitor (4) at the time of turn-off according to the voltage (Vce) between the plurality of output terminals of the driving target switching element. The semiconductor element driving circuit according to claim 1, wherein   The said capacitor | condenser (4) uses the thing of the electrostatic capacitance value equivalent to or less than the parasitic capacitance parasitic to the control terminal of the said drive object switching element, The one in any one of Claims 1-8 characterized by the above-mentioned. Semiconductor device driving circuit.   The semiconductor element drive according to claim 1, further comprising an energization limiting circuit (7) that limits energization between the bidirectional switch (5) and a control terminal of the drive target switching element. circuit. The energization limiting circuit (7)
ON that is configured by combining a resistor (R2) and a diode (D1), and restricts energization in the direction from the bidirectional switch (5) to the control terminal side of the drive target switching element when the drive target switching element is turned on. A current limiting circuit (R2 and D1);
OFF that is configured by combining a resistor (R3) and a diode (D2), and restricts energization in the direction from the control terminal of the driving target switching element to the bidirectional switch (5) when the driving target switching element is turned off. 11. The semiconductor element driving circuit according to claim 10, further comprising an energization limiting circuit (R3 and D2).   A series connection circuit of a capacitor (C1) and a resistor (R4) is included, and one end is connected between the bidirectional switch (5) and the control terminal of the drive target switching element and the other. 12. The semiconductor element driving circuit according to claim 1, further comprising a series connection body (8) having an end connected to an on / off reference node of the driving target switching element.

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