JP5469228B1 - Switch element driving device - Google Patents

Abstract

In order to perform synchronous rectification control of first and second switch elements connected in series, even if the temperature environment rises, the ON section of the second switch element is compared to the ON section of the first switch element. A switch element driving device that prevents an arm short circuit by preventing the two elements from overlapping each other is obtained.
A control signal for controlling a first switch element 2 and a second switch element 4 so as not to be simultaneously turned on is received, and a first and a second drive signal is output to the first switch element 2. Switch element drive means 3a, and second switch element drive means 5a for receiving the control signal and outputting ON and OFF drive signals to the second switch element 4, and the first switch element drive means 3a outputs a drive signal for increasing the ON delay of the first switch element 2 as the environmental temperature rises with respect to the OFF of the second switch element 4.
[Selection] Figure 1

Description

  The present invention relates to a switch element driving device that receives a control signal to drive a switch element, and in particular, the first and second switch elements of a switching device including first and second switch elements connected in series. The present invention relates to a switch element driving device that performs synchronous rectification control on the switch.

  The inverter that controls the motor controls the switching device, thereby switching the current supply path that flows to each coil of the motor and performing drive control of the motor. Moreover, a transformer etc. controls the switching apparatus, adjusts the electric current supply amount from a power supply to a reactor (coil), transforms the voltage which generate | occur | produces with a power supply into arbitrary voltages, and outputs it.

  In the switching device, a first switch element and a second switch element are connected in series, and a connection point between the first switch element and the second switch element is connected to a reactor as an output unit to supply current. In order to drive the first and second switch elements of the switching device, a switch element driving device is required.

  As this type of switch element driving apparatus, there is a switch element driving apparatus that performs synchronous rectification control of a first switch element and a second switch element. The synchronous rectification control is a control method in which the second switch element is turned OFF when the first switch element is ON, and the second switch element is turned ON when the first switch element is OFF. At this time, the ON section of the first switch element is not overlapped with the ON section of the second switch element with respect to the energization section of the first switch element (hereinafter referred to as the ON section). On the other hand, an invention has been proposed in which a delay (dead time) is provided so that the ON sections of the second switch elements do not overlap.

For example, Japanese Patent Laid-Open No. 2002-335679 (Patent Document 1) includes a circuit that distributes a common control signal to two , inverts one of them, and a delay circuit that delays the rising or falling of the control signal. In addition, a switch element driving device that performs synchronous rectification control of the first switch element and the second switch element is shown. In this switch element driving device, the dead time is given by delaying the rise or fall of the control signal, and the arm short circuit is prevented.

  Japanese Patent Application Laid-Open No. 2009-290812 (Patent Document 2) includes a circuit that detects edges of output signals of the first switch element and the second switch element, a circuit that adjusts the voltage of the detected edge, A switching element that compares the adjusted edges and determines a delay amount, and a circuit that adds a delay to the control signal in accordance with the delay amount, and that controls synchronous rectification of the first switch element and the second switch element The drive is shown. In this switching element driving device, a delay amount is given according to the detected edge to prevent an arm short circuit.

JP 2002-335679 A JP 2009-290812 A

  In the switch element driving device shown in Patent Document 1, when a delay is given by a capacitor, the capacitor capacity changes due to a temperature change, the dead time cannot be secured, and an arm short circuit may occur.

  Further, in the switching element driving device shown in Patent Document 2, since the dead time is set until the edge detection, depending on the environmental temperature, a state where the dead time cannot be ensured at the start occurs, and the arm is short-circuited. Sometimes.

Further, with respect to the rise of the signal input to the switching element driving device for controlling the switching element, even when the slow rising timing or rising speed of a signal output from the switching element driving device, and variation of the element, The delay (output transmission delay) between the signal that controls the switch element and the signal that drives the switch element may increase when the environmental temperature is high, and therefore, the dead time cannot be ensured, leading to an arm short circuit. There is.

  The smaller the dead time is, the more efficient the switching device is. However, when the dead time cannot be ensured and the arm is short-circuited, the switch element burns out, and in the worst case, a fire occurs. In addition, synchronous rectification is often used for DC-DC converters that transform the voltage generated by the generator to a voltage suitable for the connected equipment, inverters that control motors, etc. There is a problem that the power supply or the motor stops.

  The present invention has been made to solve the above-described problems. Even if the temperature environment rises, the ON section of the second switch element does not overlap the ON section of the first switch element. Thus, an object of the present invention is to obtain a switch element driving device that prevents an arm short circuit.

The switch element drive device according to the present invention is a switch element drive device that performs synchronous rectification control of the first and second switch elements of a switching device including first and second switch elements connected in series.
A first control signal input terminal to which a control signal of the first switch element is input; a second control signal input terminal to which a control signal of the second switch element is input; and the first control signal. First switch element driving means for receiving the control signal from an input terminal and outputting ON and OFF drive signals to the first switch element; and receiving the control signal from the second control signal input terminal. A second switch element driving means for outputting ON and OFF drive signals to the second switch element,
The control signal input to the first and second control signal input terminals is a control signal for controlling the first switch element and the second switch element so as not to be simultaneously turned on, and the first switch The element driving means outputs a drive signal that delays the ON speed of the first switch element with an increase in environmental temperature with respect to the OFF speed of the second switch element.

  According to the switch element driving device of the present invention, it is possible to obtain a switch element driving device that prevents an arm short circuit even when the environmental temperature rises.

In addition, according to the switch element driving device according to the present invention, since the dead time of the switch element control signal set on the control side can be fixed, a control device with low calculation capability can be used, and switching can be performed at low cost. It is possible to control the device. Furthermore, since the dead time can be eliminated when the environmental temperature is low, an efficient switch element driving device can be obtained.

It is a circuit diagram explaining an example of the switch element drive device concerning Embodiment 1 of this invention. It is a timing chart which shows the operation | movement of the 2nd switch element drive means of the switch element drive device concerning Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the switch element drive device concerning Embodiment 1 of this invention, and the switching device driven by it. It is a figure which shows the accumulation | storage delay time of the transistor with respect to environmental temperature. It is a circuit diagram explaining the other example of the switch element drive device which concerns on Embodiment 1 of this invention. It is a circuit diagram explaining an example of the switch element drive device concerning Embodiment 2 of this invention. It is a circuit diagram explaining an example of the switch element drive device concerning Embodiment 3 of this invention. It is a timing chart which shows operation | movement of the switch element drive device which concerns on Embodiment 3 of this invention, and the switching device driven by it. It is a circuit diagram explaining the other example of the switch element drive device which concerns on Embodiment 3 of this invention.

  Preferred embodiments of a switch element driving apparatus according to the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Embodiment 1 FIG.
1 is a circuit diagram illustrating an example of a switch element driving apparatus according to Embodiment 1 of the present invention.
In Figure 1, the switching element driving device 1a drives the first switch element drive means 3a for driving the first switching element 2 consisting of N-channel MOSFET, a second switching element 4 also consists of N-channel MOSFET A second switch element driving means 5a; a first control signal input terminal (hereinafter referred to as a first signal input terminal) 6 which is an input terminal for the ON / OFF control signal of the first switch element 2; A second control signal input terminal (hereinafter referred to as a second signal input terminal) 7 is provided as an input terminal for ON / OFF control signals of the second switch element 4. The first switch element 2 and the second switch element 4 constitute a switching device 8 and are connected to a reactor 9 that stores energy of a signal output from the switching device 8.

  The first switch element driving means 3 a receives a control signal from the first signal input terminal 6 and outputs ON and OFF drive signals to the first switch element 2. Further, when the environmental temperature is higher than a preset temperature, the second switch element driving means 5a receives a control signal from the second signal input terminal 7, and turns on the output signal from the ON timing of this control signal. An ON / OFF drive signal is output to the second switch element 4 so that the delay increases with an increase in temperature.

  The switching device 8 has a configuration in which the first switch element 2 and the second switch element 4 are connected in series, and is connected to a power supply 10. The switching device 8 turns on and off the first switch element 2 and the second switch element 4 by applying a voltage from the power source 10 and a drive signal output from the switch element drive device 1a, and thereby the first switch element 2 A signal is output from the connection portion 11 of the second switch element 4. Then, the energy of this output signal is stored in the reactor 9.

Next, details of the first switch element driving means 3a and the second switch element driving means 5a will be described.
First, the first switch element driving means 3a includes a resistor 13 connected between the first signal input terminal 6 and the gate of the third switch element 12, and a gate and a source of the third switch element 12. A resistor 14 connected between the first power source 15a and a first power source 15 of the first switch element driving means 3a and a drain 16 of the third switch element 12 for limiting the drain-source current; A resistor 18 connected between the drain of the third switch element 12 and the gate of the fourth switch element 17a, a resistor 19 connected between the gate and source of the fourth switch element 17a, and driving A resistor 20 is connected between the power supply 15 and the drain of the fourth switch element 17a and limits the drain-source current of the fourth switch element 17a.

The third switch element 12 and the fourth switch element 17a are composed of N- channel MOSFETs. The third switch element 12 is driven by a resistor 13 and a resistor 14 and inverts ON and OFF of a control signal input from the first signal input terminal 6 to convert it into a drive voltage for the first switch element 2. . The fourth switching element 17a is driven by the resistor 18 resistor 19, is converted to ON and OFF is inverted signal from the third switching element 12, the first driving voltage of the switch element 2 Rubeki Invert to become a signal .

  Further, the first switch element driving means 3a is connected between the drain of the fourth switch element 17a and the bases of the first and second transistors 21 and 22, and the first and second brother transistors 21 and 22 are connected. Is connected between the resistor 23 for limiting the base current of the first switch element 2 and the emitters of the first and second transistors 21 and 22 and the gate of the first switch element 2 to limit the amount of current of the first switch element 2. A resistor 24 for adjusting the switch speed is provided.

The first transistor 21 is composed of an N- channel bipolar transistor, and the second transistor 22 is composed of a P- channel bipolar transistor. The first transistor 21 has a collector connected to the drive power supply 15 and an emitter connected to the emitter of the second transistor 22. The first transistor 21 is driven so as to be charged when the drive signal of the first switch element 2 input by the fourth switch element 17a is ON. The collector of the second transistor 22 is connected to the source of the fourth switch element 17a and the ground G1 of the power supply 10, and the drive signal of the first switch element 2 input by the fourth switch element 17a is received. It is driven to discharge when it is OFF.

Next, the second switch element driving means 5a includes a resistor 26 connected between the second signal input terminal 7 and the gate of the fifth switch element 25, and the gate and source of the fifth switch element 25. Between the drain 27 and the source of the fifth switch element 25, the resistor 27 connected between the second switch element driver 5 a and the drain of the fifth switch element 25. a resistor 29 to limit the current, the oN and OFF is inverted signals from the fifth switching element 25, a third tons reversed so that the second Rubeki signal is converted into a driving voltage of the switch element 4 The resistor 30 is connected between the drive power supply 28 and the collector of the third transistor 30 and has a resistor 31 for limiting the collector-emitter current of the third transistor 30.

The third transistor 30 is composed of an N- channel bipolar transistor , and the fifth switch element 25 is composed of an N- channel MOSFET. The fifth switch element 25 is driven by a resistor 26 and a resistor 27, inverts the control signal input from the second signal input terminal 7 to ON and OFF, and converts it into a drive voltage for the second switch element 4. .

  Further, the second switch element driving means 5 a is connected between the collector of the third transistor 30 and the bases of the fourth and fifth transistors 32, 33, and the fourth and brother 5 transistors 32, 33. Is connected between the resistor 34 for limiting the base current of the second switch element 4 and the emitters of the fourth and fifth transistors 32 and 33 and the gate of the second switch element 4 to limit the amount of current of the second switch element 4. A resistor 35 for adjusting the switch speed is provided.

The fourth transistor 32 is composed of an N- channel bipolar transistor, and the fifth transistor 33 is composed of a P- channel bipolar transistor. The fourth transistor 32 has a collector connected to the drive power supply 28, an emitter connected to the emitter of the fifth transistor 33, and a drive signal for the second switch element 4 input by the third transistor 30. It is driven to charge when is turned on. The fifth transistor 33 has a collector connected to the emitter of the third transistor 30 and the ground G2 of the drive power supply 28, and the drive signal of the second switch element 4 input by the third transistor 30 is received. It is driven to discharge when it is OFF.

  In the above description, the first switch element 2 and the second switch element 4 are constituted by high-breakdown-voltage power MOSFETs having a large package size, and the third switch element 12, the fourth switch element 17a, and the fifth switch element. The switch element 25 is composed of a small signal MOSFET having a small package size.

The switch element driving device 1a according to the first embodiment is configured as described above, and the operation thereof will be described next.
FIG. 2 is a timing chart showing the operation of the second switch element driving means 5a. Here, before describing the operation of the second switch element driving means 5a, the characteristics of the bipolar transistor will be described first.

  In the bipolar transistor, when a voltage is applied between the base and the emitter to turn on the input signal, a current flows between the collector and the emitter, and the output voltage (collector-emitter voltage) becomes 0V. As a result, the bipolar transistor outputs an inverted OFF with respect to the ON of the input signal. On the other hand, when the voltage between the base and emitter is set to 0 V and the input signal is turned off, the current between the collector and emitter is cut off, so the output voltage (collector-emitter voltage) becomes the voltage applied to the transistor, and the input signal Inverted ON is output with respect to OFF.

  In addition, the bipolar transistor has an accumulation delay time due to the minority carrier accumulation effect, and a phenomenon occurs in which the rise of the output signal is delayed with respect to the fall of the input signal. Since this accumulation delay time does not exist in the MOSFET, the delay in the MOSFET is very small as compared with outputting inverted OFF with respect to ON of the input signal of the bipolar transistor.

Returning to FIG. 2, the signal (a) indicates the control signal from the second signal input terminal 7 and the gate-source voltage (input signal: Vgs) of the fifth switch element 25. The signal (b) indicates the drain-source voltage (output signal: Vds) of the fifth switch element 25 and the base-emitter voltage (input signal: Vbe ) of the third transistor 30. The signal (c) indicates the collector-emitter voltage (output signal: Vce) of the third transistor 30. The signal (d) indicates the gate-source voltage (input signal: Vgs ) of the second switch element 4.

  The signal input to the fifth switch element 25 is output with the ON and OFF inverted and input to the third transistor 30. In the third transistor 30, the output is delayed with respect to the input signal by the storage delay time ts due to the minority carrier storage effect. Therefore, in the second switch element driving means 5a, the input voltage of the second switch element 4 is turned on with a delay of the accumulation delay time ts with respect to the ON of the control signal input from the second signal input terminal 7.

FIG. 3 is a timing chart showing operations of the switch element driving device 1a and the switching device 8.
In FIG. 3, a signal (e) indicates a control signal from the first signal input terminal 6 and a gate-source voltage (input signal: Vgs) of the third switch element 12. The signal (f) indicates the control signal from the second signal input terminal 7 and the gate-source voltage (input signal: Vgs) of the fifth switch element 25. The signal (g) indicates the gate-source voltage (input signal: Vgs) of the first switch element 2. The signal (h) indicates the gate-source voltage (input signal: Vgs) of the second switch element 4. The signal (i) indicates the drain-source voltage (input signal: Vds) of the first switch element 2. The signal (j) indicates the drain-source voltage (input signal: Vds) of the second switch element 4.

  As described above, the control signal from the first signal input terminal 6 is a signal obtained by inverting ON and OFF with respect to the control signal from the second signal input terminal 7. Further, the control signal from the first signal input terminal 6 is turned OFF and the control signal from the second signal input terminal 7 is turned ON, and the control signal from the first signal input terminal 6 is turned ON and second. The dead time td set by the control signal for preventing the arm short circuit between the first switch element 2 and the second switch element 4 is provided between the control signal OFF from the signal input terminal 7. The dead time td is a threshold value from the beginning of the rise of the voltage between the gate and the source of the second switch element 4 with respect to the time tf when the gate and source voltage of the first switch element 2 becomes less than the threshold at the normal temperature. Using the time tr as described above, tf + tr <td is set.

Since the first switch element 2 has a larger package size than the third switch element 12, the first switch element 2 has a large input parasitic capacitance, and the switching speed (ON of the gate-source voltage is higher than that of the third switch element 12. , OFF speed) becomes slower. Similarly, the second switch element 4 has a lower switching speed (ON / OFF speed of the gate-source voltage) than the fifth switch element 25. Further, as described above, the input voltage of the second switch element 4 is turned on with a delay of the storage delay time ts with respect to the ON of the control signal input from the second signal input terminal 7 .

  In the first switch element 2, when the gate-source voltage rises and exceeds the threshold value, the drain-source voltage is energized, and the drain-source voltage becomes 0 V (section A). As a result, the gate-source voltage of the first switch element 2 decreases. When the voltage drops below the threshold, the drain-source voltage is cut off, and the drain-source voltage becomes the voltage of the power supply 10. Similarly, in the second switch element 4, when the gate-source voltage rises and exceeds the threshold value, the drain-source voltage is energized, and the drain-source voltage becomes 0 V (section C). As a result, the gate-source voltage of the second switch element 4 decreases. When the voltage falls below the threshold, the drain-source voltage is cut off, and the drain-source voltage becomes the voltage of the power supply 10.

  However, the output (drain-source voltage) of the second switch element 4 is supplied as energy from the power supply 10 to the reactor 9 when the drain-source of the first switch element 2 is energized. Accumulated. The stored energy flows via the body diode of the second switch element 4 by the back electromotive force of the reactor 9 at the moment when the drain and source of the first switch element 2 are cut off, A voltage drop corresponding to the forward voltage of the body diode occurs in the voltage between the drain and source of the switch element 4 (section B: dead time). When there is no section B in which the drain and source of the first switch element 2 are energized and the section A and the section C overlap, an arm short circuit occurs.

FIG. 4 is a diagram illustrating the accumulation delay time of the transistor with respect to the environmental temperature. Here, the accumulation delay time and the temperature characteristic will be described.
The horizontal axis in FIG. 4 indicates the environmental temperature, and the vertical axis indicates the accumulation delay time. As shown in FIG. 4, it can be seen that the storage delay time increases as the environmental temperature increases.

In addition, due to environmental temperature and element variation, the time tf when the gate-source voltage of the first switching element 2 is less than or equal to the threshold, and the time tr when the gate-source voltage of the second switching element 4 is greater than or equal to the threshold. However, the increase in the storage delay time due to the increase in the environmental temperature is larger than these time changes. Accordingly, when the environmental temperature rises, the accumulation delay time ts increases, so that the section B shown in FIG. 3 increases. Therefore, the section A and the section C do not overlap with each other, and an arm short circuit due to the environmental temperature rise can be prevented. it can.

  As described above, the switch element driving device 1a according to the first embodiment includes the first signal input terminal 6 that controls ON and OFF of the first switch element 2 and the ON and OFF of the second switch element 4. The first switch element drive which receives the control signal from the second signal input terminal 7 for controlling the control signal and the first signal input terminal 6 and outputs ON and OFF drive signals to the first switch element 2 When the environmental temperature is higher than the preset temperature with the means 3a, the control signal is received from the second signal input terminal 7, and the ON timing of the output drive signal is delayed as the temperature rises. The second switch element drive means 5a for outputting ON and OFF drive signals to the second switch element 4 is provided so as to increase.

  The switch element driving device 1a drives the switching device 8. The switching device 8 includes a first switch element 2 and a second switch element 4, and the first switch element 2 and the second switch element 4 are connected in series. The first and second switch elements 2 and 4 are turned on and off by a drive signal output from the switch element driving device 1a, and a signal is transmitted from the connection portion 11 between the first switch element 2 and the second switch element 4. Output. The energy of the signal output from the connection unit 11 is stored in the reactor 9.

  With this configuration, even when the environmental temperature rises, the ON section of the second switch element 4 is delayed with respect to the ON section of the first switch element 2, so that an arm short circuit can be prevented.

Incidentally, in the above embodiment, a case has been described using a N-channel MOSFET in the fourth switch element 17a constituting the first switch element drive means 3a, when there is voltage fluctuation of the power source 10, N-channel The MOSFET may be changed to a P- channel MOSFET. Specific examples thereof will be described below.

FIG. 5 is a circuit diagram illustrating another example of the switch element driving device according to the first embodiment. In FIG. 5, reference numeral 1b indicates another example of the switch element driving device. Reference numeral 17b denotes a fourth switch element constituting the switch element driving device 1b, which is composed of a P- channel MOSFET.

  The first switch element driving means 3b includes a resistor 50 connected between the drain of the third switch element 12 and the gate of the fourth switch element 17b, and the gate and source of the fourth switch element 17b. A resistor 51 connected in between, and a resistor 52 connected between the ground G1 of the power supply 10 and the drain of the fourth switch element 17b and limiting the drain-source current of the fourth switch element 17b. Yes. In addition, about another structure, it is the same as that of Embodiment shown in FIG. 1, The same code | symbol is attached | subjected and description is abbreviate | omitted.

The fourth switch element 17 b is connected to the drive power supply 15, and the gate is driven by the resistor 50 and the resistor 51. The fourth switch element 17b is ON and OFF is inverted signal from the third switching element 12 is converted into a first driving voltage of the switch element 2 and outputs a Rubeki signal.

According to the switch element driving device 1b configured as described above, since the fourth switch element 17b also has no delay in the accumulation delay time, the output signal is equivalent to that of the embodiment shown in FIG. 1, and the same effect is obtained. be able to. Further, the use of a P- channel MOSFET for the fourth switch element 17b has the following characteristics.

In the case of the switching power supply, there is a mode in which a counter electromotive force is generated in the reactor 9. As a result, a drop voltage corresponding to the resistance of the body diode of the second switch element 4 is generated at the ground G1 of the power supply 10. That is, when a back electromotive force is generated in the reactor 9 and the second switch element 4 is in the OFF state, the potential of the ground G1 of the power supply 10 is only a drop voltage corresponding to the resistance of the body diode of the second switch element 4. Negative potential. Therefore, as shown in FIG. 1, when an N- channel MOSFET is used for the fourth switch element 17a, the reference potential is the ground G1 when viewed from the fourth switch element 17a. The gate-source voltage Vgs is a positive potential. At this time, the voltage applied between the gate and source of the fourth switch element 17a (drop voltage corresponding to the resistance of the body diode of the second switch element 4) exceeds the threshold value of the fourth switch element 17a. In this case, the fourth switch element 17a is turned on.

  That is, since the fourth switch element 17a is turned on even though the third switch element 12 is turned on and the first switch element 2 is turned on, the first switch element 2 is turned off. . In particular, this phenomenon occurs when the power supply 10 is close to the same potential as the output voltage of the reactor 9, that is, in the case of a step-down switching power supply, when the ON time of the third switch element 12 is long, in other words, the third switch element 12 This occurs remarkably when the DUTY ratio is close to 100%. More specifically, the larger the current flowing through the body diode of the second switch element 4 and the path passing through the connecting portion 11 (the output current of the reactor 9), the greater the generation.

On the other hand, as shown in FIG. 5, when a P- channel MOSFET is used for the fourth switch element 17b, the fourth switch element 17b applies a gate-source voltage Vgs negative voltage based on the drive power supply 15. If you drive. When a counter electromotive force is generated in the reactor 9, even if the voltage of the ground G1 varies as viewed from the fourth switch element 17b, the reference potential for driving the fourth switch element 17b becomes the drive power supply 15. It can be driven stably.

Embodiment 2. FIG.
Next, a switching element driving apparatus according to Embodiment 2 of the present invention will be described. FIG. 6 is a circuit diagram illustrating an example of the switch element driving device according to the second embodiment. In FIG. 6, reference numeral 1c indicates a switch element driving apparatus according to the second embodiment, and reference numeral 3c indicates a first switch element driving means constituting the switch element driving apparatus 1c.

The first switch element driving means 3c is connected between the resistor 61 connected between the first signal input terminal 6 and the base of the sixth transistor 60, and between the base and emitter of the sixth transistor 60. A resistor 62 connected between the drive power supply 15 and the collector of the sixth transistor 60 to limit the collector-emitter current of the sixth transistor 60, and a collector of the sixth transistor 60. A resistor 65 connected between the base of the seventh transistor 64, a resistor 66 connected between the base and emitter of the seventh transistor 64, a collector of the drive power supply 15 and the seventh transistor 64 And a resistor 67 for limiting the collector-emitter current of the seventh transistor 64. Note that the younger brother 6 and the seventh transistors 60 and 64 are N- channel bipolar transistors. The other configuration of the first switch element driving unit 3c is the same as that of the first embodiment, and the same reference numerals are given and description thereof is omitted.

  The sixth transistor 60 is driven by a resistor 61 and a resistor 62, inverts ON and OFF of a control signal input from the first signal input terminal 6, and converts it into a drive voltage for the first switch element 2. The seventh transistor 64 is driven by a resistor 65 and a resistor 66, and is matched with ON and OFF of a signal converted into a drive voltage of the first switch element 2 in which ON and OFF are inverted from the sixth transistor 60. Reverse.

The second switch element driving means 5b includes a resistor 69 connected between the second signal input terminal 7 and the base of the eighth transistor 68, and a base and emitter of the eighth transistor 68. Is connected between the drive power supply 28 and the collector of the eighth transistor 68 to limit the collector-emitter current of the eighth transistor 68 and the base current of the third transistor 30. The thermistor 71 whose resistance value is lowered as the temperature rises is provided. The transistor 68 of the younger brother 8 is composed of an N- channel bipolar transistor. The other configuration of the second switch element driving unit 5b is the same as that of the first embodiment, and the same reference numerals are given and description thereof is omitted.

  The eighth transistor 68 is driven by the resistor 69 and the resistor 70, inverts ON and OFF of the control signal input from the second signal input terminal 7, and converts it into the drive voltage of the second switch element 4.

  Here, the relationship between the accumulation delay time and the base current will be described. When the charge output from the base current is small, the minority carrier accumulation effect is weakened and the number of accumulated carriers is reduced, so that the accumulation delay time is reduced. Therefore, the larger the base current, the longer the accumulation delay time.

  In the second switch element driving means 5b configured as described above, the resistance value of the resistor 63 and the resistance value of the thermistor 71 are the same at room temperature, so that the control signal from the first signal input terminal 6 can be obtained. Delay of the timing of starting and shutting off energization between the drain and source of the first switch element 2 with respect to ON and OFF, and the drain of the second switch element 4 with respect to ON and OFF of the control signal from the second signal input terminal 7 -The delay in timing of starting and shutting off the current between the sources is the same, and there is no relative delay.

Considering the case where the environmental temperature rises in this state, the resistance value of the thermistor 71 decreases, and the base current of the third transistor 30 increases. Accordingly, as shown in FIG. 3, the cumulative delay time environment temperature rises ts that increase, because the interval B is increased, the intervals A and C will not be not occur overlap, arm short circuit due to an increase in environmental temperature Can be prevented.

  As described above, the switch element driving device 1c according to the second embodiment includes the first signal input terminal 6 that controls ON and OFF of the first switch element 2, and ON and OFF of the second switch element 4. The first switch element driving means 3c which receives the control signal from the second signal input terminal 7 for controlling the first and second signal input terminals 6 and outputs ON and OFF drive signals for the first switch element 2. When the environmental temperature is higher than a preset temperature, the control signal is received from the second signal input terminal 7, and the ON timing of the drive signal to be output has a longer delay as the temperature rises than the ON timing of the control signal. As shown, the second switch element drive means 5b for outputting ON and OFF drive signals to the second switch element 4 is provided.

  The switch element driving device 1c drives the switching device 8. The switching device 8 includes a first switch element 2 and a second switch element 4, and the first switch element 2 and the second switch element 4 are connected in series. The first and second switch elements 2 and 4 are turned on and off by a drive signal output from the switch element driving device 1c, and a signal is transmitted from the connection portion 11 between the first switch element 2 and the second switch element 4. Output. The energy of the signal output from the connection unit 11 is stored in the reactor 9.

  With this configuration, even when the environmental temperature rises, the ON section of the second switch element 4 is delayed with respect to the ON section of the first switch element 2, so that an arm short circuit can be prevented.

Embodiment 3 FIG.
Next, a switching element driving device according to Embodiment 3 of the present invention will be described. FIG. 7 is a circuit diagram illustrating an example of the switch element driving device according to the third embodiment. In FIG. 7, reference numeral 1d indicates a switch element driving apparatus according to Embodiment 3, and reference numeral 5c indicates a second switch element driving means constituting the switch element driving apparatus 1d.

  The second switch element driving means 5c is connected between the sixth switch element 80, the drive power supply 28 and the drain of the sixth switch element 80, and the drain-source current of the sixth switch element 80 is obtained. The limiting resistor 81, the thermistor 82 connected between the emitter of the fourth transistor 32 and the gate of the second switch element 4, and between the emitter of the fifth transistor 33 and the gate of the second switch element 4 A resistor 83 is provided.

Switching element 80 of the sixth is an N-channel MOSFET, the ON and OFF is inverted signals from the fifth switching element 25, so that the second Rubeki signal is converted into a driving voltage of the switch element 4 inverted to. The resistor 83 limits the discharge amount of the gate current of the second switch element 4 and adjusts the switch speed of the fall of the gate-source voltage (input signal: Vgs) of the second switch element 4. The thermistor 82 limits the charge amount of the gate current of the second switch element 4, and the resistance value of the thermistor 82 becomes larger than the resistance value of the resistor 83 due to the temperature rise, and the gate / source of the second switch element 4 The switch speed at the rise of the inter-voltage (input signal: Vgs) is made slower than room temperature. The other configuration of the switch element driving device 1d is the same as that of the first embodiment, and the same reference numerals are given and the description thereof is omitted.

FIG. 8 is a timing chart showing operations of the switching element driving device 1d and the switching device 8 according to the third embodiment.
In FIG. 8, the signals (k) to (m), (o), and (p) are the same as (e) to (g), (i), and (j) of the first embodiment described in FIG. The signal (n) indicates the gate-source voltage (input signal: Vgs) of the second switch element 4.

  Here, the charge amount of the gate current and the switching speed of the switch element will be described. MOSFETs have input parasitic capacitance. If this input parasitic capacitance is constant, if the charge amount of the gate current is small, the switching speed of the rise of the gate-source voltage of the switch element will be slow, and the charge amount of the gate current will be large. For example, the switching speed at the rise of the gate-source voltage of the switch element is increased.

  Accordingly, since the resistance value of the thermistor 82 increases due to the temperature rise, the charge amount of the gate current of the second switch element 4 becomes smaller than that at room temperature, and the rise of the gate-source voltage Vgs of the second switch element 4 increases. Switch speed is slow. That is, the time until the gate-source voltage Vgs reaches the threshold voltage at which energization between the drain and source of the second switch element 4 is started is delayed (the start of energization between the drain and source is delayed).

  From the above, since the section B shown in FIG. 8 increases, the section A and the section C do not overlap each other, and an arm short circuit due to an increase in the environmental temperature can be prevented.

  As described above, the switch element drive device 1d according to the third exemplary embodiment includes the first signal input terminal 6 that controls ON and OFF of the first switch element 2 and the ON and OFF of the second switch element 4. The first switch element drive which receives the control signal from the second signal input terminal 7 for controlling the control signal and the first signal input terminal 6 and outputs ON and OFF drive signals to the first switch element 2 When the environmental temperature is higher than the preset temperature with the means 3a, the control signal is received from the second signal input terminal 7, and the ON timing of the output drive signal is delayed as the temperature rises. The second switch element drive means 5c for outputting ON and OFF drive signals to the second switch element 4 is provided so as to increase.

  The switch element driving device 1d drives the switching device 8. The switching device 8 includes a first switch element 2 and a second switch element 4, and the first switch element 2 and the second switch element 4 are connected in series. The first and second switch elements 2 and 4 are turned on and off by a drive signal output from the switch element drive device 1 d, and a signal is transmitted from the connection portion 11 between the first switch element 2 and the second switch element 4. Output. The energy of the signal output from the connection unit 11 is stored in the reactor 9.

  With this configuration, even when the environmental temperature rises, the ON section of the second switch element 4 is delayed with respect to the ON section of the first switch element 2, so that an arm short circuit can be prevented.

  In the above embodiment, the thermistor 82 is connected to the emitter of the fourth transistor 32 constituting the second switching element driving means 5c and the gate of the second switch element 4, and the emitter of the fifth transistor 33 is connected. In the above description, the resistor 83 is connected to the gate of the second switch element 4, but the emitter of the fourth transistor 32 and the emitter of the fifth transistor 33 are connected to each other by using a diode, a resistor, and a thermistor. It may be configured. Specific examples thereof will be described below.

  FIG. 9 is a circuit diagram illustrating another example of the switch element driving device according to the third embodiment. In FIG. 9, the emitter of the fourth transistor 32 and the emitter of the fifth transistor 33 are connected to each other. Here, reference numeral 1e represents another example of the switch element driving apparatus according to the third embodiment. Reference numeral 90 denotes a thermistor, reference numeral 91 denotes a diode, and reference numeral 92 denotes a resistance.

  The thermistor 90 is connected between the emitters of the fourth and fifth transistors 32 and 33 and the gate of the second switch element 4. The diode 91 and the resistor 92 are connected in series, and the series connection body is connected to the thermistor 90 in parallel. In addition, about another structure, it is the same as that of Embodiment shown in FIG. 7, The same code | symbol is attached | subjected and description is abbreviate | omitted.

  The thermistor 90 limits the charge amount of the gate current of the second switch element 4, the resistance value becomes larger than the resistance 92 due to the temperature rise, and the switch speed of the rise of the gate-source voltage Vgs of the second switch element 4. Make it slower than room temperature. The diode 91 has a cathode connected to the emitters of the fourth and fifth transistors 32 and 33 and an anode connected to the resistor 92, and is energized only when the gate current of the second switch element 4 is discharged. The resistor 92 limits the discharge amount of the gate current of the second switch element 4 and adjusts the switch speed of the fall of the gate-source voltage Vgs of the second switch element 4.

  According to the switch element driving device 1e configured as described above, the resistance value of the thermistor 90 increases due to the temperature rise, so that the charge amount of the gate current of the second switch element 4 becomes smaller than that at room temperature, and the first The switch speed of the rise of the gate-source voltage Vgs of the second switch element 4 is reduced. That is, the time until the gate-source voltage Vgs reaches the threshold voltage at which energization between the drain and source of the second switch element 4 is started is delayed (the start of energization between the drain and source is delayed). Accordingly, the output signal is equivalent to the embodiment shown in FIG. 7, and the same effect can be obtained.

  In the above embodiment, the thermistor 90 is connected between the emitters of the fourth and fifth transistors 32 and 33 and the gate of the second switch element 4, but the second switch element 4 is turned on. The method of slowing the switching speed is to connect the thermistor 90 to the base or collector of the fourth transistor 32 to reduce the charge amount of the gate current of the second switch element 4 as the temperature rises. The thermistor 90 is not necessarily connected to the gate of the second switch element 4.

  Further, in the first to third embodiments, the ON timing of the drive signal output from the second switch element driving means 5a to 5d is less than the ON timing of the control signal from the second signal input terminal 7. The case where the ON / OFF drive signal of the second switch element 4 is output so as to increase the delay as the temperature rises has been described. However, even if this concept is applied to the first switch element driving means 3a to 3c. Good.

The above concept may be applied to both the first switch element driving means 3a to 3c and the second switch element driving means 5a to 5d.
That is, when the environmental temperature rises, the output signals of the second switch element driving units 5a to 5d are delayed with respect to the OFF of the output signals of the first switch element driving units 3a to 3c. An arm short circuit is prevented by delaying the ON section of the second switch element 4 with respect to the ON section of the switch element 2. Alternatively, by delaying the switching speed of the output signal ON of the second switch element driving means 5a to 5d relative to the switching speed of the output signal OFF of the first switch element driving means 3a to 3c when the environmental temperature rises, The ON section of the second switch element 4 is delayed with respect to the ON section of the first switch element 2 to prevent an arm short circuit.

  In addition, when the environmental temperature rises, the output signals of the first switch element driving means 3a to 3c are delayed with respect to the OFF of the output signals of the second switch element driving means 5a to 5d. The ON section of the first switch element 2 is delayed with respect to the ON section of the switch element 4, thereby preventing an arm short circuit. Alternatively, when the environmental temperature rises, the ON switching speed of the output signals of the first switch element driving means 3a to 3c is delayed with respect to the OFF switching speed of the output signals of the second switch element driving means 5a to 5d, and the second The ON section of the first switch element 2 may be delayed with respect to the ON section of the switch element 4 to prevent an arm short circuit.

  In each of the above embodiments, the signals input to the first signal input terminal 6 and the second signal input terminal 7 can be realized by combining a microcomputer, a logic circuit, and the like.

  In each of the above-described embodiments, the MOSFET is described as an example of the switching element. However, the switching element such as an IGBT can also be controlled, and the switching element is not necessarily limited to the MOSFET.

  Further, in the second and third embodiments, the thermistor has been described as an example of a resistor whose resistance value varies depending on the environmental temperature, but by using a resistor having a different temperature coefficient, a resistance value difference can be caused by an increase in the environmental temperature. Therefore, it is not necessarily limited to the thermistor.

  As described above, the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified and omitted.

1a, 1b, 1c, 1d, 1e switch element driving device, 2 first switch element, 3a, 3b, 3c, first switch element driving means, 4 second switch element, 5a, 5b, 5c, 5d 2 switch element driving means, 6 first signal input terminal, 7 second signal input terminal, 8 switching device, 9 reactor, 10 power supply, 11 connection section, 12 3rd switch element, 13, 14, 16, 18, 19, 20, 23, 24 Resistance, 15, 28 Drive power supply, 17a, 17b Fourth switch element, 21 First transistor, 22 Second transistor, 25 Fifth switch element, 26, 27, 29 , 31, 34, 35, 50, 51, 52 Resistor, 30 Third transistor, 32 Fourth transistor, 33 Fifth transistor, 60 Sixth transistor Transistor, 61, 62, 63, 65, 66, 67, 69, 70 resistor, 64 seventh transistor, 68 eighth transistor, 71, 82, 90 thermistor, 80 sixth switch element, 81, 83, 92 Resistor, 91 diode.

Claims (4)

In the switching element driving device that performs synchronous rectification control of the first and second switching elements of the switching apparatus including the first and second switching elements connected in series,
A first control signal input terminal to which a control signal of the first switch element is input;
A second control signal input terminal to which a control signal of the second switch element is input;
First switch element driving means for receiving the control signal from the first control signal input terminal and outputting ON and OFF drive signals to the first switch element;
Second switch element driving means for receiving the control signal from the second control signal input terminal and outputting ON and OFF drive signals to the second switch element;
With
The control signal input to the first and second control signal input terminals is a control signal for controlling the first switch element and the second switch element so as not to be turned ON at the same time.
The first switch element driving means outputs a drive signal that delays the ON speed of the first switch element with an increase in environmental temperature with respect to the OFF speed of the second switch element. Switch element driving device. The second switch element driving means outputs a drive signal that delays the ON speed of the second switch element with an increase in environmental temperature with respect to the OFF speed of the first switch element. The switch element driving device according to claim 1. In the switching element driving device that performs synchronous rectification control of the first and second switching elements of the switching apparatus including the first and second switching elements connected in series,
A first control signal input terminal to which a control signal of the first switch element is input;
A second control signal input terminal to which a control signal of the second switch element is input;
First switch element driving means for receiving the control signal from the first control signal input terminal and outputting ON and OFF drive signals to the first switch element;
Second switch element driving means for receiving the control signal from the second control signal input terminal and outputting ON and OFF drive signals to the second switch element;
With
The control signal input to the first and second control signal input terminals is a control signal for controlling the first switch element and the second switch element so as not to be turned ON at the same time.
The second switch element driving means outputs a drive signal that delays the ON speed of the second switch element with an increase in environmental temperature with respect to the OFF speed of the first switch element. Switch element driving device. 4. The drive signal for delaying the ON speed of the first or second switch element with an increase in environmental temperature is formed by a resistance element whose resistance value varies depending on the environmental temperature. The switch element driving device according to any one of the above.

Images