JP2010093885A - Drive circuit for power switching element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a system in the prior art that it is difficult to strike a balance between the suppression of the power loss of a voltage control type power switching element Sw and the suppression of surge. <P>SOLUTION: The gate of a power switching element Sw is connected to the positive electrode of a power supply 30 via a resistor 34 for charge, a bipolar transistor 32 for charge, and a MOS transistor 40 for charge. To switch on the power switching element Sw, the gate of the power switching element Sw is charged with positive charge by turning on a bipolar transistor 32 for charge to begin with. Then, after the power switching element Sw is switched on, a MOS transistor 40 for charge is turned on. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a drive circuit for a power switching element that drives a voltage-controlled power switching element.

  An inverter including a series connection body of a pair of power switching elements that connect each phase of a three-phase motor to a positive electrode side and a negative electrode side of a DC power supply is well known. Here, a free wheel diode is connected in antiparallel to each of the pair of power switching elements. When a forward current flows through a freewheeling diode connected to one of the pair of power switching elements, when the other power switching element is turned on, the freewheeling diode is moved from its cathode side to its anode side. Recovery current flows. The recovery current increases and then decreases and eventually becomes zero, but when starting to decrease, a surge voltage is superimposed on both ends of the freewheel diode. And this surge voltage becomes so small that the amount of voltage drops between the input-output terminals of a power switching element is large.

  Therefore, conventionally, as seen in, for example, the following Patent Document 1, a high-potential side bipolar transistor for charging a positive charge to the gate of an insulated gate bipolar transistor (IGBT) as a power switching element and a positive gate from the gate of the IGBT. It has also been proposed to provide a series connection body of low potential side bipolar transistors for discharging electric charges, and to apply an IGBT drive signal to the bases of the pair of bipolar transistors via a CR circuit. Thus, by using the pair of bipolar transistors as an emitter follower, the output voltage of the emitter can be adjusted according to the time constant of the CR circuit. Thereby, the charge rate of a gate can be adjusted and a surge can be suppressed suitably by extension.

Other examples of this type of drive circuit are described in Patent Document 2 below, for example.
JP-A-5-161343 JP 2000-295838 A

  By the way, the voltage at the output terminal (emitter) of the bipolar transistor on the high potential side is lower than the voltage at the input terminal (collector). For this reason, compared with the case where a MOS field effect transistor is used, for example, the voltage which can be applied to the gate of IGBT becomes small. When the voltage that can be applied to the gate is small, the amount of voltage drop between the input terminal and the output terminal of the IGBT when the IGBT is in the on state increases, and the power loss increases accordingly. For this reason, it is required to select an element having sufficient thermal capacity as the IGBT. Further, since the output voltage of the bipolar transistor is likely to change according to the temperature, when the output voltage decreases according to the temperature, the loss of the IGBT further increases, and as a result, the IGBT has a further thermal margin. Is required to be selected.

  Here, when the gate of the IGBT is connected to the MOS field effect transistor via the gate resistance instead of being connected to the bipolar transistor on the high potential side via the gate resistance, the voltage that can be applied to the gate of the IGBT is Although it can be increased, there is a concern that it is difficult to achieve both suppression of surges associated with switching of the switching state and reduction of power loss during switching of the switching state. That is, when the gate resistance between the MOS field effect transistor and the gate of the IGBT is increased, the switching speed of the switching state is reduced, so that surge can be suppressed, but power loss at the time of switching increases. . On the other hand, when the gate resistance between the MOS field effect transistor and the gate of the IGBT is reduced, the switching speed of the switching state is increased, so that the power loss at the time of switching can be reduced but the surge increases.

  The present invention has been made in order to solve the above-described problems, and the object thereof is a power switching element capable of achieving both the suppression of power loss and the suppression of surge of a voltage control type power switching element. The drive circuit is provided.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to a first aspect of the present invention, there is provided a drive circuit for driving a voltage-controlled power switching element, wherein an electrical connection is established between a power source for charging a conduction control terminal of the power switching element and a conduction control terminal. As a charging opening / closing means that opens and closes electrically, a current-controlled switching element and a voltage-controlled switching element are provided.

  In the above invention, by providing the current control type switching element, the degree of freedom of setting the charging mode of the conduction control terminal of the power switching element is increased as compared with the case where only the voltage control type switching element is used. Setting that can suitably suppress a surge is possible. Furthermore, by providing the voltage control type switching element, it is possible to increase the voltage of the conduction control terminal of the power switching element as compared with the case where only the current control type switching element is used. For this reason, the said invention can aim at suitable coexistence with suppression of the power loss and suppression of a surge of a voltage control type power switching element.

  According to a second aspect of the present invention, in the first aspect of the present invention, the current control type switching element is an NPN type bipolar transistor.

  According to a third aspect of the present invention, in the second aspect of the present invention, the rate of increase in the output voltage of the NPN bipolar transistor within a predetermined period from the start of charging of the charge to the conduction control terminal is mitigated. It is characterized by providing a relaxing means.

  When a diode is connected in series with the power switching element, a recovery current flows through the diode during the charging period of the conduction control terminal, thereby generating a surge. On the other hand, it is known that surge can be suppressed by suppressing the charging speed of the conduction control terminal. In the above invention, in view of this point, the surge can be suitably suppressed by providing the mitigating means.

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the mitigating means includes a delay circuit that delays a change in the operation signal of the power switching element, and the output voltage of the delay circuit is the NPN bipolar transistor. It is a means applied to the base of this.

  In the said invention, a mitigating means can be comprised appropriately by providing a delay circuit.

  According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the charging opening / closing means is closed to charge the conduction control terminal of the power switching element with a positive charge. The processing is after the timing when the voltage of the conduction control terminal of the power switching element becomes equal to or higher than a threshold voltage (threshold voltage for turning on the power switching element) after the current control type switching element is turned on. In the step, the voltage-controlled switching element is turned on.

  In the above-described invention, the voltage control type switching element can be used as an application for securing a voltage to be applied to the conduction control terminal after the timing when the power switching element is turned on.

  The invention according to claim 6 is the invention according to any one of claims 2 to 5, wherein the conduction control terminal and the positive charge are discharged so as to discharge the positive charge from the conduction control terminal of the power switching element. As a discharge opening / closing means for electrically opening / closing between the discharge path and the downstream side of the discharge path, a PNP bipolar transistor is provided.

  In the above invention, since the charging opening / closing means and the discharging opening / closing means include the NPN type bipolar transistor and the PNP type bipolar transistor, respectively, a command to turn on one of them is given and the other is given. When the command to switch to the off state is given, the process for generating the dead time can be deleted.

  According to a seventh aspect of the invention, in the sixth aspect of the invention, the discharge opening / closing means further includes a voltage control type switching element.

  According to an eighth aspect of the invention, in the seventh aspect of the invention, the process of closing the discharge opening / closing means to discharge positive charges from the conduction control terminal of the power switching element is of the current control type. After the switching element is turned on, the voltage-controlled switching element after the timing when the voltage at the conduction control terminal of the power switching element becomes equal to or lower than a threshold voltage (threshold voltage for turning the power switching element off). This is a process for turning on.

  The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein a diode is connected in series to the power switching element.

(First embodiment)
Hereinafter, an embodiment in which a drive circuit of a power switching element according to the present invention is applied to a drive circuit of a power conversion circuit of a hybrid vehicle will be described with reference to the drawings.

  FIG. 1 shows the system configuration of this embodiment. As shown in the figure, a motor generator 10 as an in-vehicle rotating machine is connected to a high voltage battery 12 via an inverter IV. The inverter IV is configured by connecting three series-connected bodies of a high-potential side power switching element Swp and a low-potential side power switching element Swn in parallel. The connection points of these series connection bodies are connected to the respective phases of the motor generator 10. Between the input / output terminals (between collector and emitter) of the high potential side power switching element Swp and the low potential side power switching element Swn, there is a high potential side freewheel diode FDp and a low potential side freewheel diode. The cathode and anode of FDn are connected.

  A drive circuit DC is connected to the conduction control terminals (gates) of the power switching elements Swp and Swn constituting the inverter IV. Thereby, the power switching elements Swp and Swn are driven by the microcomputer (microcomputer 20) using the low voltage battery 16 as a power source via the drive circuit DC and the interface 14. Here, the interface 14 includes an insulating means such as a photocoupler that insulates the high voltage system including the inverter IV and the converter CV from the low voltage system including the microcomputer 20. The microcomputer 20 controls operation signals gup, gvp, and gwp for operating the power switching element Swp for each of the U phase, V phase, and W phase of the inverter IV based on detection values of various sensors (not shown), and power switching. Operation signals gn, gvn, and gwn for operating the element Swn are generated and output. Thereby, the switching elements Swp and Swn are operated by the microcomputer 20 via the drive circuit DC. The high-potential side operation signals gup, gvp, and gwp of each phase and the low-potential side operation signals gun, gvn, and gwn are respectively a high-potential side switching element Swp and a low-potential side switching element. Swn may be driven complementarily to each other. In other words, during the period when one of the operation signals is a signal for turning on, the other operation signal may be a signal for turning off.

  Each of the power switching elements Swp and Swn is a switching element that has an input terminal and an output terminal that are uniquely defined and prevents a current from flowing from the output terminal to the input terminal. Specifically, these are constituted by insulated gate bipolar transistors (IGBT). For this reason, in a situation where a current can flow through the power switching element Swp on the high potential side, by turning it off, the current does not flow through the power switching element Swn on the low potential side, and this is antiparallel. A current flows through the freewheeling diode FDn connected to. Further, in a situation where a current can flow through the low potential side power switching element Swn, by turning it off, no current flows through the high potential side power switching element Swp, and this is in antiparallel. A current flows through the connected freewheeling diode FDp. In this case, when the power switching element Swp (Swn) is turned on again, a recovery current flows through the freewheel diode FDn (FDp). This recovery current causes a surge voltage when the power switching elements Swp and Swn are turned on. Hereinafter, this will be further described with reference to FIG.

  FIG. 2 illustrates a situation where a current can flow through the power switching element Swp on the high potential side. Under such circumstances, as shown in FIG. 2A, when the high-potential side power switching element Swp is in the OFF state, the collector current ic is zero, and the forward current flows through the low-potential-side freewheel diode FDn. id flows. At this time, since the voltage Vfd across the free wheel diode FDn is substantially zero, the voltage Vce between the emitter and the collector of the power switching element Swp on the high potential side is about the voltage Vdc of the high voltage battery 12.

  Here, when the power switching element Swp on the high potential side is turned on at time t1, the collector current ic gradually increases as shown in FIG. Along with this, the current id flowing through the free wheel diode FDn gradually decreases to zero. At this time, the voltage Vce between the collector and the emitter is obtained by subtracting the product of the current change rate of the collector current ic and the inductor component existing in the wiring of the inverter IV (schematically represented as wiring inductor Lp in the figure) from the power supply voltage Vdc. It becomes the value.

  When the current flowing through the free wheel diode FDn becomes zero, a recovery current that is a reverse current starts to flow due to the carrier accumulation effect of the free wheel diode FDn. At this time, a recovery current flows between the collector and the emitter of the switching element Swp on the high potential side in addition to the current (load current) exchanged with the motor generator 10. After that, the carrier at the junction of the free wheel diode FDn decreases, and the recovery current gradually changes from increasing to zero and eventually becomes zero. Here, when the recovery current changes from gradual increase to gradual decrease, a surge voltage is generated by the current change rate of the recovery current and the voltage component generated by the inductor component existing in the wiring of the inverter IV.

  FIG. 3 shows a circuit configuration of the drive circuit DC according to the present embodiment having an effect of suppressing the surge voltage. In the following description, the power switching elements Swp and Swn are collectively expressed as a power switching element Sw, and the free wheel diodes FDp and FDn are collectively expressed as a free wheel diode FD. Further, the operation signals gup, gvp, gwp, gun, gvn, and gwn are collectively expressed by the operation signal g.

  As shown in the figure, in the drive circuit DC, the collector of a charging bipolar transistor 32, which is an NPN-type bipolar transistor, is connected to the positive electrode of a power source 30 having a voltage Vin, and a charging resistor 34 is connected to the emitter thereof. The gate of the power switching element Sw is connected through the via. The collector of a discharge bipolar transistor 36, which is a PNP bipolar transistor, is connected to the negative electrode of the power supply 30, and the gate of the power switching element Sw is connected to the emitter via a discharge resistor 38. . Further, a charging MOS transistor 40 made of a P-channel MOS field effect transistor is connected in parallel between the collector and emitter of the charging bipolar transistor 32.

  On the other hand, the input circuit 42 is a circuit that receives the operation signal g and operates the charging bipolar transistor 32, the discharging bipolar transistor 36, and the charging MOS transistor 40 in accordance with the input. Here, the operation of the charging bipolar transistor 32 and the discharging bipolar transistor 36 is performed by the input circuit 42 outputting to the delay circuit 44 a signal obtained by converting the operation signal g into a predetermined voltage. That is, the input circuit 42 includes a buffer circuit including a pair of bipolar transistors or MOS field effect transistors to which the voltage Vin of the power supply 30 is applied, and a signal corresponding to the operation signal g is transmitted through the buffer circuit to the delay circuit 44. Output to.

  The delay circuit 44 is a CR circuit including a resistor 44a as a linear element and a capacitor 44b. The voltage at the connection point between the resistor 44a and the capacitor 44b is applied to the respective bases of the charging bipolar transistor 32 and the discharging bipolar transistor 36 as an output signal (delay voltage Vd) of the delay circuit 44. The delay circuit 44 is provided mainly for relaxing the rising speed of the output voltage Vout1 of the emitter of the charging bipolar transistor 32 with respect to the rising speed of the operation signal g. That is, since the charging bipolar transistor 32 constitutes an emitter follower circuit, the output voltage Vout1 from the emitter becomes a voltage (delay voltage Vd) applied to the base (more precisely, from now on, the base and emitter The voltage drop amount is between Vbe).

  The input circuit 42 further has a function of turning on the charging MOS transistor 40 when a predetermined period elapses after the operation signal g instructs that the power switching element Sw be switched from the off state to the on state. . Thereby, the voltage of the gate can be held at the voltage Vin of the power source 30 after the charging of the gate of the power switching element Sw is completed.

  FIG. 4 shows a switching processing mode for turning on the power switching element Sw according to the present embodiment. Specifically, FIG. 4A shows the transition of the operation signal g, FIG. 4B shows the transition of the output signal voltage (drive voltage Vm) of the input circuit 42, and FIG. The transition of the voltage (delay voltage Vd) of the output signal of the delay circuit 44 is shown, and FIG. 4D shows the transition of the output voltage Vout1 of the charging bipolar transistor 32. Further, FIG. 4E shows the transition of the charging current of the gate of the power switching element Sw, FIG. 4F shows the transition of the gate voltage Vg of the power switching element Sw, and FIG. The transition of the state of the charging MOS transistor 32 is shown.

  As shown in the figure, the drive voltage Vm rises when the operation signal g rises, but the rising speed of the delay voltage Vd becomes slower than the rising speed of the drive voltage Vm. For this reason, the rising speed of the output voltage Vout1 is also slower than the rising speed of the operation signal g and the drive voltage Vm. Therefore, the rising speed of the gate voltage Vg is moderate as compared with the case where the delay circuit 44 is not provided.

  The output voltage Vout1 rises gently and then becomes a constant value. In the present embodiment, the period in which the recovery current flows through the freewheeling diode FD connected in series due to the switching of the power switching element Sw to the on state is included in the period of gradual increase. The time constant of the delay circuit 44 is set. Thereby, suppression of the surge resulting from a recovery current can be aimed at.

  On the other hand, the gate charging current flows according to the differential pressure between the output voltage Vout1 and the gate voltage Vg. However, this charging current can be controlled by the charging resistor 34. For this reason, by setting the charging resistor 34 to have a relatively low resistance, the charging speed of the gate after the output voltage Vout1 becomes a substantially steady value can be increased. For this reason, the time required for the power switching element Sw to switch from the off state to the on state can be shortened, and as a result, power loss associated with switching of the switching state can be reduced.

  When a predetermined period T elapses after the operation signal g instructs the power switching element Sw to be turned on, the charging MOS transistor 40 is turned on. Here, the predetermined period T is set to a timing at which the charging of the gate of the power switching element Sw by the charging bipolar transistor 32 is substantially completed. Thereby, after the power switching element Sw is turned on, the gate voltage Vg can be raised to the voltage Vin of the power supply 30 and held.

  As described above, in this embodiment, the output voltage of the delay circuit 44 is applied to the gate of the power switching element Sw via the emitter follower, so that the gate can be suppressed in accordance with the time constant of the delay circuit 44. It is possible to adjust the charging process mode. By taking a surge countermeasure by using a bipolar transistor in this way, it is possible to perform charge control as if the resistance value of the charging resistor 34 is variable during the gate charging period. For this reason, compared with the case where a surge countermeasure is performed only by the charging resistor 34, the surge countermeasure can be more suitably performed while suppressing an increase in power loss associated with switching of the switching state.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) A charging bipolar transistor 32 as a charging opening / closing means for electrically switching between a power source 30 and a gate for charging a positive charge to the conduction control terminal (gate) of the power switching element Sw, and charging MOS transistor 40 is provided. Thereby, suitable coexistence with suppression of the power loss of the power switching element Sw and suppression of a surge can be aimed at.

  (2) The charging bipolar transistor 32 was used as an emitter follower, and the output voltage (delay voltage Vd) of the delay circuit 44 was applied to its base. Thereby, the charge speed in the initial charging period of the gate of the power switching element Sw can be relaxed, and the surge can be suitably suppressed.

  (3) The charging MOS transistor 40 is turned on after the timing when the gate voltage of the power switching element Sw becomes equal to or higher than the threshold voltage for turning on the power switching element Sw by turning on the charging bipolar transistor 32. It was. As a result, it is possible to reliably perform the processing for suppressing the surge countermeasures and to avoid a through current from flowing between the charging MOS transistor 40 and the discharging bipolar transistor 36.

  (4) A discharging bipolar transistor 36 is provided as a switching element for discharging positive charges from the gate of the power switching element Sw. As a result, the charging of the gate of the power switching element Sw based on the operation signal g can be easily avoided while avoiding the occurrence of a through state in which both the charging bipolar transistor 32 and the discharging bipolar transistor 36 are simultaneously turned on. Discharge treatment can be performed.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 5 shows a circuit configuration of the drive circuit DC according to the present embodiment. In FIG. 5, members corresponding to those shown in FIG. 3 are given the same reference numerals for the sake of convenience.

  In the present embodiment, the output voltage Vout1 of the charging bipolar transistor 32 is monitored, and when this becomes equal to or higher than the threshold voltage, the charging MOS transistor 40 is turned on. The threshold voltage is set to a value lower than the voltage Vin of the power supply 30 by a voltage drop Vbe between the base and emitter of the charging bipolar transistor 32. Thereby, the charging MOS transistor 40 can be turned on during the charging process of the gate of the power switching element Sw by the charging bipolar transistor 32.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 6 shows a circuit configuration of the drive circuit DC according to the present embodiment. In FIG. 6, members corresponding to those shown in FIG. 3 are given the same reference numerals for convenience.

  In the present embodiment, the gate voltage Vg of the power switching element Sw is monitored, and when this becomes equal to or higher than the threshold voltage, the charging MOS transistor 40 is turned on. The threshold voltage is set to a value lower than the voltage Vin of the power supply 30 by a voltage drop Vbe between the base and emitter of the charging bipolar transistor 32. Also by this, the charging MOS transistor 40 can be turned on after the charging bipolar transistor 32 completes the charging of the gate of the power switching element Sw as in the first embodiment.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 7 shows a switching processing mode for turning on the power switching element Sw according to the present embodiment. 7A to 7G correspond to the previous FIGS. 4A to 4G.

  As shown in the figure, also in the present embodiment, the charging MOS transistor 40 is turned on when a predetermined period T elapses after the operation signal g instructs the power switching element Sw to be turned on. However, in the present embodiment, the predetermined period T is set to a timing as early as possible after the timing when the power switching element Sw starts to be turned on. Specifically, it is set to a timing at which the gate voltage of the power switching element Sw becomes the voltage in the mirror period and the recovery current of the free wheel diode FD connected in series to the power switching element Sw becomes zero. Thereby, after the recovery current becomes zero, the gate voltage of the power switching element Sw can be quickly raised to the voltage Vin of the power supply 30.

(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to the drawings, focusing on differences from the first embodiment.

  FIG. 8 shows a circuit configuration of the drive circuit DC according to the present embodiment. In FIG. 8, members corresponding to those shown in FIG. 3 are given the same reference numerals for the sake of convenience.

  As shown in the figure, in this embodiment, a discharge MOS transistor 50 as an N-channel MOS field effect transistor is connected in parallel between the collector and emitter of the discharge bipolar transistor 36.

  FIG. 9 shows a switching processing mode of the power switching element Sw according to the present embodiment to the off state. Specifically, FIG. 9A shows the transition of the operation signal g, FIG. 9B shows the transition of the emitter voltage (output voltage Vout1) of the discharging bipolar transistor 36, and FIG. The transition of the gate voltage of the power switching element Sw is shown, and FIG. 9D shows the transition of the state of the discharge MOS transistor 50.

  As shown in the figure, in this embodiment, when the operation signal g instructs to switch the power switching element Sw to the off state, the discharge bipolar transistor 36 is first turned on, so that the power switching element Sw is turned on. A positive charge is discharged from the gate. Then, when the predetermined period T has elapsed from the instructed timing, the discharge MOS transistor 50 is turned on, whereby the gate voltage Vg of the power switching element Sw is lowered to the negative potential of the power supply 30 and held. . Here, the predetermined period T is set to a time required for completing the discharge process of the gate of the power switching element Sw by the discharge bipolar transistor 36.

(Sixth embodiment)
Hereinafter, the sixth embodiment will be described with reference to the drawings with a focus on differences from the fifth embodiment.

  FIG. 10 shows a circuit configuration of the drive circuit DC according to the present embodiment. In FIG. 10, members corresponding to those shown in FIG. 8 are given the same reference numerals for convenience.

  In the present embodiment, the output voltage Vout2 of the discharge bipolar transistor 36 is monitored, and when this becomes equal to or lower than the threshold voltage, the discharge MOS transistor 50 is turned on. The threshold voltage is set to about the voltage drop amount Vbe between the base and the emitter of the discharging bipolar transistor 36. As a result, the discharging MOS transistor 50 can be turned on during the discharging process of the gate of the power switching element Sw.

(Seventh embodiment)
Hereinafter, the seventh embodiment will be described with reference to the drawings with a focus on differences from the fifth embodiment.

  FIG. 11 shows a circuit configuration of the drive circuit DC according to the present embodiment. In FIG. 11, members corresponding to those shown in FIG. 10 are given the same reference numerals for convenience.

  In the present embodiment, the gate voltage Vg of the power switching element Sw is monitored, and the discharge MOS transistor 50 is turned on when the gate voltage Vg is equal to or lower than the threshold voltage. The threshold voltage is set to about the voltage drop amount Vbe between the base and the emitter of the discharging bipolar transistor 36. This also makes it possible to turn on the discharge MOS transistor 50 after the discharge bipolar transistor 36 completes the discharge of the gate of the power switching element Sw, as in the fifth embodiment.

(Eighth embodiment)
Hereinafter, the eighth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 12 shows a switching processing mode of the power switching element Sw according to the present embodiment to the on state. FIGS. 12A to 12D correspond to the previous FIGS. 9A to 9D.

  As shown in the figure, also in the present embodiment, the discharge MOS transistor 50 is turned on when a predetermined period T elapses after the operation signal g instructs the power switching element Sw to be turned off. However, in the present embodiment, the predetermined period T is set to a timing as early as possible after the timing when the power switching element Sw starts shifting to the off state. Specifically, the timing is set while the gate voltage of the power switching element Sw is at the mirror period voltage. Thereby, the discharge rate of the power switching element Sw can be increased. For this reason, it is possible to suitably compensate for the decrease in the gate voltage decrease rate due to the provision of the delay circuit 44 by cooperation with the discharge resistor 38. Furthermore, since the degree of freedom for controlling the discharge rate as desired can be improved, the rate of decrease in the gate voltage can be controlled as desired.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  -You may change previous 4th Embodiment by the change of 3rd Embodiment with respect to previous 1st Embodiment.

  The previous eighth embodiment may be changed by changing the seventh embodiment with respect to the previous fifth embodiment.

  The delay circuit 44 is not limited to a CR circuit. For example, a diode having a forward direction from the capacitor 44b side to the input circuit 42 side may be provided in parallel with the resistor 44a. In this case, when the power switching element Sw is switched to the off state, the rate of decrease in the output voltage of the discharge bipolar transistor 36 can be increased. For example, an LCR circuit may be used.

  A delay circuit is used as a relaxation means for relaxing the rising speed of the output voltage Vout1 of the charging bipolar transistor 32 at the initial stage of charging the positive charge to the gate of the power switching element Sw with respect to the logic inversion speed of the operation signal g. Not exclusively. For example, the base current of the charging bipolar transistor 32 may be variably set based on the priority of reducing the power loss of the power switching element Sw and suppressing the surge voltage. Even in this case, by switching to the ON state of the power switching element Sw using the charging bipolar transistor 32 instead of the charging MOS transistor 40, there is a demand for suppression of surge and reduction of power loss. Can respond appropriately. In addition, by using the charging MOS transistor 40 at this time, the gate voltage of the power switching element Sw can be increased as compared with the case where only the charging bipolar transistor 32 is used.

  The drive circuit DC is not limited to the one provided with the discharge bipolar transistor 36. For example, the discharge treatment may be performed by the discharge MOS transistor 50 without providing the discharge bipolar transistor 36.

  The drive circuit DC is not limited to the gate voltage when the power switching element Sw is turned off substantially zero (the same potential as the output terminal potential), but is negative (lower potential than the output terminal potential). May be. In order to realize this, it is particularly effective to provide the discharge MOS transistor 50.

  The timing for turning on the discharge MOS transistor 50 is not limited to the timing exemplified in the above embodiments. For example, the timing may be as early as possible under the condition that no through current flows through the charging MOS transistor 40 and the discharging MOS transistor 50.

  In each of the above embodiments, the charging resistor 34 and the discharging resistor 38 are separate members, but the present invention is not limited thereto, and these members may be the same member.

  The voltage-controlled switching element for charging is not limited to a MOS field effect transistor. For example, any field effect transistor such as a MIS field effect transistor may be used.

  The power switching element is not limited to an IGBT, and may be a power MOS field effect transistor, for example.

  -The power conversion circuit composed of power switching elements is not limited to the inverter IV. For example, if a booster circuit is provided between the in-vehicle inverter IV and the high-voltage battery 12, this booster circuit may be used. Further, it may be a step-down converter that steps down the voltage of the high voltage battery 12 and supplies it to the low voltage battery 16. Even in these cases, if the power switching element and the freewheel diode are connected in series, from the viewpoint of facilitating the design to suppress the surge caused by the recovery current of the freewheel diode, the charging switching means Since it is desirable to use a current control type switching element, application of the present invention is effective.

1 is a system configuration diagram according to a first embodiment. FIG. The figure for demonstrating the production | generation of the surge resulting from a recovery current. The circuit diagram which shows the circuit structure of the drive circuit concerning the said embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning 2nd Embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning 3rd Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning 4th Embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning 5th Embodiment. The time chart which shows the off operation mode of the power switching element concerning the embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning 6th Embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning 7th Embodiment. The time chart which shows the OFF operation aspect of the power switching element concerning 8th Embodiment.

Explanation of symbols

  32 ... Charging bipolar transistor, 36 ... Discharging bipolar transistor, 40 ... Charging MOS transistor, 44 ... Delay circuit, 50 ... Discharging MOS transistor, Sw ... Power switching element, FD ... Free wheel diode.

Claims (9)

In a drive circuit for driving a voltage-controlled power switching element,
As a charging opening / closing means for electrically opening and closing between a power supply for charging positive conduction to the conduction control terminal of the power switching element and the conduction control terminal, a current control type switching element and a voltage control type A drive circuit for a power switching element, comprising: a switching element.   2. The power switching element drive circuit according to claim 1, wherein the current control type switching element is an NPN bipolar transistor.   3. The power according to claim 2, further comprising a mitigation unit for mitigating a rate of increase in output voltage of the NPN bipolar transistor within a predetermined period of time from the start of charging of the charge to the conduction control terminal. Switching element drive circuit.   4. The relaxation means includes a delay circuit that delays a change in an operation signal of the power switching element, and applies the output voltage of the delay circuit to a base of the NPN bipolar transistor. The drive circuit of the power switching element of description.   The process of closing the charging opening / closing means to charge a positive charge to the conduction control terminal of the power switching element is performed by turning on the current control type switching element and then controlling the conduction of the power switching element. 5. The driving of a power switching element according to claim 1, wherein the voltage-controlled switching element is turned on after a timing at which a terminal voltage becomes equal to or higher than a threshold voltage. 6. circuit.   As a discharge opening / closing means for electrically opening and closing between the conduction control terminal and the downstream side of the discharge path of the positive charge in order to discharge the positive charge from the conduction control terminal of the power switching element, a PNP type 6. The power switching element drive circuit according to claim 2, further comprising a bipolar transistor.   7. The drive circuit for a power switching element according to claim 6, further comprising a voltage-controlled switching element as the discharge opening / closing means.   The process of closing the discharge switching means to discharge positive charges from the conduction control terminal of the power switching element is performed by turning on the current control type switching element and then controlling the conduction of the power switching element. 8. The drive circuit for a power switching element according to claim 7, wherein the voltage controlled switching element is turned on after the timing when the terminal voltage becomes equal to or lower than the threshold voltage.   The power switching element drive circuit according to any one of claims 1 to 8, wherein a diode is connected in series to the power switching element.

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