JP2017063365A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power loss by accelerating turn-on operation of a normally-off main switching element in a gate drive circuit.SOLUTION: A parallel circuit 40 has a capacitor C40 for applying a reverse bias voltage to a main switching element Q100, and a switch element Q40 for disconnection connected in series with this capacitor. A switch element Q50 for reverse bias elimination is connected with the gate of the main switching element Q100. A delay circuit 20 outputs an effective pulse, obtained by delaying a drive pulse, to the parallel circuit. A reverse bias reset circuit 30 generates a reset pulse a5 from the drive pulse and effective pulse, and immediately before the main switching element Q100 is turned on, turns the switch element for disconnection off and turns the switch element for reverse bias elimination on.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a gate drive circuit having a normally-off type switching element that is advantageous for lowering a gate-on voltage as a main switch.

  A normally-off type power transistor has excellent characteristics in ensuring the safety of equipment because no current flows in a state where no gate voltage is applied. Recently, GaN (gallium nitride) has attracted attention as a normally-off transistor. GaN is also called a wide-gap semiconductor because of its wide band gap, and has high dielectric breakdown strength, and is a power device that is excellent for small and high-frequency applications such as switching power supplies and power converters.

  A normally-off transistor made of GaN or the like is considered to be a promising power device in the future because of its good high-frequency characteristics and low on-resistance characteristics. On the other hand, normally-off type devices have a small threshold voltage, a large leakage current even when the gate voltage is 0 [V], and there is a problem that power is wasted. As a countermeasure, a technique has been proposed in which a reverse bias voltage is applied at the time of OFF to reduce the leakage current. One example will be described below as a conventional example.

  FIG. 4 shows a conventional gate drive circuit in which a switching element is reverse-biased when the switch is turned off in order to speed up the turn-off operation (see Patent Document 1).

  As shown in FIG. 4, a capacitor C1 for applying a reverse bias voltage to the switching element Q1 and a resistance element R3 for limiting the current flowing through the gate are connected between the node A ′ and the gate of the switching element Q1. In addition, a series circuit 32 of the resistor element R1 and the diode D1 is connected between the connection node N1 of the capacitor C1 and the resistor element R3 and the ground line GL. The anode of the diode D1 is connected to the resistance element R1, and the cathode is connected to the ground line GL. The series circuit 32 of the resistor element R1 and the diode D1 has a function of generating a DC voltage between both ends of the reverse bias voltage applying capacitor C1 by causing a current to flow therethrough. A series circuit of a Zener diode ZD1 and a resistance element R2 is connected between both ends of the capacitor C1 to constitute a parallel circuit 33. The anode of the Zener diode ZD1 and one end of the resistor element R2 are connected, the cathode of the Zener diode ZD1 is connected to the node A ′, and the other end of the resistor element R2 is connected to the connection node N1 between the resistor element R1 and the resistor element R3. Yes. The series circuit of the Zener diode ZD1 and the resistance element R2 has a function of controlling a DC voltage value (reverse bias voltage) generated across the capacitor C1 for applying a reverse bias voltage to be constant. Since the resistance element R2 suppresses the peak of the current flowing through the Zener diode ZD1, it is possible to employ a Zener diode ZD1 having a small power capacity.

FIG. 5 is a timing chart (estimation) showing an example of the operation of the gate drive circuit 31 shown in FIG. At timing t _11, when the ON signal (the rising of the drive pulse a ₁₁₎ is input to the input stage, a current flows to the gate of the switching element Q1 through the capacitor C1 and the resistor R3, the switching element Q1 is turned on Since the direct current I flows through the series circuit 32 including the resistor element R1 and the diode D1 and a potential difference is generated between the connection node N1 and the node A ′, a direct current voltage is generated in the capacitor C1. This DC voltage is −V _ZD1 (positive value) + V _R2 = | V _ZD1 | + V _R2 , where the zener voltage of the zener diode ZD1 in the parallel circuit 33 is V _ZD1 (negative value). Here, V _R2 is a voltage drop of the resistance element R2 due to the direct current I flowing when the switching element Q1 is on. The gate voltage of the switching element Q1 is a voltage (V _DD − | V _ZD1 | −V _R2 ) obtained by subtracting the voltage | V _ZD1 | + V _R2 from the power supply voltage V _DD .

On the other hand, at a timing t _13, when the OFF signal (the trailing edge of the drive pulse a ₁₁₎ is input to the input stage, the positive electrode side and the source of the switching element Q1 of the node A'-B 'between is shorted capacitor C1 The charge stored in the gate of the switching element Q1 is discharged by the opposite charge stored in the capacitor C1. The voltage applied between the gate and source of the switching element Q1 at the turn-off timing is the charging voltage | V _ZD1 | + V _R2 of the capacitor C1. Since the voltage at the positive terminal of the capacitor C1 is 0 [V], the voltage at the negative terminal of the capacitor C1 finally becomes a negative value (− | V _ZD1 | = V _ZD1 ). That is, this is a constant negative bias voltage applied to the gate of the switching element Q1 in the off state.

  In the above, the DC voltage generated in the capacitor C1 when the switching element Q1 is turned on becomes a reverse bias voltage (about −3 [V]) to the gate of the switching element Q1 when the switching element Q1 is turned off. Accordingly, at the time of turn-off, the switching element Q1 is turned off at high speed by the reverse bias voltage. Since the reverse bias is applied to the gate terminal when the switching element Q1 is off, the leakage current can be reduced as compared with the case of applying 0 [V].

Japanese Patent Application Laid-Open No. 8-149497

In the gate drive circuit shown in FIG. 4, a reverse bias voltage (V _ZD1 : negative value) is applied to the gate of the switching element Q1 until just before the turn-on (see timings t ₁₁ and t ₁₅ ). Since a large voltage change (ΔV _B ) from the voltage (reverse bias voltage) to the gate-on voltage is required, there is a problem that the switching speed at the turn-on is lowered, and the power loss is increased correspondingly. Note that as the absolute value of the reverse bias voltage increases, the switching response delay time (on / off switching time) becomes longer. Incidentally, the response delay time when the reverse bias voltage is −4.2 [V] is 27.3 ns, and the response delay time when the reverse bias voltage is −7 [V] is 40.7 ns (an example) ).

  The present invention has been created in view of such circumstances, and relates to a gate drive circuit having a normally-off type switching element as a main switch, and the normally-on type switching element (hereinafter referred to as “main switching element”) is turned on. The purpose is to increase the speed and reduce the power loss.

  The present invention solves the above problems by taking the following measures.

  A gate driving circuit according to the present invention is a gate driving circuit for controlling on / off of a normally-off type main switching element, and is a capacitor for applying a reverse bias voltage to a driving control terminal of the main switching element in an off state. A reverse bias disconnecting switching element connected in series to the capacitor and capable of stopping application of the reverse bias voltage by disconnecting conduction between the capacitor and the main switching element, and the main switching A reverse bias erasing switching element that is interposed between a drive control terminal of the element and a ground line and can short-circuit the drive control terminal of the main switching element and the ground line; Immediately before the element is turned on, the reverse bias disconnection switching element Together with application of the reverse bias voltage is stopped, the drive control terminal and the ground line of the main switching element by the switching element for the reverse bias erasing, characterized in that it is short-circuited.

  According to this configuration, since the reverse bias voltage is applied to the drive control terminal while the main switching element is in the OFF state, the leakage current can be reduced. Moreover, since the reverse bias voltage is applied by the capacitor, the voltage can be stably applied. On the other hand, the application of the reverse bias voltage is stopped by the switching element for reverse bias separation immediately before the main switching element is turned on, and the drive control terminal and the ground line of the main switching element are connected by the switching element for reverse bias erasing. Since it is short-circuited, application of the reverse bias voltage can be stopped immediately before the main switching element is turned on. For this reason, the turn-on operation can be speeded up and the switching loss at the time of turn-on can be reduced.

  Here, in addition to the control unit that outputs a drive pulse in which an active level and an inactive level are alternately repeated, and the capacitor and the switching element for separating the reverse bias, the switching element for separating the capacitor and the reverse bias A constant voltage element connected in parallel to the series circuit to control the magnitude of the reverse bias voltage and supply a predetermined drive current to the drive control terminal of the main switching element, and the output terminal A drive pulse transmission parallel circuit that is conductively connected to the drive control terminal of the main switching element, and the drive pulse output from the control unit with respect to the input terminal of the drive pulse transmission parallel circuit is transmitted for a certain short time. A delay circuit for generating and outputting a delayed effective pulse; the drive pulse from the control unit; and the delay circuit. In order to turn off the reverse bias disconnecting switching element and turn on the reverse bias erasing switching element in the transition period from the OFF state to the ON state of the main switching element. And a reverse bias reset circuit for generating a reverse bias reset pulse.

  In the above configuration, the reverse bias reset pulse generated by the reverse bias reset circuit becomes active at the start timing of the transition period from the OFF state to the ON state of the main switching element, and becomes inactive at the short-term end timing. Needless to say.

  In the gate drive circuit of the present invention having the above configuration, the voltage of the drive control terminal of the main switching element to which the reverse bias voltage is applied in the off state is changed from the gate off voltage level (reverse bias voltage) to the gate on voltage level. At this time, instead of making a transition from the reverse bias voltage to the gate-on voltage all at once, the following control is performed. That is, for reverse bias voltage application over a short period of time (delay time by delay circuit) by turning off the reverse bias disconnection switching element based on the application of the reverse bias reset pulse and turning on the reverse bias erasing switching element. And the application of the reverse bias voltage to the drive control terminal of the main switching element is stopped, and the drive control terminal is short-circuited to the ground line. The negative charge of the drive control terminal related to the reverse bias voltage due to the short circuit is discharged to the ground level, and the application of the reverse bias voltage from the cathode terminal of the capacitor is stopped, and the drive control terminal voltage is once set to the reverse bias voltage and the gate on voltage. Shift to 0 level in between.

  When the reverse bias reset pulse becomes inactive and the effective pulse (the drive pulse output from the control unit is delayed for a certain short time by the delay circuit) becomes active, the reverse bias disconnecting switching element is turned on, The reverse bias erase switching element is turned off. That is, the cathode terminal of the capacitor for applying the reverse bias voltage is conductively connected to the drive control terminal of the main switching element, and the short circuit state with respect to the ground line of the drive control terminal is released. As a result, the effective pulse applied to the positive terminal of the reverse bias voltage application capacitor is applied to the drive control terminal of the main switching element via the reverse bias disconnection switching element that is turned on with the capacitor, and the main switching element is turned on. Let At this time, as described above, the drive control terminal voltage is shifted to the 0 level in advance, and the main switching element is turned on by the voltage change from the 0 level to the gate-on voltage, so that the voltage is changed from the reverse bias voltage to the gate-on voltage. Compared to the example, the turn-on speed of the main switching element is increased, and the switching loss at the turn-on is reduced by the increase in speed.

  The gate drive circuit of the present invention having the above configuration has several preferred modes as follows.

  In the above configuration, the switching element for reverse bias separation has a low potential side terminal connected to the capacitor side and a high potential side terminal connected to the drive control terminal side of the main switching element, respectively. The switching element for bias erasing preferably has a low potential side terminal connected to the drive control terminal side of the main switching element and a high potential side terminal connected to the ground line side.

  In the case of a normal mode in which it is not necessary to consider the application of the reverse bias voltage to the drive control terminal in the OFF state of the main switching element, in the switching element for reverse bias separation, the high potential side terminal is connected to the capacitor. The low potential side terminal is connected to the drive control terminal side of the main switching element, and the reverse bias erase switching element has its high potential side terminal connected to the drive control terminal side of the main switching element. The low potential side terminals may be connected to the ground line side.

  However, in the unique technical configuration of the present invention that considers the application of the reverse bias voltage to the drive control terminal of the main switching element, the connection relationship is in the reverse direction to that in the normal mode. This connection mode is useful for operational stability and safety when the reverse bias disconnecting switching element and the reverse bias erasing switching element are formed of semiconductor elements, particularly NMOS transistors and PMOS transistors.

  In the above configuration, there is a preferable aspect in which a unidirectional energization element for driving pulse compensation is connected in parallel to the switching element for reverse bias separation. When an effective pulse is supplied via a capacitor for applying a reverse bias voltage, if the switching element for disconnecting the reverse bias remains off and the turn-on is delayed due to a shift in operation timing, main switching The device turn-on operation is also delayed.

  On the other hand, with this configuration, even when an effective pulse is supplied via the reverse bias voltage application capacitor when the reverse bias disconnection switching element is in the OFF state, the drive pulse compensation is performed. Due to the function of the unidirectional energizing element, the effective pulse can be reliably and immediately sent out to the drive control terminal of the main switching element.

  Further, in the above configuration, there is a preferable aspect in which a backflow prevention element for driving pulse compensation is inserted between the switching element for reverse bias erasing and the ground line. When an effective pulse is applied to the drive control terminal of the main switching element from the drive pulse transmission parallel circuit, the switching element for reverse bias erasure remains on and turns off due to a shift in the operation timing. If the delay is delayed, the drive control terminal becomes the ground level via the reverse bias erasing switching element in the ON state, and the drive control terminal voltage cannot be increased as expected.

  On the other hand, with this configuration, when the reverse bias erasing switching element is in the ON state, an effective pulse is applied from the drive pulse transmission parallel circuit to the drive control terminal of the main switching element. Even in this case, the function of the backflow prevention element for compensating the drive pulse can prevent the drive control terminal from being at the ground level, and the drive control terminal voltage can be increased as expected.

  According to the present invention, since the reverse bias of the drive control terminal is released and reset to 0 level immediately before the turn-on, the turn-on speed of the main switching element is increased and the switching loss at the turn-on is reduced. Can be realized.

The circuit diagram which shows the structure of the gate drive circuit in the Example of this invention The circuit diagram which shows the detailed structure of the delay circuit and short pulse generation circuit in the gate drive circuit in the Example of this invention Timing chart showing the operation of the gate drive circuit in the embodiment of the present invention Circuit diagram showing configuration of conventional gate drive circuit Timing chart (example) showing an example of the operation of the gate drive circuit in the conventional example

  Hereinafter, the embodiment of the gate drive circuit of the present invention having the above configuration will be described in detail at the level of specific examples.

  FIG. 1 is a circuit diagram showing a configuration of a gate driving circuit in an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a detailed configuration of a delay circuit and a short pulse generating circuit in the gate driving circuit. 1 and 2, 10 is a control circuit as a control unit, 20 is a delay circuit, 30 is a reverse bias reset circuit, 40 is a parallel circuit for driving pulse transmission, 40A is a voltage adjustment circuit unit, and 40B is reverse bias control. A constant current circuit section, C40 is a reverse bias voltage applying capacitor constituting the voltage adjustment circuit section 40A, Q40 is a reverse bias disconnecting switching element constituting the voltage adjustment circuit section 40A, and Q50 is a reverse bias erasing switching element. , D50 is a backflow prevention element for driving pulse compensation, and Q100 is a normally-off type switching element (main switching element).

  The drive pulse transmission parallel circuit 40 is configured as a parallel circuit of a voltage adjustment circuit unit 40A and a reverse bias control / constant current circuit unit 40B. The voltage adjustment circuit unit 40A includes a reverse bias voltage applying capacitor C40, a reverse bias disconnecting switching element Q40, and a unidirectional energization element D40 for driving pulse compensation. Here, the switching element Q40 for reverse bias separation and the unidirectional energization element D40 for driving pulse compensation are connected in parallel to each other. A capacitor C40 for applying a reverse bias voltage is connected in series to the parallel circuit. The reverse bias isolation switching element Q40 is composed of an N-channel MOS transistor, and the unidirectional energization element D40 is composed of a diode. The source of the NMOS transistor and the anode of the diode are connected to each other. The voltage application capacitor C40 is also connected to the negative terminal. The drain of the NMOS transistor Q40 is connected to the cathode of the diode D40. The reverse bias voltage application capacitor C40 has a function of reducing the gate voltage V100 as a drive control terminal when the main switching element Q100 is turned on and applying a reverse bias voltage to the gate (drive control terminal) when the main switching element Q100 is turned off. ing.

  The unidirectional energization element D40 for driving pulse compensation is connected in parallel to the switching element Q40 for disconnecting the reverse bias via the capacitor C40 for applying a reverse bias voltage when the switching element Q40 is in the OFF state. This is to ensure that the pulse is immediately sent to the gate of the main switching element Q100 when the pulse is supplied.

  The reverse bias control / constant current circuit unit 40B includes a constant voltage element ZD40 and a resistance element R40. The constant voltage element ZD40 is composed of a Zener diode, and its anode is connected to one terminal of the resistance element R40, and its cathode is connected to the positive terminal of the capacitor C40 for applying a reverse bias voltage and the output terminal of the delay circuit 20. (Connection node N1). The other terminal of the resistance element R40 is connected to a connection point between the drain of the switching element Q40 for reverse bias disconnection and the cathode of the unidirectional conducting element D40 for driving pulse compensation (connection node N2). The reverse bias control / constant current circuit unit 40B connected in parallel to the voltage adjustment circuit unit 40A controls the magnitude of the reverse bias voltage of the voltage adjustment circuit unit 40A when the main switching element Q100 is turned off, and performs main switching. A predetermined drive current is supplied to the gate when the element Q100 is turned on.

  The reverse bias reset circuit 30 includes a short pulse generation circuit 30A and an inverter circuit 30B. The inverter circuit 30B is inserted between the output terminal of the short pulse generation circuit 30A and the gate (drive control terminal) of the switching element Q50 for reverse bias erasing. The reverse bias reset circuit 30 receives the drive pulse a3 from the control circuit 10 and the effective pulse a4 from the delay circuit 20, and generates a reverse bias reset pulse a5 that indicates a period from the start timing to the end timing of a minute fixed time. . When the reverse bias reset pulse a5 becomes active ("L" level), the reverse bias disconnecting switching element Q40 is turned off. At the same time, a reverse bias reset pulse a6 whose logic is inverted by the inverter circuit 30B is generated to reverse bias erase. The switching element Q50 is turned on. When the reverse bias reset pulse a5 becomes inactive ("H" level), the reverse bias disconnection switching element Q40 is turned on. At the same time, the reverse bias erase switching element Q50 is reversed by the reverse bias reset pulse a6 whose logic is inverted. To turn off.

  The control circuit 10 is composed of a control IC using a smoothing capacitor C11 held at a constant voltage by a DC power supply voltage Vcc as a drive power supply, and outputs a drive pulse a1 in which an active level and an inactive level are alternately repeated. It is configured. The drive pulse a1 output from the control circuit 10 is output to the delay circuit 20 as the drive pulse a2 via the resistance element R11, while the drive pulse a1 is output to the short pulse generation circuit 30A as the drive pulse a3 via the resistance element R12. It is comprised so that.

  The delay circuit 20 and the short pulse generation circuit 30A are driven by the DC power supply voltage Vcc, that is, the output voltage of the smoothing capacitor C11. The delay circuit 20 outputs an effective pulse a4 obtained by delaying the input drive pulse a2 by a predetermined minute constant delay time τ1, and the effective pulse a4 is output to the short pulse generation circuit 30A, while the connection node N1. Are output to the input terminal of the drive pulse transmission parallel circuit 40, that is, the positive terminal of the capacitor C40 for applying a reverse bias voltage and the cathode of the constant voltage element ZD40.

  The output terminal of the drive pulse transmission parallel circuit 40 is connected to the gate (drive control terminal) of the main switching element Q100 via the resistor element R13. A connection node N3 between the resistance element R13 and the gate of the switching element Q100 is connected to the ground line GL via a resistance element R14 for preventing malfunction, and the switching element Q50 for reverse bias erasing and driving pulse compensation. The backflow prevention element D50 is connected to the ground line GL through a series circuit. The backflow prevention element D50 for driving pulse compensation is composed of a diode, its anode is connected to the ground line GL, its cathode is connected to the drain of the switching element Q50 for reverse bias erasing, and the source of this switching element Q50 Is connected to a connection node N3 between the resistance element R13 and the gate of the switching element Q100.

  The reverse current prevention element D50 for driving pulse compensation is a case where a pulse is applied from the driving pulse transmission parallel circuit 40 to the gate of the main switching element Q100 while the reverse bias erasing switching element Q50 is on. In addition, the gate voltage of the main switching element Q100 can be increased as expected.

  As described above, the gate drive circuit according to the embodiment of the present invention that performs on / off control using the main switching element Q100 as the main switch is configured.

  Next, details of the delay circuit 20 and the short pulse generation circuit 30A will be described with reference to FIG.

  As shown in FIG. 2A, the delay circuit 20 includes a smoothing capacitor C21, PMOS transistors Q21 and Q23, and NMOS transistors Q22 and Q24. A smoothing capacitor C21 is connected between the input terminal of the DC power supply voltage Vcc and the ground GND. A series circuit of a PMOS transistor Q21 and an NMOS transistor Q22 and a series circuit of a PMOS transistor Q23 and an NMOS transistor Q24 are connected in parallel to the smoothing capacitor C21. Each of the series circuits of these PMOS and NMOS constitutes an inverter circuit, and a buffer circuit is constituted by two stages of inverter circuits. That is, the drains of the transistors Q21 and Q22 are connected to each other, and the connection node is connected to the gates of the transistors Q23 and Q24. The drains of the transistors Q23 and Q24 are connected to each other, and the connection point serves as an output terminal for the effective pulse a4.

  In the delay circuit 20, the delay time τ1 of the effective pulse a4 with respect to the drive pulse a2 is determined with the time constant of the buffer circuit. The drive pulse a2 having a repetition pattern of “H” and “L” input to the delay circuit 20 becomes an effective pulse a4 having a repetition pattern of “H” and “L” while being delayed by the delay time τ1, and is driven. The signal is output toward the input terminal (connection node N1) of the pulse transmission parallel circuit 40 and the input terminal of the short pulse generation circuit 30A.

  As shown in FIG. 2B, the short pulse generation circuit 30A includes a smoothing capacitor C31, a resistance element R31, and an NMOS transistor Q31. A smoothing capacitor C31 is connected between the input terminal of the DC power supply voltage Vcc and the ground GND. A series circuit of a resistance element R31 and an NMOS transistor Q31 is connected between the positive terminal of the smoothing capacitor C31 and the output terminal of the delay circuit 20 (the drain of the NMOS transistor Q24). A drive pulse a3 is applied to the gate of the transistor Q31, and an effective pulse a4 is applied to the source. A connection node between the resistor element R31 and the drain of the transistor Q31 is an output terminal for the reverse bias reset pulse a5.

  In this short pulse generating circuit 30A, when the combination of the drive pulse a3 and the effective pulse a4 is [“L”, “L”], [“L”, “H”], [“H”, “H”] Generates an “H” level as the reverse bias reset pulse a5, and generates an “L” level as the reverse bias reset pulse a5 when the combination of the driving pulse a3 and the effective pulse a4 is [“H”, “L”]. .

  That is, since the transistor Q31 is turned off when the drive pulse a3 is at “L” level, the reverse bias reset pulse a5 is at “H” level regardless of the “H” and “L” of the effective pulse a4. On the other hand, when the drive pulse a3 is at the “H” level, the transistor Q31 is turned on, so that the level of the reverse bias reset pulse a5 changes according to the level of the effective pulse a4. That is, if the effective pulse a4 is at “H” level, the reverse bias reset pulse a5 is also at “H” level, and if the effective pulse a4 is at “L” level, the reverse bias reset pulse a5 is at “L” level.

When the drive pulse a2 becomes "L" level, the NMOS transistor Q22 is turned off, the PMOS transistor Q21 is turned on and the DC power supply voltage Vcc is applied, so that the "H" level is output from the common drain connection point. As a result, the PMOS transistor Q23 is turned off and the NMOS transistor Q24 is turned on and connected to the ground line GL, so that the effective pulse a4 output from the delay circuit 20 becomes the “L” level. When the effective pulse a4 is at the “L” level and the drive pulse a3 is at the “H” level, the NMOS transistor Q31 is in the on state, and therefore the “L” level is output from the short pulse generating circuit 30A. (period t ₂ ~t _3), conversely, the long drive pulses a3 is at the "L" level the NMOS transistor Q31 is in the oFF state, from the short pulse generation circuit 30A "H" level is output (time t ₅ ~t _6).

On the other hand, when the driving pulse a2 becomes “H” level, the PMOS transistor Q21 is turned off and the NMOS transistor Q22 is turned on and connected to the ground line GL, so that the “L” level is output from the common drain connection point. . As a result, the NMOS transistor Q24 is turned off, the PMOS transistor Q23 is turned on, and the DC power supply voltage Vcc is applied. Therefore, the effective pulse a4 output from the delay circuit 20 becomes the “H” level. In a state where the effective pulse a4 is at the “H” level, the “H” level is output from the short pulse generation circuit 30A regardless of the “H” level and “L” level of the drive pulse a3 (period t ₃ ~t _5).

  In summary, the reverse bias reset pulse a5 becomes “L” level only when the combination of the drive pulse a3 and the effective pulse a4 is [“H”, “L”]. The reverse bias reset pulse a5 is a low active (negative logic) pulse having a sufficiently short time width corresponding to the delay time τ1.

  Here, by making it low active (reverse bias reset pulse a5 becomes “L” level), switching element Q40 for reverse bias disconnection is made active (off), and capacitor C40 for reverse bias voltage application is disconnected (reverse) In synchronization with this, a high-active reverse bias reset pulse a6 obtained by inverting the reverse bias reset pulse a5 via the inverter circuit 30B activates the switching element Q50 for reverse bias erasing ( ON) to short-circuit between the gate and source of the main switching element Q100 (reverse bias short-circuit).

  Next, the operation of the gate drive circuit configured as described above will be described with reference to the timing chart of FIG.

The drive pulse a1 output from the control circuit 10 has a repeating pattern of “L” and “H” that falls at timing t ₀ , rises at timing t ₂ , and falls again at timing t ₄ .

  The pattern and timing of the driving pulse a2 through which the driving pulse a1 has passed through the resistance element R11 and the driving pulse a3 through which the driving pulse a1 has passed through the resistance element R12 are synchronized with the driving pulse a1 in the same phase.

Drive pulse a2 delay circuit 20 and processed results of an effective pulse a4 is falls at the timing t _1, the rising timing t _3, "L" that fall again at the timing t _5, the repetitive pattern of "H" Have. The pattern of the effective pulse a4 is the same as that of the driving pulses a1, a2, and a3, and the timing of the effective pulse a4 is delayed by a predetermined delay time τ1 from the timing of the driving pulses a1, a2, and a3.

Drive pulse a3 and effective pulse a4 and reverse bias reset pulse a5 generated by the short pulse generation circuit 30A based on the falls at the timing t _2, rising at the timing t _3, "that again falls at the timing t ₆ L "," H "repeated pattern. The reverse bias reset pulse a5 is a low active signal having a time width of the delay time τ1. Reverse bias reset pulse a5 is falling timing t ₂ becomes active precedes by a predetermined time corresponding to the delay time τ1 with respect to the rising timing t ₃ of the effective pulse a4. Then, the reverse bias reset pulse a5 is rising timing t ₃ when the inactive are consistent with the rising timing t ₃ of the effective pulse a4. That is, the reverse bias reset pulse a5 is activated (activated) immediately before the timing at which the effective pulse a4 is activated (activated), and this period is a short time corresponding to the delay time τ1. is there. Reverse bias reset pulse a5 low active, it controls the switching element Q40 for reverse bias disconnecting the off state in the period of the timing t ₂ ~t _3.

Low reverse bias reset pulse a5 is logically inverted by the high reverse bias reset pulse a6 active by the inverter circuit 30B of the active rises at the timing t _2, falls at the timing t _3, that again rises at the timing t ₆ "H" , “L” repeating pattern. Reverse bias reset pulse a6 This high active, it controls the switching element Q50 for reverse bias erased in the ON state in the period of the timing t ₂ ~t _3.

That is, a low active reverse bias at timing t ₂ preceding the timing t ₃ by applying the effective pulse a 4 to the gate of the main switching element Q 100 via the driving pulse transmission parallel circuit 40 by a delay time τ 1. The reverse bias disconnection switching element Q40 is turned off by the reset pulse a5, and at the same time, the reverse bias erase switching element Q50 is turned on by the high active reverse bias reset pulse a6.

When the effective pulse a4 output from the delay circuit 20 falls at the timing t ₁ , the positive terminal of the reverse bias voltage application capacitor C40 is connected to the ground line GL via the NMOS transistor Q24 turned on in the delay circuit 20, Since the charge at the positive terminal of the reverse bias voltage application capacitor C40 is discharged, the reverse bias disconnection switching element Q40 and the resistance element R13 are turned on with respect to the negative terminal of the reverse bias voltage application capacitor C40. The voltage between the gate and the source of the connected main switching element Q100 is rapidly reduced. At this time, the gate-source voltage Vr is a negative value and is in a reverse bias state. In the OFF state of the main switching element Q100, the gate-source voltage is stabilized by the breakdown voltage (Zener voltage) V _ZD40 (negative value) of the constant voltage element ZD40 in the reverse bias control / constant current circuit unit 40B. That is, the reverse bias voltage Vr (= V _ZD40 (negative value)) is applied to the gate of the main switching element Q100. As a result, the leakage current in the OFF state of main switching element Q100 is suppressed to a small level.

At timing t _2, a reverse bias reset pulse a6 high active output from the short pulse generation circuit 30A a5 and the reverse bias reset pulse low active output from the inverter circuit 30B are both activated. As a result, the switching element Q40 for separating the reverse bias in the voltage adjustment circuit unit 40A is turned off, while the switching element Q50 for erasing the reverse bias is turned on.

  When the reverse bias disconnection switching element Q40 is turned off, supply of the reverse bias voltage to the gate of the main switching element Q100 by the reverse bias voltage application capacitor C40 is stopped. On the other hand, when the reverse bias erasing switching element Q50 is turned on, the negative charge related to the reverse bias between the gate and the source of the main switching element Q100 is rapidly discharged through the backflow prevention element D50 for driving pulse compensation and the switching element Q50. Then, the gate voltage of the main switching element Q100 is converged to 0 level. Thus, in raising the gate voltage of the main switching element Q100, it is once raised from the gate-off voltage (reverse bias voltage) to the 0 level.

At timing t ₃ , the effective pulse a 4 rises, and at the same time, the low active reverse bias reset pulse a 5 rises, the reverse bias disconnection switching element Q 40 is turned on, and the high active reverse bias reset pulse a 6 falls. Switching element Q50 for reverse bias erasing is turned off. The “H” level pulse that is the effective pulse a4 that has passed through the capacitor C40 for applying the reverse bias voltage is applied to the gate of the main switching element Q100 via the turned-on unidirectional conducting element D40 for compensating the driving pulse and the resistance element R13. To turn on the main switching element Q100. The voltage change accompanying the increase from the 0 level to the gate-on voltage is ΔVA, and this voltage change ΔVA is sufficiently smaller than the voltage change ΔV _{B in the} conventional example (see FIG. 5).

  If the unidirectional energization element D40 for driving pulse compensation is not connected in parallel to the switching element Q40 for disconnecting the reverse bias, the effective pulse a4 is supplied via the capacitor C40 for applying the reverse bias voltage. If the switching element Q40 for disconnecting the reverse bias remains in the off state due to a shift in the operation timing and the turn-on is delayed, the turn-on operation of the main switching element Q100 is also delayed. On the other hand, when the unidirectional energization element D40 is connected in parallel to the switching element Q40, even if the effective pulse a4 is supplied when the switching element Q40 for reverse bias disconnection is in the OFF state, one The effective pulse a4 can be immediately sent to the gate of the main switching element Q100 by the function of the directional energization element D40, so that the main switching element Q100 can be turned on rapidly.

  In addition, if the reverse bias erasing switching element Q50 is not connected to the reverse bias erasing switching element D50, the reverse bias erasing is performed when the effective pulse a4 is applied to the gate of the main switching element Q100. When the switching element Q50 is turned on due to a shift in the operation timing and the turn-off is delayed, the gate becomes the ground level via the switching element Q50 for reverse bias erasing in the on state, and the gate voltage is reduced. You will not be able to ascend as expected. On the other hand, when the backflow prevention element D50 for compensating the driving pulse is inserted between the ground line GL and the switching element Q50 for reverse bias erasing, the switching element Q50 for reverse bias erasing is in the ON state. Sometimes even when the effective pulse a4 is applied to the gate of the main switching element Q100, the function of the backflow prevention element D50 for compensating the drive pulse prevents the gate from being at the ground level and raises the gate voltage as expected. It becomes possible to make it.

Anyway, already in the period of the timing t ₂ ~t ₃ immediately before the timing t ₃ when the gate-on voltage is applied to the capacitor C40 for applying a reverse bias voltage, the gate voltage of the main switching element Q100 is forcibly reverse bias The voltage Vr (= V _ZD40 (negative value)) is raised to 0 level. That is, the gate of the main switching element Q100 is released from the reverse bias state and is in the normal 0 level state. As a result, the time required for turning on the main switching element Q100 can be significantly reduced as compared with the case where the main switching element Q100 is turned on from the reverse bias state. As described above, according to the present invention, the turn-on speed of the main switching element Q100 can be increased. Then, the switching loss when the main switching element Q100 is turned on is reduced accordingly.

  Next, the connection between the source and drain of the switching element Q40 for separating reverse bias and the switching element Q50 for erasing reverse bias, which are NMOS transistors, will be described. In the case of an NMOS transistor, in principle, the source is connected to a terminal on the lower potential side than the drain, and the drain is connected to the terminal on the higher potential side than the source. In FIG. 1, the source of the switching element Q40 for disconnecting the reverse bias is on the side of the capacitor C40 for applying a reverse bias voltage, and the drain is on the side of the resistor element R13 (connection node N2). The source of the reverse bias erasing switching element Q50 is on the side of the gate (connection node N3) of the main switching element Q100, and the drain is on the side of the backflow prevention element D50 for driving pulse compensation that is connected to the ground line GL. This aspect appears to be the opposite of the above principle.

  However, this is not the case, and it follows the above principle (in the case of an NMOS transistor, the source is connected to a terminal on the lower potential side than the drain, and the drain is connected to the terminal on the higher potential side than the source). This is because a reverse bias is applied to the gate of the main switching element Q100 instead of a positive bias.

In the OFF state of the main switching element Q100, the potential V _{C at} the connection point between the reverse bias disconnection switching element Q40 and the reverse bias voltage application capacitor C40 is lower than the gate voltage V _G of the main switching element Q100 ( V _C <V _G ). Therefore, the source of the reverse bias disconnection switching element Q40, which is an NMOS transistor, is connected to the reverse bias voltage application capacitor C40, which is on the lower potential side.

The switching element Q40 for separating the reverse bias and the switching element Q50 for erasing the reverse bias effectively operate as transistors during the period from the timing t _{1 to} t ₂ in the time chart of FIG. The potential V _{C at} the connection point between the switching element Q40 for disconnection and the capacitor C40 for applying the reverse bias voltage is lower than the gate voltage V _G of the main switching element Q100, and the potential difference is 0.05 to 0.2 [V]. The degree is preferable, more preferably about 0.1 [V].

On the other hand, in the on-state of the main switching element Q100, the gate voltage V _G is the potential of the connection point of the gate of the switching element Q50 and the main switching element Q100 for reverse bias erasing is lower than the potential V _GL of the ground line GL (V _G <V _GL ). Therefore, the source of the reverse bias erasing switching element Q50, which is an NMOS transistor, is connected to the gate side of the main switching element Q100 on the lower potential side.

  Since the capacitor C40 for applying the reverse bias voltage hardly undergoes charging / discharging through the switching operation, a constant current supply type driving circuit with small driving loss can be realized.

In the period from the timing t ₃ when the effective pulse a4 rises until time t ₅ falls, the main switching element Q100 is in an ON state. In this state, the voltage applied between the output terminal (connection node N1) of the delay circuit 20 and the low side terminal (source) of the main switching element Q100 is the gate input capacitance C _iss of the main switching element Q100 and the reverse bias voltage. The voltage is divided by the capacitor C40 for application. At this time,
V _G = C ₄₀ · Vcc / (C ₄₀ + C _iss ) = Vcc / (1 + C _iss / C ₄₀ ) <Vcc
And the gate voltage V _G is smaller than the drive voltage Vcc.

The initial gate voltage V _G is given by the above equation. In the case of a normally-off type GaN transistor, a gate current flows, the gate voltage V _G is clamped by the gate current, and the gate voltage V _G does not increase beyond a certain value. . Therefore, the C _40> C _iss even V _C40> V _G.

  Immediately after the main switching element Q100 is turned on, the current driving of the main switching element Q100 is maintained by the current flowing through the series circuit of the constant voltage element (Zener diode) ZD40 and the resistance element R40 of the reverse bias control / constant current circuit unit 40B. Thus, the ON state of the main switching element Q100 is maintained. At this time, the current flowing into the gate of the main switching element Q100 is maintained at a constant current, and the drain-source current of the main switching element Q100 is stabilized.

  Further, in the steady-on state of the main switching element Q100, the DC power supply voltage generated in the reverse bias voltage application capacitor C40 is limited by the breakdown voltage (zener voltage) of the constant voltage element (zener diode) ZD40. Part of the current flows through the resistance element R14 for preventing malfunction.

  INDUSTRIAL APPLICABILITY The present invention is useful as a technique for realizing an increase in turn-on speed of a normally-off type switching element and a reduction in switching loss at the time of turn-on, with respect to a gate drive circuit having a normally-off type switching element as a main switch.

10 Control circuit (control unit)
DESCRIPTION OF SYMBOLS 20 Delay circuit 30 Reverse bias reset circuit 30A Short pulse generation circuit 30B Inverter circuit 40 Drive pulse transmission parallel circuit 40A Voltage adjustment circuit part 40B Reverse bias control and constant current circuit part a1, a2, a3 Drive pulse a4 Effective pulse a5, a6 Reverse bias reset pulse C40 Capacitor for applying reverse bias voltage D40 One-way energizing element for driving pulse compensation D50 Backflow prevention element for driving pulse compensation GL Ground line Q40 Switching element for reverse bias disconnection Q50 Switching for reverse bias elimination Element Q100 Main switching element ZD40 Constant voltage element

Claims (5)

A gate driving circuit for controlling on / off of a normally-off type main switching element,
A capacitor for applying a reverse bias voltage to the drive control terminal of the main switching element in the off state;
A switching element for reverse bias disconnection, which is connected in series to the capacitor and capable of stopping application of the reverse bias voltage by disconnecting conduction between the capacitor and the main switching element;
A reverse bias erasing switching element interposed between a drive control terminal of the main switching element and a ground line, and capable of short-circuiting the drive control terminal of the main switching element and the ground line;
Immediately before the main switching element is turned on, application of the reverse bias voltage is stopped by the reverse bias disconnection switching element, and the drive control terminal of the main switching element is connected to the ground by the reverse bias erasing switching element. A gate driving circuit characterized in that a line is short-circuited. A control unit that outputs a drive pulse in which an active level and an inactive level are alternately repeated;
In addition to the capacitor and the reverse bias disconnection switching element, the main switching circuit is connected in parallel to a series circuit of the capacitor and the reverse bias disconnection switching element to control the magnitude of the reverse bias voltage. A parallel circuit for driving pulse transmission having a constant voltage element for supplying a predetermined driving current to the driving control terminal of the element, and an output terminal electrically connected to the driving control terminal of the main switching element;
A delay circuit that generates and outputs an effective pulse obtained by delaying the drive pulse output from the control unit for a predetermined short time with respect to an input terminal of the drive pulse transmission parallel circuit;
With the drive pulse from the control unit and the effective pulse from the delay circuit as inputs, the switching element for reverse bias separation is turned off in the transition period from the off state to the on state of the main switching element. The gate drive circuit according to claim 1, further comprising a reverse bias reset circuit that generates a reverse bias reset pulse for turning on the switching element for reverse bias erasing.   The switching element for reverse bias disconnection has a low potential side terminal connected to the capacitor side and a high potential side terminal connected to the drive control terminal side of the main switching element, respectively. 3. The gate drive according to claim 1, wherein the element has a low potential side terminal connected to the drive control terminal side of the main switching element and a high potential side terminal connected to the ground line side. circuit.   4. The gate drive circuit according to claim 1, wherein a unidirectional energization element for drive pulse compensation is connected in parallel to the switching element for reverse bias separation. 5.   5. The gate drive circuit according to claim 1, wherein a reverse current prevention element for compensating a drive pulse is inserted between the reverse bias erasing switching element and the ground line. 6.

Images