WO2014128942A1 - Device for driving semiconductor element - Google Patents

Device for driving semiconductor element Download PDF

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Publication number
WO2014128942A1
WO2014128942A1 PCT/JP2013/054649 JP2013054649W WO2014128942A1 WO 2014128942 A1 WO2014128942 A1 WO 2014128942A1 JP 2013054649 W JP2013054649 W JP 2013054649W WO 2014128942 A1 WO2014128942 A1 WO 2014128942A1
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terminal
semiconductor element
switch
voltage
gate
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PCT/JP2013/054649
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French (fr)
Japanese (ja)
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坂本　光造
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株式会社 日立製作所
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Priority to JP2015501205A priority Critical patent/JPWO2014128942A1/en
Priority to PCT/JP2013/054649 priority patent/WO2014128942A1/en
Publication of WO2014128942A1 publication Critical patent/WO2014128942A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Definitions

  • the present invention relates to a power semiconductor device such as a junction FET (Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET, and a bipolar transistor, and a drive circuit thereof.
  • a power semiconductor device such as a junction FET (Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET, and a bipolar transistor, and a drive circuit thereof.
  • Patent Document 1 a technique described in Japanese Patent Application Laid-Open No. 2007-336694 (Patent Document 1) is known.
  • the device for driving an insulated gate semiconductor device according to the present technology has a simple configuration while using a single DC power source, and the gate voltage of the insulated gate semiconductor device is applied to a direct current in order to apply a reverse bias voltage at turn-off.
  • a reverse bias voltage that is, a negative gate voltage is applied at the time of OFF.
  • the first object of the present invention is to reduce the power consumed in the main circuit due to a self-turn-on malfunction during switching.
  • the drive circuit that makes the input terminal a negative voltage in this off state The second purpose is to reduce the size and cost.
  • the drive circuit power supply voltage is driven at a voltage lower by the clamp voltage specified by the voltage clamp circuit. For this reason, when the voltage fluctuation of the drive circuit power supply fluctuates, it is added to the fluctuation corresponding to the clamp voltage, and substantially the same fluctuation voltage is applied to the input voltage of the insulated gate semiconductor element. For this reason, in order to set the absolute value of the negative gate drive voltage level high, when trying to increase the clamp voltage, the gate-source voltage (collector-emitter voltage for bipolar transistors, the same applies hereinafter) increases, and the output Current (drain current in bipolar transistors, the same applies hereinafter) tends to vary.
  • the third object of the present invention is to reduce the variation in the output current (drain current and collector current) even if the absolute value of the negative gate drive voltage level is set high in order to prevent the self-turn-on malfunction.
  • the drive current is prevented from becoming excessive.
  • An object of the present invention is to provide a low-cost and small-sized driving device that drives a power semiconductor element such as a junction FET, a power bipolar transistor, a power MOSFET, and an IGBT with high reliability and low loss as described above. To do.
  • a power semiconductor element such as a junction FET, a power bipolar transistor, a power MOSFET, and an IGBT with high reliability and low loss as described above.
  • the semiconductor device driving apparatus turns on the semiconductor element by turning on the first switch connected to the input terminal of the semiconductor element having at least the reference terminal, the input terminal, and the output terminal.
  • the semiconductor element is turned off by applying a reverse polarity voltage to the input terminal with respect to the reference terminal via a capacitor connected to the input terminal of the semiconductor element, and the first switch is turned off when the semiconductor element is turned off.
  • the present invention it is possible to reduce power consumption in the main circuit, reduce the size and cost of the drive circuit, and reduce power consumption in the drive circuit.
  • 1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows 2nd Example of this invention. It is a circuit diagram which shows 3rd Example of this invention. It is a circuit diagram which shows 4th Example of this invention. It is a circuit diagram which shows 5th Example of this invention. It is a circuit diagram which shows 6th Example of this invention. It is a circuit diagram which shows 7th Example of this invention. It is a circuit diagram which shows 8th Example of this invention. It is a circuit diagram which shows 9th Example of this invention.
  • FIG. 1 is a circuit diagram of a semiconductor device driving apparatus according to a first embodiment of the present invention.
  • the power semiconductor element 4 a normally-off SiC junction FET will be described as an example.
  • SiC is silicon carbide and is a kind of semiconductor material that constitutes a semiconductor element. Since SiC has a higher breakdown electric field strength than silicon (Si), it is suitable for a power semiconductor device with high breakdown voltage and low loss.
  • the reference terminal 1 is the source terminal of the normally-off type SiC junction FET 4
  • the input terminal 2 is the gate terminal of the normally-off type SiC junction FET 4
  • the output terminal 3 is the drain terminal of the normally-off type SiC junction FET 4.
  • the source terminal 1 is connected to the ground terminal 25.
  • the drive circuit power supply terminal 8 is set to, for example, 15V with respect to the ground terminal 25.
  • the switch 10 in order to turn on the normally-off junction FET 4, the switch 10 is turned off, the switches 9 and 5 are turned on, and the gate current is supplied to the gate terminal 3 of the normally-off junction FET 4 via the resistor 7.
  • the gate terminal voltage of the SiC junction type FET 4 is set by the voltage of the drive circuit power supply terminal 8 and the value of the resistor 7, but since the gate-source is a PN junction diode, the voltage of the drive circuit power supply terminal 8 is Mainly applied to the resistor 7.
  • the capacitor 6 is charged to a voltage (about 12.5 V) obtained by subtracting the gate terminal voltage (for example, 2.5 V) of the normally-off type SiC junction FET 4 from the voltage (15 V) of the drive circuit power supply terminal 8.
  • the gate current is stopped by turning off the switch 9 and the switch 5, and further, the gate terminal 3 of the normally-off type junction FET 4 is charged to the capacitor 6 by turning on the switch 10.
  • the negative gate voltage is driven by the voltage.
  • the normally-off type SiC junction FET is turned off when the gate-source voltage is zero volts. Therefore, it can be used in a system with higher reliability than a normally-on type SiC junction FET that cannot be turned off unless a negative voltage is applied to the gate-source voltage.
  • the normally-off type SiC junction FET 4 has no internal potential even if the gate terminal 3 and the source terminal 1 are set to zero volts due to the influence of the capacitance between the drain and gate. Since the gate resistance exists, the internal gate voltage that effectively determines the drain current of the normally-off type SiC junction FET 4 increases, and a self-turn-on phenomenon occurs in which the drain current flows.
  • the negative voltage drive can be performed by the single power source drive circuit as described above, it is possible to realize the suppression of useless power consumption by the self-turn-on with a low cost and a small drive circuit.
  • the fluctuation can be mainly absorbed by the voltage applied to the resistor 7. For this reason, the fluctuation
  • the gate terminal voltage can be prevented from being overvoltage, and can be driven with low power consumption under the condition that no excessive gate current flows.
  • the voltage charged in the capacitor 6 can be mainly determined by the voltage of the drive circuit power supply terminal 8 and the gate terminal voltage when the junction FET 4 is on, the negative gate voltage (absolute value) can be increased.
  • FIG. 2 is a circuit diagram of a semiconductor device driving apparatus according to a second embodiment of the present invention. The difference from the first embodiment described with reference to FIG. 1 is that a switch 11 is used instead of the switch 5, and a gate current is supplied from the drive circuit power supply terminal 8 to the gate terminal 3 of the junction FET 4 without going through the switch 9. It is that.
  • the switch 10 in order to turn on the junction type FET 4, the switch 10 is turned off and the switch 11 is turned on to supply the gate current 3 to the gate terminal 3 of the junction type FET 4 through the resistor 7.
  • the gate terminal voltage of the junction FET 4 is set by the voltage of the drive circuit power supply terminal 8 and the value of the resistor 7, but since the gate-source is a diode, the voltage of the drive circuit power supply terminal 8 is mainly a resistance. 7 is applied.
  • the capacitor 6 is charged to a voltage (about 12.5 V) obtained by subtracting the gate terminal voltage (for example, 2.5 V) of the normally-off type SiC junction FET 4 from the voltage (15 V) of the drive circuit power supply terminal 8.
  • the switch 11 is turned off to stop the gate current, and further, the switch 9 is turned off and the switch 10 is turned on to drive the gate terminal 3 of the normally-off junction FET 4 to a negative voltage.
  • FIG. 3 is a circuit diagram of a semiconductor device driving apparatus according to a third embodiment of the present invention.
  • the difference from the second embodiment described with reference to FIG. 2 is that instead of the switch 11, a switch 13 connected between the drive circuit power supply terminal 13 connected to a potential lower than the drive circuit power supply terminal 8 and the resistor 7 is used.
  • the gate current is supplied to the gate terminal 3 of the junction FET 4.
  • the potential of the drive circuit power supply terminal 8 is increased to increase the negative gate voltage (absolute value), and the potential of the drive circuit power supply terminal 13 is decreased to reduce the power consumption of the resistor 7. Can be performed independently.
  • FIG. 4 shows a circuit diagram of a semiconductor device driving apparatus according to a fourth embodiment of the present invention.
  • the gate terminal is connected to the ground terminal 25
  • the source terminal is connected to the terminal between the switch 9 and the switch 10
  • the drain terminal is connected to the junction type FET 4.
  • a p-channel MOSFET 14 connected to the gate terminal 3 side is used.
  • a p-channel MOSFET 14 whose source and body are connected is connected, and a parasitic diode between the drain and body of the p-channel MOSFET 14 is used.
  • FIG. 5 is a circuit diagram of a semiconductor device driving apparatus according to a fifth embodiment of the present invention.
  • a series connection circuit of a resistor 15 and a Si diode 16 is connected between the gate and source of the junction FET 4. Since the threshold voltage of the SiC junction FET is lower than the forward voltage of the Si diode, the resistor 15 can function as a short-circuit resistance for reliably turning off the junction FET.
  • the diode 16 is provided to prevent the capacitor 6 from being discharged through the resistor 15 when a negative gate voltage is applied.
  • the resistor 29 for adjusting the switching speed of the junction FET 4 is provided is shown, but it may not be provided.
  • Other configurations, operations, and effects are the same as those in the fourth embodiment.
  • FIG. 6 is a circuit diagram of a semiconductor device driving apparatus according to a sixth embodiment of the present invention.
  • a resistor 34 is connected between the source terminal and the gate terminal of the MOSFET 14, and a Zener diode which is a voltage clamping element is connected between the ground terminal 25 and the gate terminal of the MOSFET 14. 33 is connected.
  • FIG. 7 is a circuit diagram of a semiconductor device driving apparatus according to a seventh embodiment of the present invention.
  • a drain-body diode of an n-channel MOSFET 17 is used instead of the diode 16 of the fifth embodiment of the present invention shown in FIG.
  • the n-channel MOSFET 17 is turned on, and the gate and the source of the junction FET 4 are short-circuited by the short-circuit resistor 15.
  • the forward voltage drop between the gate and the source of the junction FET 4 is about 2.5V, so the threshold voltage of the n-channel MOSFET 17 is 2.5V or less. It is desirable to make it.
  • the parasitic diode between the drain and the body of the MOSFET 17 is easily forward-biased even when the MOSFET 17 is not sufficiently turned on. Therefore, it is easy to short-circuit between the gate and source of the junction FET 4.
  • FIG. 8 is a circuit diagram of a semiconductor device driving apparatus according to an eighth embodiment of the present invention.
  • p-channel MOSFETs 30 and 31 are used as specific means of the switches 9 and 11 shown in FIG. 2, and an n-channel MOSFET 32 is used as specific means of the switch 10, respectively.
  • MOSFETs provided on the same chip such as a semiconductor integrated circuit (IC) can be used.
  • Other configurations, operations and effects are the same as those of the second embodiment.
  • FIG. 9 shows an inverter circuit according to a ninth embodiment of the present invention.
  • any one of the driving devices described in the first to eighth embodiments is used for the gate driving circuits 20 and 21.
  • the semiconductor elements 18 and 19 are on / off controlled by the driving apparatus described in the first to eighth embodiments. As a result, the power consumption and size of the inverter circuit can be reduced.

Abstract

This device for driving a semiconductor element has: a means for switching on a first switch (5) connected to an input terminal (2) of a semiconductor element (4) having a reference terminal (1), the input terminal (2), and an output terminal (3), and switching on the semiconductor element (4); a means for applying a reverse polarity voltage to the input terminal (2) with respect to the reference terminal (1) via a capacitor (6) connected to the input terminal of the semiconductor element (4), and thereby switching off the semiconductor element (4); and a means for switching off the first switch (5) when the semiconductor element (4) is switched off.

Description

半導体素子の駆動装置Semiconductor device driving apparatus
　本発明は、接合型ＦＥＴ(Field Effect Transistor )，ＩＧＢＴ(Insulated Gate Bipolar Transistor)、パワーＭＯＳＦＥＴ、バイポーラトランジスタなどの電力用半導体装置およびその駆動回路に関する。 The present invention relates to a power semiconductor device such as a junction FET (Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET, and a bipolar transistor, and a drive circuit thereof.
　本技術分野に関連した背景技術として、特開２００７－３３６６９４号公報（特許文献１）に記載の技術が知られている。本技術による絶縁ゲート型半導体素子の駆動装置は、単一の直流電源を使用しながらも簡単な構成で、ターンオフ時の逆バイアス電圧の印加するために、絶縁ゲート型半導体素子のゲート電圧を直流電圧より低く維持するための電圧クランプ回路、ならびに、絶縁ゲート型半導体素子のオン時に充電され、オフ時に逆バイアス電圧を発生するコンデンサを備える。 As a background technique related to this technical field, a technique described in Japanese Patent Application Laid-Open No. 2007-336694 (Patent Document 1) is known. The device for driving an insulated gate semiconductor device according to the present technology has a simple configuration while using a single DC power source, and the gate voltage of the insulated gate semiconductor device is applied to a direct current in order to apply a reverse bias voltage at turn-off. A voltage clamp circuit for maintaining the voltage lower than the voltage, and a capacitor that is charged when the insulated gate semiconductor element is turned on and generates a reverse bias voltage when turned off.
　また、一般に電力用半導体素子では、高速遮断などによりコレクタ電圧あるいはドレイン電圧が急峻に立ち上がったときに、帰還容量結合によるセルフターンオン誤動作を防止してスイッチング時の無駄な消費電力を低減するために、オフ時に逆バイアス電圧すなわち負ゲート電圧を印加する。 In general, in a power semiconductor element, when collector voltage or drain voltage rises sharply due to high-speed cutoff or the like, self-turn-on malfunction due to feedback capacitive coupling is prevented, and wasteful power consumption during switching is reduced. A reverse bias voltage, that is, a negative gate voltage is applied at the time of OFF.
特開２００７－３３６６９４号公報JP 2007-336694 A
　本発明は、スイッチング時にセルフターンオン誤動作により主回路で浪費される消費電力を低減することが第一の目的である。 The first object of the present invention is to reduce the power consumed in the main circuit due to a self-turn-on malfunction during switching.
　セルフターンオン誤動作による誤動作防止の対策方法としては電力用半導体素子をオフする時、入力端子を十分負電圧に保つ方法があるが、本発明では、このオフ状態で入力端子を負電圧にする駆動回路を小型かつ低コスト化することが第二の目的である。 As a countermeasure method for preventing malfunction due to a self-turn-on malfunction, there is a method of keeping the input terminal at a sufficiently negative voltage when the power semiconductor element is turned off. In the present invention, the drive circuit that makes the input terminal a negative voltage in this off state The second purpose is to reduce the size and cost.
　さらに、上記従来の駆動回路では電圧クランプ回路で規定されるクランプ電圧分だけ、駆動回路電源電圧が低い電圧で駆動することになる。このため、駆動回路電源の電圧変動が変動すると、上記クランプ電圧分の変動分に加算され、ほぼ同じ変動電圧が絶縁ゲート型半導体素子の入力電圧に印加される。このため、負ゲート駆動電圧レベルの絶対値を高く設定するため、上記クランプ電圧を高くしようとすると、ゲート・ソース間電圧（バイポーラトランジスタではコレクタ・エミッタ電圧、以下同様）のばらつきが大きくなり、出力電流（バイポーラトランジスタではドレイン電流、以下同様）がばらつきやすくなる。 Furthermore, in the above conventional drive circuit, the drive circuit power supply voltage is driven at a voltage lower by the clamp voltage specified by the voltage clamp circuit. For this reason, when the voltage fluctuation of the drive circuit power supply fluctuates, it is added to the fluctuation corresponding to the clamp voltage, and substantially the same fluctuation voltage is applied to the input voltage of the insulated gate semiconductor element. For this reason, in order to set the absolute value of the negative gate drive voltage level high, when trying to increase the clamp voltage, the gate-source voltage (collector-emitter voltage for bipolar transistors, the same applies hereinafter) increases, and the output Current (drain current in bipolar transistors, the same applies hereinafter) tends to vary.
　特に接合ＦＥＴやバイポーラトランジスタの場合にはゲート電流（バイポーラトランジスタではベース電流、以下同様）のばらつきが大きくなるという問題がある。これに対し、駆動回路電源の変動とクランプ電圧のマージンを考慮し、入力電圧（ベース電圧またはゲート電圧）のバイアス電圧を高めに設計すると、ゲート電流やベース電流が過大に流れて、駆動回路の損失が増大するという問題があった。 Especially, in the case of a junction FET or a bipolar transistor, there is a problem that the variation of the gate current (base current in the case of a bipolar transistor, the same applies hereinafter) becomes large. On the other hand, if the bias voltage of the input voltage (base voltage or gate voltage) is designed to be high considering the fluctuation of the drive circuit power supply and the clamp voltage margin, the gate current and base current will flow excessively, There was a problem that the loss increased.
　そこで、本発明の第三の目的はセルフターンオン誤動作を防止するために負ゲート駆動電圧レベルの絶対値を高く設定しても、出力電流（ドレイン電流やコレクタ電流）のばらつきが小さく、なおかつ、接合ＦＥＴや電力用バイポーラトランジスタの場合には駆動電流が過大となることを防止することにある。 Therefore, the third object of the present invention is to reduce the variation in the output current (drain current and collector current) even if the absolute value of the negative gate drive voltage level is set high in order to prevent the self-turn-on malfunction. In the case of an FET or a power bipolar transistor, the drive current is prevented from becoming excessive.
　本発明は、上記のように、接合ＦＥＴ、電力用バイポーラトランジスタ、パワーＭＯＳＦＥＴ、ＩＧＢＴ等の電力半導体素子を高信頼かつ低損失に駆動する、低コストかつ小型な駆動装置を提供することを目的とする。 An object of the present invention is to provide a low-cost and small-sized driving device that drives a power semiconductor element such as a junction FET, a power bipolar transistor, a power MOSFET, and an IGBT with high reliability and low loss as described above. To do.
　本発明による半導体素子の駆動装置においては、上記課題を解決するために、少なくとも基準端子と入力端子と出力端子を有する半導体素子の入力端子に接続した第１スイッチをオンさせて半導体素子をオンし、半導体素子の入力端子に接続されたコンデンサを介して基準端子に対し入力端子に逆極性電圧を印加することにより半導体素子をオフさせ、半導体素子をオフさせた時に第１スイッチをオフさせる。 In order to solve the above-described problem, the semiconductor device driving apparatus according to the present invention turns on the semiconductor element by turning on the first switch connected to the input terminal of the semiconductor element having at least the reference terminal, the input terminal, and the output terminal. The semiconductor element is turned off by applying a reverse polarity voltage to the input terminal with respect to the reference terminal via a capacitor connected to the input terminal of the semiconductor element, and the first switch is turned off when the semiconductor element is turned off.
　本発明によれば、主回路での低消費電力化、駆動回路の小型・低コスト化、駆動回路での低消費電力化が可能となる。 According to the present invention, it is possible to reduce power consumption in the main circuit, reduce the size and cost of the drive circuit, and reduce power consumption in the drive circuit.
本発明の第１実施例を示す回路図である。1 is a circuit diagram showing a first embodiment of the present invention. 本発明の第２実施例を示す回路図である。It is a circuit diagram which shows 2nd Example of this invention. 本発明の第３実施例を示す回路図である。It is a circuit diagram which shows 3rd Example of this invention. 本発明の第４実施例を示す回路図である。It is a circuit diagram which shows 4th Example of this invention. 本発明の第５実施例を示す回路図である。It is a circuit diagram which shows 5th Example of this invention. 本発明の第６実施例を示す回路図である。It is a circuit diagram which shows 6th Example of this invention. 本発明の第７実施例を示す回路図である。It is a circuit diagram which shows 7th Example of this invention. 本発明の第８実施例を示す回路図である。It is a circuit diagram which shows 8th Example of this invention. 本発明の第９実施例を示す回路図である。It is a circuit diagram which shows 9th Example of this invention.
　以下、本発明の実施例を図面を用いて説明する。なお、上述した本発明の特徴以外の特徴については、以下の説明ならびに図面の記載より明らかになるであろう。また、以下の各実施例が備える各スイッチとしては、電力用半導体素子よりも小容量のＭＯＳＦＥＴなどの半導体スイッチング素子などが用いられる。
（実施例１）
  図１は、本発明の第１の実施例である半導体素子の駆動装置の回路図を示す。ここでは電力用半導体素子４として、ノーマリオフ型ＳｉＣ接合型ＦＥＴを例として説明する。なお、ＳｉＣとは、炭化珪素(Silicon Carbide)のことであり、半導体素子を構成する半導体材料の一種である。ＳｉＣは、シリコン(Si)に比べて破壊電界強度が大きいため、高耐圧かつ低損失の電力用半導体素子に適する。 Embodiments of the present invention will be described below with reference to the drawings. Note that features other than the features of the present invention described above will become clear from the following description and drawings. In addition, as each switch provided in each of the following embodiments, a semiconductor switching element such as a MOSFET having a smaller capacity than a power semiconductor element is used.
(Example 1)
FIG. 1 is a circuit diagram of a semiconductor device driving apparatus according to a first embodiment of the present invention. Here, as the power semiconductor element 4, a normally-off SiC junction FET will be described as an example. Note that SiC is silicon carbide and is a kind of semiconductor material that constitutes a semiconductor element. Since SiC has a higher breakdown electric field strength than silicon (Si), it is suitable for a power semiconductor device with high breakdown voltage and low loss.
　本実施例では、基準端子１はノーマリオフ型ＳｉＣ接合型ＦＥＴ４のソース端子、入力端子２はノーマリオフ型ＳｉＣ接合型ＦＥＴ４のゲート端子、出力端子３はノーマリオフ型ＳｉＣ接合型ＦＥＴ４のドレイン端子である。ソース端子１はグランド端子２５に接続する。また、駆動回路電源端子８は、グランド端子２５に対し、例えば１５Ｖに設定する。 In this embodiment, the reference terminal 1 is the source terminal of the normally-off type SiC junction FET 4, the input terminal 2 is the gate terminal of the normally-off type SiC junction FET 4, and the output terminal 3 is the drain terminal of the normally-off type SiC junction FET 4. The source terminal 1 is connected to the ground terminal 25. Further, the drive circuit power supply terminal 8 is set to, for example, 15V with respect to the ground terminal 25.
　本実施例では、ノーマリオフ型接合型ＦＥＴ４をオンさせるために、スイッチ１０をオフ、スイッチ９とスイッチ５をオンさせて、ノーマリオフ型接合型ＦＥＴ４のゲート端子３に抵抗７を介してゲート電流を供給する。このとき、ＳｉＣ接合型ＦＥＴ４のゲート端子電圧は駆動回路電源端子８の電圧と抵抗７の値により設定されるが、ゲート・ソース間はＰＮ接合ダイオードであるため、駆動回路電源端子８の電圧は主に抵抗７に印加される。このとき、コンデンサ６は駆動回路電源端子８の電圧（１５Ｖ）からノーマリオフ型ＳｉＣ接合型ＦＥＴ４のゲート端子電圧（例えば２．５Ｖ）を差し引いた電圧（約１２．５Ｖ）に充電される。 In this embodiment, in order to turn on the normally-off junction FET 4, the switch 10 is turned off, the switches 9 and 5 are turned on, and the gate current is supplied to the gate terminal 3 of the normally-off junction FET 4 via the resistor 7. To do. At this time, the gate terminal voltage of the SiC junction type FET 4 is set by the voltage of the drive circuit power supply terminal 8 and the value of the resistor 7, but since the gate-source is a PN junction diode, the voltage of the drive circuit power supply terminal 8 is Mainly applied to the resistor 7. At this time, the capacitor 6 is charged to a voltage (about 12.5 V) obtained by subtracting the gate terminal voltage (for example, 2.5 V) of the normally-off type SiC junction FET 4 from the voltage (15 V) of the drive circuit power supply terminal 8.
　ノーマリオフ型接合型ＦＥＴ４をオフさせるためにはスイッチ９とスイッチ５をオフさせてゲート電流を止め、更に、スイッチ１０をオンさせることにより、ノーマリオフ型接合型ＦＥＴ４のゲート端子３を、コンデンサ６の充電電圧によって負ゲート電圧駆動する。スイッチ５がオフすると、コンデンサ６の放電が抑制されるため接合型ＦＥＴ４のオフ状態を時間的に長く保持できる。 In order to turn off the normally-off junction type FET 4, the gate current is stopped by turning off the switch 9 and the switch 5, and further, the gate terminal 3 of the normally-off type junction FET 4 is charged to the capacitor 6 by turning on the switch 10. The negative gate voltage is driven by the voltage. When the switch 5 is turned off, the discharge of the capacitor 6 is suppressed, so that the junction FET 4 can be kept off for a long time.
　ノーマリオフ型ＳｉＣ接合型ＦＥＴはゲート・ソース間電圧がゼロボルトのときオフ状態になる。このため、ゲート・ソース間電圧に負電圧を印加しないとオフ状態にできないノーマリオン型ＳｉＣ接合型ＦＥＴに比べ、信頼性が高いシステムに使用できる。しかし、高速にオフさせてドレイン電圧が急峻に立ち上がるとドレイン・ゲート間の容量の影響で、ゲート端子３とソース端子１との間をゼロボルトにしていても、ノーマリオフ型ＳｉＣ接合型ＦＥＴ４には内部ゲート抵抗が存在するため、ノーマリオフ型ＳｉＣ接合型ＦＥＴ４のドレイン電流を実効的に決めている内部ゲート電圧が上昇し、ドレイン電流が流れてしまうセルフターンオン現象が発生する。このため、この無駄なドレイン電流によりノーマリオフ型ＳｉＣ接合型ＦＥＴ４のスイッチング損失が増加する。これに対し、ゲート端子を負ゲート電圧を印加することによりセルフターンオンを防止できるが、負ゲート電圧発生のための負電源を追加すると駆動回路のコストが高くなり、駆動回路のサイズも大きくなる。 The normally-off type SiC junction FET is turned off when the gate-source voltage is zero volts. Therefore, it can be used in a system with higher reliability than a normally-on type SiC junction FET that cannot be turned off unless a negative voltage is applied to the gate-source voltage. However, when the drain voltage rises sharply after being turned off at high speed, the normally-off type SiC junction FET 4 has no internal potential even if the gate terminal 3 and the source terminal 1 are set to zero volts due to the influence of the capacitance between the drain and gate. Since the gate resistance exists, the internal gate voltage that effectively determines the drain current of the normally-off type SiC junction FET 4 increases, and a self-turn-on phenomenon occurs in which the drain current flows. For this reason, this useless drain current increases the switching loss of the normally-off type SiC junction FET 4. On the other hand, self-turn-on can be prevented by applying a negative gate voltage to the gate terminal, but adding a negative power supply for generating a negative gate voltage increases the cost of the drive circuit and increases the size of the drive circuit.
　これに対し、本実施例では、上記のように単一電源駆動回路で負電圧駆動できるため、セルフターンオンによる無駄な消費電力の抑制を低コストで小型化の駆動回路で実現できる。 On the other hand, in this embodiment, since the negative voltage drive can be performed by the single power source drive circuit as described above, it is possible to realize the suppression of useless power consumption by the self-turn-on with a low cost and a small drive circuit.
　また、駆動回路電源端子８の電圧が変動しても、その変動分は抵抗７に印加される電圧により主に吸収できる。このため、ノーマリオフ型ＳｉＣ接合型ＦＥＴ４のゲート・ソース間電圧の変動を抑えられ、この結果、出力電流の変動も抑制できる。 Further, even if the voltage of the drive circuit power supply terminal 8 fluctuates, the fluctuation can be mainly absorbed by the voltage applied to the resistor 7. For this reason, the fluctuation | variation of the gate-source voltage of normally-off type SiC junction FET4 can be suppressed, As a result, the fluctuation | variation of an output current can also be suppressed.
　更に、ノーマリオフ型ＳｉＣ接合型ＦＥＴ４のオン状態のゲート端子電圧の変動を抑制できるため、ゲート端子電圧が過電圧となることを防止し、過大なゲート電流が流れない条件で低消費電力に駆動できる。 Furthermore, since the fluctuation of the gate terminal voltage in the ON state of the normally-off type SiC junction FET 4 can be suppressed, the gate terminal voltage can be prevented from being overvoltage, and can be driven with low power consumption under the condition that no excessive gate current flows.
　また、コンデンサ６に充電される電圧は駆動回路電源端子８の電圧と接合型ＦＥＴ４がオン状態でのゲート端子電圧で主に決定できるため、負ゲート電圧（絶対値）を大きくできる。 Further, since the voltage charged in the capacitor 6 can be mainly determined by the voltage of the drive circuit power supply terminal 8 and the gate terminal voltage when the junction FET 4 is on, the negative gate voltage (absolute value) can be increased.
　本実施例では電力用半導体素子４として、ノーマリオフ型ＳｉＣ接合型ＦＥＴを例として説明したが、バイポーラトランジスタでも同様の効果がある。また、Ｓｉデバイスなど他の半導体材料を用いたデバイスでも同様の効果があることは言うまでも無い。
（実施例２）
　図２は、本発明の第２の実施例である半導体素子の駆動装置の回路図である。図１で説明した実施例１との相違点は、スイッチ５の代わりに、スイッチ１１を用い、駆動回路電源端子８からスイッチ９を介さずに接合型ＦＥＴ４のゲート端子３にゲート電流を供給していることである。 In the present embodiment, a normally-off type SiC junction FET has been described as an example of the power semiconductor element 4, but a bipolar transistor has the same effect. Needless to say, a device using other semiconductor materials such as a Si device has the same effect.
(Example 2)
FIG. 2 is a circuit diagram of a semiconductor device driving apparatus according to a second embodiment of the present invention. The difference from the first embodiment described with reference to FIG. 1 is that a switch 11 is used instead of the switch 5, and a gate current is supplied from the drive circuit power supply terminal 8 to the gate terminal 3 of the junction FET 4 without going through the switch 9. It is that.
　すなわち、本実施例では、接合型ＦＥＴ４をオンさせるために、スイッチ１０をオフさせ、かつスイッチ１１をオンさせて、接合型ＦＥＴ４のゲート端子３に抵抗７を介してゲート電流を供給する。このとき、接合型ＦＥＴ４のゲート端子電圧は駆動回路電源端子８の電圧と抵抗７の値により設定されるが、ゲート・ソース間はダイオードであるため、駆動回路電源端子８の電圧は主に抵抗７に印加される。このとき、コンデンサ６は駆動回路電源端子８の電圧（１５Ｖ）からノーマリオフ型ＳｉＣ接合型ＦＥＴ４のゲート端子電圧（例えば２．５Ｖ）を差し引いた電圧（約１２．５Ｖ）に充電される。 That is, in this embodiment, in order to turn on the junction type FET 4, the switch 10 is turned off and the switch 11 is turned on to supply the gate current 3 to the gate terminal 3 of the junction type FET 4 through the resistor 7. At this time, the gate terminal voltage of the junction FET 4 is set by the voltage of the drive circuit power supply terminal 8 and the value of the resistor 7, but since the gate-source is a diode, the voltage of the drive circuit power supply terminal 8 is mainly a resistance. 7 is applied. At this time, the capacitor 6 is charged to a voltage (about 12.5 V) obtained by subtracting the gate terminal voltage (for example, 2.5 V) of the normally-off type SiC junction FET 4 from the voltage (15 V) of the drive circuit power supply terminal 8.
　ノーマリオフ型接合型ＦＥＴ４をオフさせるためにはスイッチ１１をオフさせてゲート電流を止め、更に、スイッチ９をオフ、スイッチ１０をオンさせることにより、ノーマリオフ型接合型ＦＥＴ４のゲート端子３を負電圧駆動させる。 In order to turn off the normally-off junction FET 4, the switch 11 is turned off to stop the gate current, and further, the switch 9 is turned off and the switch 10 is turned on to drive the gate terminal 3 of the normally-off junction FET 4 to a negative voltage. Let
　従って、本実施例の動作と効果は実施例１と同様である。
（実施例３）
　図３は、本発明の第３の実施例である半導体素子の駆動装置の回路図を示す。図２で説明した実施例２との相違点はスイッチ１１の代わりに、駆動回路電源端子８より低い電位に接続される駆動回路電源端子１３と抵抗７との間に接続したスイッチ１３を用いて、接合型ＦＥＴ４のゲート端子３にゲート電流を供給していることである。このため、本実施例では、駆動回路電源端子８の電位を高くして、負ゲート電圧（絶対値）を増加することと、駆動回路電源端子１３の電位を低くして、抵抗７の消費電力を低減することを独立に実行できる。 Therefore, the operation and effect of the present embodiment are the same as those of the first embodiment.
(Example 3)
FIG. 3 is a circuit diagram of a semiconductor device driving apparatus according to a third embodiment of the present invention. The difference from the second embodiment described with reference to FIG. 2 is that instead of the switch 11, a switch 13 connected between the drive circuit power supply terminal 13 connected to a potential lower than the drive circuit power supply terminal 8 and the resistor 7 is used. The gate current is supplied to the gate terminal 3 of the junction FET 4. For this reason, in this embodiment, the potential of the drive circuit power supply terminal 8 is increased to increase the negative gate voltage (absolute value), and the potential of the drive circuit power supply terminal 13 is decreased to reduce the power consumption of the resistor 7. Can be performed independently.
　その他の構成、動作と効果は実施例２と同様である。
（実施例４）
　図４は、本発明の第４の実施例である半導体素子の駆動装置の回路図を示す。本実施例では、図１に示したスイッチ５の具体的手段として、ゲート端子をグランド端子２５に接続し、ソース端子をスイッチ９とスイッチ１０の間の端子に接続し、ドレイン端子を接合型ＦＥＴ４のゲート端子３側に接続したｐチャネルＭＯＳＦＥＴ１４を使用する。図４では、ソースとボディを接続したｐチャネルＭＯＳＦＥＴ１４を接続して、ｐチャネルＭＯＳＦＥＴ１４のドレイン・ボディ間の寄生ダイオードを利用している。 Other configurations, operations, and effects are the same as those in the second embodiment.
Example 4
FIG. 4 shows a circuit diagram of a semiconductor device driving apparatus according to a fourth embodiment of the present invention. In the present embodiment, as a specific means of the switch 5 shown in FIG. 1, the gate terminal is connected to the ground terminal 25, the source terminal is connected to the terminal between the switch 9 and the switch 10, and the drain terminal is connected to the junction type FET 4. A p-channel MOSFET 14 connected to the gate terminal 3 side is used. In FIG. 4, a p-channel MOSFET 14 whose source and body are connected is connected, and a parasitic diode between the drain and body of the p-channel MOSFET 14 is used.
　ｐチャネルＭＯＳＦＥＴ１４のボディとソースを接続させない場合には、ｐチャネルＭＯＳＦＥＴ１４のドレインとソースの間に外付けダイオードを図４に示したドレイン・ボディ間の寄生ダイオードと同じ向きにしても同様の効果が得られる。 When the body and source of the p-channel MOSFET 14 are not connected, the same effect can be obtained even if an external diode is placed between the drain and source of the p-channel MOSFET 14 in the same direction as the parasitic diode between the drain and body shown in FIG. can get.
　図４に示した本実施例では、ｐチャネルＭＯＳＦＥＴ１４が図１に示したスイッチ５の機能を備えるため、スイッチ５並びにその駆動回路が不要になる。 In the present embodiment shown in FIG. 4, since the p-channel MOSFET 14 has the function of the switch 5 shown in FIG. 1, the switch 5 and its drive circuit are not required.
　その他の構成,動作と効果は実施例１と同様である。
（実施例５）
　図５は、本発明の第５の実施例である半導体素子の駆動装置の回路図を示す。本実施例では、図４に示した実施例４において、抵抗１５とＳｉのダイオード１６の直列接続回路を接合ＦＥＴ４のゲート・ソース間に接続している。ＳｉＣ接合ＦＥＴのしきい電圧はＳｉダイオードの順方向電圧より低いため、抵抗１５は接合ＦＥＴを確実にオフさせるための短絡抵抗として機能できる。ダイオード１６は負ゲート電圧が印加されたときに抵抗１５を介してコンデンサ６が放電することを防止するために設けてある。また、本実施例では接合ＦＥＴ４のスイッチング速度を調整するための抵抗２９を設けた場合を示してあるが、なくても構わない。その他の構成,動作と効果は実施例４と同様である。 Other configurations, operations, and effects are the same as those in the first embodiment.
(Example 5)
FIG. 5 is a circuit diagram of a semiconductor device driving apparatus according to a fifth embodiment of the present invention. In this embodiment, in the fourth embodiment shown in FIG. 4, a series connection circuit of a resistor 15 and a Si diode 16 is connected between the gate and source of the junction FET 4. Since the threshold voltage of the SiC junction FET is lower than the forward voltage of the Si diode, the resistor 15 can function as a short-circuit resistance for reliably turning off the junction FET. The diode 16 is provided to prevent the capacitor 6 from being discharged through the resistor 15 when a negative gate voltage is applied. In the present embodiment, the case where the resistor 29 for adjusting the switching speed of the junction FET 4 is provided is shown, but it may not be provided. Other configurations, operations, and effects are the same as those in the fourth embodiment.
　なお、ここで、接合ＦＥＴ４のゲート・ソース間の順方向電圧降下より、ダイオード１６の順方向電圧降下を低くすると接合ＦＥＴ４のゲート・ソース間を短絡する効果が生じる。この条件は接合ＦＥＴ４にワイドバンドギャップ半導素子を使用し、ダイオード１６にシリコン半導素子を使用することにより、容易に実現できる。
（実施例６）
　図６は、本発明の第６の実施例である半導体素子の駆動装置の回路図を示す。本実施例では、図５に示した実施例５において、ＭＯＳＦＥＴ１４におけるソース端子とゲート端子の間に抵抗３４を接続すると共に、グランド端子２５とＭＯＳＦＥＴ１４のゲート端子の間に電圧クランプ要素であるツェナーダイオード３３が接続される。これにより、ｐチャネルＭＯＳＦＥＴ１４のゲート・ソース間耐圧が十分得られにくい場合でも、駆動回路電源８を高くして接合ＦＥＴ４を駆動できる。 Here, if the forward voltage drop of the diode 16 is made lower than the forward voltage drop between the gate and the source of the junction FET 4, an effect of short-circuiting between the gate and the source of the junction FET 4 occurs. This condition can be easily realized by using a wide band gap semiconductor element for the junction FET 4 and a silicon semiconductor element for the diode 16.
(Example 6)
FIG. 6 is a circuit diagram of a semiconductor device driving apparatus according to a sixth embodiment of the present invention. In this embodiment, in the fifth embodiment shown in FIG. 5, a resistor 34 is connected between the source terminal and the gate terminal of the MOSFET 14, and a Zener diode which is a voltage clamping element is connected between the ground terminal 25 and the gate terminal of the MOSFET 14. 33 is connected. As a result, even when it is difficult to sufficiently obtain the gate-source breakdown voltage of the p-channel MOSFET 14, the drive FET power supply 8 can be increased to drive the junction FET 4.
　その他の構成、動作と効果は実施例５と同様である。
（実施例７）
　図７は、本発明の第７の実施例である半導体素子の駆動装置の回路図を示す。本実施例では、図５に示した本発明の実施例５のダイオード１６の代わりにｎチャネルＭＯＳＦＥＴ１７のドレイン・ボディ間ダイオードを用いている。ｎチャネルＭＯＳＦＥＴ１７のゲート・ソース間の電圧がしきい電圧以上になると、ｎチャネルＭＯＳＦＥＴ１７がオンして、接合ＦＥＴ４のゲート・ソース間は短絡抵抗１５により短絡される。例えば、接合ＦＥＴ４にワイドバンドギャップ半導体材料を用いた場合には、接合ＦＥＴ４のゲート・ソース間の順方向電圧降下が約２．５Ｖであるため、ｎチャネルＭＯＳＦＥＴ１７のしきい電圧は２．５Ｖ以下にすることが望ましい。 Other configurations, operations, and effects are the same as those in the fifth embodiment.
(Example 7)
FIG. 7 is a circuit diagram of a semiconductor device driving apparatus according to a seventh embodiment of the present invention. In the present embodiment, a drain-body diode of an n-channel MOSFET 17 is used instead of the diode 16 of the fifth embodiment of the present invention shown in FIG. When the voltage between the gate and the source of the n-channel MOSFET 17 becomes equal to or higher than the threshold voltage, the n-channel MOSFET 17 is turned on, and the gate and the source of the junction FET 4 are short-circuited by the short-circuit resistor 15. For example, when a wide band gap semiconductor material is used for the junction FET 4, the forward voltage drop between the gate and the source of the junction FET 4 is about 2.5V, so the threshold voltage of the n-channel MOSFET 17 is 2.5V or less. It is desirable to make it.
　なお、ここで、接合ＦＥＴ４にワイドバンドギャップ半導素子を使用し、ＭＯＳＦＥＴ１７にシリコン半導体素子を使用するとＭＯＳＦＥＴ１７が十分にはオンしない場合でもＭＯＳＦＥＴ１７のドレイン・ボディ間にある寄生ダイオードが順バイアスされやすいため接合ＦＥＴ４のゲート・ソース間を短絡させやすい。 Here, when a wide band gap semiconductor element is used for the junction FET 4 and a silicon semiconductor element is used for the MOSFET 17, the parasitic diode between the drain and the body of the MOSFET 17 is easily forward-biased even when the MOSFET 17 is not sufficiently turned on. Therefore, it is easy to short-circuit between the gate and source of the junction FET 4.
　その他の構成、動作と効果は実施例５と同様である。
（実施例８）
　図８は、本発明の第８の実施例である半導体素子の駆動装置の回路図を示す。本実施例では、図２に示したスイッチ９，１１の具体的手段として、それぞれｐチャネルＭＯＳＦＥＴ３０，３１が用いられ、かつスイッチ１０の具体的手段としてｎチャネルＭＯＳＦＥＴ３２が用いられる。本実施例ではｐチャネルＭＯＳＦＥＴ３０とｐチャネルＭＯＳＦＥＴ３１のソース端子を接続するため、図２におけるスイッチ９,１１を同時に駆動する回路が構成しやすい。また半導体集積回路（ＩＣ）のように同一チップに設けられるＭＯＳＦＥＴを使用できる。　
　その他の構成,動作と効果は実施例２と同様である。 Other configurations, operations, and effects are the same as those in the fifth embodiment.
(Example 8)
FIG. 8 is a circuit diagram of a semiconductor device driving apparatus according to an eighth embodiment of the present invention. In the present embodiment, p- channel MOSFETs 30 and 31 are used as specific means of the switches 9 and 11 shown in FIG. 2, and an n-channel MOSFET 32 is used as specific means of the switch 10, respectively. In this embodiment, since the source terminals of the p-channel MOSFET 30 and the p-channel MOSFET 31 are connected, it is easy to configure a circuit that simultaneously drives the switches 9 and 11 in FIG. Further, MOSFETs provided on the same chip such as a semiconductor integrated circuit (IC) can be used.
Other configurations, operations and effects are the same as those of the second embodiment.
　（実施例９）
　図９は、本発明の第９の実施例であるインバータ回路を示す。本実施例では、ゲート駆動回路２０，２１に実施例１から実施例８で説明したいずれかの駆動装置が用いられる。本実施例のインバータ回路では実施例１から実施例８で説明した駆動装置により半導体素子１８,１９がオン・オフ制御される。これにより、インバータ回路の低消費電力化や小型化が可能になる。 Example 9
FIG. 9 shows an inverter circuit according to a ninth embodiment of the present invention. In this embodiment, any one of the driving devices described in the first to eighth embodiments is used for the gate driving circuits 20 and 21. In the inverter circuit of the present embodiment, the semiconductor elements 18 and 19 are on / off controlled by the driving apparatus described in the first to eighth embodiments. As a result, the power consumption and size of the inverter circuit can be reduced.
１　基準端子
２　入力端子
３　出力端子
４，１８，１９半導体素子
５，９，１０，１１，１２　スイッチ
６　コンデンサ
７，１５，２９，３０，３４　抵抗
８，１３　駆動回路電源端子
１７，３０，３１，３２　ＭＯＳＦＥＴ
１６　ダイオード
２０，２１　ゲート駆動回路
２２，２３　駆動回路電源
２５　グランド端子
２６　高圧端子
２７　出力端子 DESCRIPTION OF SYMBOLS 1 Reference terminal 2 Input terminal 3 Output terminal 4, 18, 19 Semiconductor element 5, 9, 10, 11, 12 Switch 6 Capacitor 7, 15, 29, 30, 34 Resistor 8, 13 Drive circuit power supply terminal 17, 30, 31 , 32 MOSFET
16 Diodes 20, 21 Gate drive circuits 22, 23 Drive circuit power supply 25 Ground terminal 26 High voltage terminal 27 Output terminal

Claims (10)

  1. 　少なくとも基準端子（１）と入力端子（３）と出力端子（２）を有する半導体素子（４）の前記入力端子（３）に接続した第１スイッチ（５）をオンさせて前記半導体素子（４）をオンする手段と、
    　前記半導体素子（４）の前記入力端子に接続されたコンデンサ（５）を介して前記基準端子（１）に対し前記入力端子（３）に逆極性電圧を印加することにより前記半導体素子（４）をオフさせる手段と、
    　前記半導体素子（４）をオフさせた時に前記第１スイッチ（５）をオフさせる手段と、を有することを特徴とする半導体素子の駆動装置。     A first switch (5) connected to the input terminal (3) of a semiconductor element (4) having at least a reference terminal (1), an input terminal (3) and an output terminal (2) is turned on to turn on the semiconductor element (4 )
    By applying a reverse polarity voltage to the input terminal (3) with respect to the reference terminal (1) via a capacitor (5) connected to the input terminal of the semiconductor element (4), the semiconductor element (4) Means for turning off,
    Means for turning off the first switch (5) when the semiconductor element (4) is turned off.
  2. 　前記第１スイッチ（５）と前記コンデンサ（６）が第２スイッチ（９）を介して駆動回路電源端子（８）に接続され、なおかつ、第３スイッチ（１０）を介してグランド端子（２５）に接続されていることを特徴とする請求項１に記載の半導体素子の駆動装置。 The first switch (5) and the capacitor (6) are connected to the drive circuit power supply terminal (8) via the second switch (9), and the ground terminal (25) via the third switch (10). The device for driving a semiconductor element according to claim 1, wherein the driving device is connected to the semiconductor element.
  3. 　前記第１スイッチ（１１）は駆動回路電源端子（８）に接続され、前記コンデンサ（６）は第２スイッチ（９）を介して前記駆動回路電源端子（８）に接続され、かつ、第３スイッチ（１０）を介してグランド端子（２５）に接続されていることを特徴とする請求項１に記載の半導体素子の駆動装置。 The first switch (11) is connected to a drive circuit power supply terminal (8), the capacitor (6) is connected to the drive circuit power supply terminal (8) via a second switch (9), and a third 2. The driving device for a semiconductor device according to claim 1, wherein the driving device is connected to a ground terminal (25) through a switch (10).
  4. 　前記コンデンサ（６）の充電に使われる駆動回路電源端子（８）と前記
    半導体素子（４）の入力端子に電流を供給する駆動回路電源端子（１３）の電位が異なることを特徴とする請求項３に記載の半導体素子の駆動装置。     The drive circuit power supply terminal (13) for supplying a current to the input terminal of the semiconductor element (4) and the drive circuit power supply terminal (8) used for charging the capacitor (6) are different from each other. 4. A drive device for a semiconductor device according to 3.
  5. 　前記第１スイッチ（５）として、ゲート端子は前記半導体素子（４）の基準端子（１）に接続され、ドレイン端子は前記半導体素子（４）の入力端子（３）に接続され、ソース端子は前記第２スイッチを介して前記駆動回路電源端子（８）に接続されるＭＯＳＦＥＴを用いたことを特徴とする請求項１に記載の半導体素子の駆動装置。 As the first switch (5), the gate terminal is connected to the reference terminal (1) of the semiconductor element (4), the drain terminal is connected to the input terminal (3) of the semiconductor element (4), and the source terminal is 2. The semiconductor device driving apparatus according to claim 1, wherein a MOSFET connected to the driving circuit power supply terminal via the second switch is used. 3.
  6. 　前記半導体素子４の基準端子（１）と入力端子（３）の間に抵抗（１５）とダイオード（１６）を接続したことを特徴とする請求項１に記載の半導体素子の駆動装置。 The drive device for a semiconductor element according to claim 1, wherein a resistor (15) and a diode (16) are connected between a reference terminal (1) and an input terminal (3) of the semiconductor element 4.
  7. 　前記ダイオード（１６）はシリコン、前記半導体素子（４）はワイドバンドギャップ半導体で構成されていることを特徴とする請求項６に記載の半導体素子の駆動装置。 The device for driving a semiconductor element according to claim 6, wherein the diode (16) is made of silicon and the semiconductor element (4) is made of a wide band gap semiconductor.
  8. 　前記ＭＯＳＦＥＴ（１４）のゲート端子が電圧クランプ手段（３３）を介して前記半導体素子４の基準端子（１）接続されることを特徴とする請求項５に記載の半導体素子の駆動装置。 6. The driving device for a semiconductor element according to claim 5, wherein the gate terminal of the MOSFET (14) is connected to the reference terminal (1) of the semiconductor element 4 via a voltage clamping means (33).
  9. 　前記半導体素子４の基準端子（１）と入力端子（３）の間に、ゲート端子が前記半導体素子（４）の前記入力端子に接続されるＭＯＳＦＥＴ（１７）が接続されることを特徴とする請求項１に記載の半導体素子の駆動装置。 A MOSFET (17) whose gate terminal is connected to the input terminal of the semiconductor element (4) is connected between the reference terminal (1) and the input terminal (3) of the semiconductor element 4. The driving device for a semiconductor element according to claim 1.
  10. 　半導体素子のむゲート駆動回路として請求項１から請求項９のいずれか１項に記載の半導体素子の駆動装置を用いたことを特徴とするインバータ回路。 10. An inverter circuit using the semiconductor element driving device according to claim 1 as a gate driving circuit for a semiconductor element.
PCT/JP2013/054649 2013-02-25 2013-02-25 Device for driving semiconductor element WO2014128942A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017063365A (en) * 2015-09-25 2017-03-30 ニチコン株式会社 Gate drive circuit
KR20180080136A (en) * 2017-01-03 2018-07-11 제네럴 일렉트릭 컴퍼니 Systems and methods for a gate drive circuit
EP3579413A1 (en) * 2018-06-07 2019-12-11 Vishay-Siliconix Devices and methods for driving a semiconductor switching device
WO2020017506A1 (en) * 2018-07-17 2020-01-23 三菱電機株式会社 Drive circuit and electric power conversion apparatus
JP2021129335A (en) * 2020-02-10 2021-09-02 Tdk株式会社 Driving circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175561A (en) * 2003-12-08 2005-06-30 Renesas Technology Corp Power supply circuit for high frequency power amplifier circuit, semiconductor integrated circuit for power supply, and electronic component for power supply
JP2007336694A (en) * 2006-06-15 2007-12-27 Mitsubishi Electric Corp Drive circuit for insulated-gate semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5668341U (en) * 1979-10-30 1981-06-06
JP3478596B2 (en) * 1993-05-27 2003-12-15 富士通株式会社 Power supply connection circuit and power supply line switch IC
JP4844007B2 (en) * 2005-05-18 2011-12-21 富士電機株式会社 Composite type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005175561A (en) * 2003-12-08 2005-06-30 Renesas Technology Corp Power supply circuit for high frequency power amplifier circuit, semiconductor integrated circuit for power supply, and electronic component for power supply
JP2007336694A (en) * 2006-06-15 2007-12-27 Mitsubishi Electric Corp Drive circuit for insulated-gate semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017063365A (en) * 2015-09-25 2017-03-30 ニチコン株式会社 Gate drive circuit
KR20180080136A (en) * 2017-01-03 2018-07-11 제네럴 일렉트릭 컴퍼니 Systems and methods for a gate drive circuit
JP2018113682A (en) * 2017-01-03 2018-07-19 ゼネラル・エレクトリック・カンパニイ System for gate drive circuit and method
JP7250421B2 (en) 2017-01-03 2023-04-03 ゼネラル・エレクトリック・カンパニイ Systems and methods for gate drive circuits
KR102398189B1 (en) 2017-01-03 2022-05-17 제네럴 일렉트릭 컴퍼니 Systems and methods for a gate drive circuit
KR102363644B1 (en) * 2018-06-07 2022-02-15 비쉐이-실리코닉스 Devices and methods for driving a semiconductor switching device
EP3579413A1 (en) * 2018-06-07 2019-12-11 Vishay-Siliconix Devices and methods for driving a semiconductor switching device
CN110581702A (en) * 2018-06-07 2019-12-17 维西埃-硅化物公司 Device and method for driving semiconductor switch device
KR20190139154A (en) * 2018-06-07 2019-12-17 비쉐이-실리코닉스 Devices and methods for driving a semiconductor switching device
US10622994B2 (en) 2018-06-07 2020-04-14 Vishay-Siliconix, LLC Devices and methods for driving a semiconductor switching device
WO2020017506A1 (en) * 2018-07-17 2020-01-23 三菱電機株式会社 Drive circuit and electric power conversion apparatus
JP6639763B1 (en) * 2018-07-17 2020-02-05 三菱電機株式会社 Drive circuit and power converter
JP2021129335A (en) * 2020-02-10 2021-09-02 Tdk株式会社 Driving circuit
JP7359016B2 (en) 2020-02-10 2023-10-11 Tdk株式会社 drive circuit

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