JP2014168131A - CMOS inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS inverter circuit that suppresses the occurrence of a through current.SOLUTION: The CMOS inverter circuit includes: a first CMOS inverter circuit 10; switch elements 13, 14 for interrupting a through current between the first CMOS inverter circuit and power supplies; diodes 15, 16 reversely biased between junctions of the switch elements 13, 14 and the first CMOS inverter circuit 10 and the power supplies; and a second CMOS inverter circuit 20 for receiving an output signal of the first CMOS inverter circuit 10 as an input signal. The second CMOS inverter circuit 20 controls the switch elements 13, 14 with an output signal thereof.

Description

  Embodiments described herein relate generally to a CMOS inverter circuit.

  Conventionally, a CMOS inverter circuit is used at the output stage of a complementary metal oxide semiconductor (CMOS) integrated circuit.

  As shown in the circuit diagram of FIG. 3, in the conventional CMOS inverter circuit 100, the drain terminals and the gate terminals of the pMOS transistor 102 and the nMOS transistor 104 are connected in common, and the source terminal of the pMOS transistor 102 is at a high level. Connected to the power supply VH, the source terminal of the nMOS transistor 104 is connected to the low level power supply VL.

  In the CMOS inverter circuit 100, the input signal Si is supplied to the gate terminals connected in common, and the output signal So is taken out from the drain terminals connected in common.

  In the CMOS inverter circuit 100, when the input signal Si is high level, the nMOS transistor 104 is turned on and the pMOS transistor 102 is turned off. When the input signal Si is low level, the pMOS transistor 102 is turned on. Since the transistor 104 is turned off, ideally, the pMOS transistor 102 and the nMOS transistor 104 are not turned on at the same time.

That is, the operation of the CMOS inverter circuit 100 is as follows.

VH-voltage level of input signal Si Vi> threshold voltage of pMOS transistor 102

At this time, the pMOS transistor 102 is turned on. Also,

Voltage level of input signal Si Vi-VL> threshold voltage of nMOS transistor 104

At this time, the nMOS transistor 104 is turned on.

  Therefore, it is generally widely used as a component of a circuit that requires low power consumption.

Suzuki Yasuo, Takeguchi Higuchi, pp. 374 of “Patent Pulse Circuit Technology Encyclopedia”, Ohm Company, May 20, 1980, first edition, first edition issued

  However, when the voltage level Vi of the input signal Si is gradually switched, such as when the capacitive load of the input signal wiring is large, the voltage of the input signal Si is shown in the voltage waveform diagram of FIG. During the level Vi transition period, both the pMOS transistor 102 and the nMOS transistor 104 are turned on, and a large through current K flows from the high-level power supply VH to the low-level power supply VL.

  In view of the above problems, an embodiment of the present invention aims to provide a CMOS inverter circuit that can suppress the generation of a through current.

  An embodiment of the present invention includes a first CMOS inverter circuit in which drains and gates of a first pMOS transistor and a first nMOS transistor are connected in common, and between the first CMOS inverter circuit and a power source. A switching element for blocking a through current, a diode reversely biased between a connection point of the switching element and the first CMOS inverter circuit and the power source, and drains of the second pMOS transistor and the second nMOS transistor And a second CMOS inverter circuit that inputs the output signal of the first CMOS inverter circuit as an input signal, and the second CMOS inverter circuit outputs the output signal of the first CMOS inverter circuit. This is a CMOS inverter circuit for controlling the switch element.

  According to the CMOS inverter circuit of the embodiment of the present invention, the pMOS transistor and the nMOS transistor are simultaneously turned on even when the voltage level of the input signal is slowly switched due to the influence of the capacitive load of the wiring of the input signal. Thus, it is possible to prevent a through current from flowing.

It is a circuit diagram of the CMOS inverter circuit of one Embodiment. It is a voltage waveform diagram of the CMOS inverter circuit of one Embodiment, (a) is an input signal, (b) is an output signal, (c) is a voltage waveform diagram of a through current. It is a circuit diagram of the conventional CMOS inverter circuit. It is a voltage waveform diagram of the conventional CMOS inverter circuit, (a) is an input signal, (b) is an output signal, (c) is a voltage waveform diagram of a through current.

  Hereinafter, the CMOS inverter circuit 1 according to the present embodiment will be described with reference to FIGS. 1 and 2.

(1) Configuration of CMOS Inverter Circuit 1 The configuration of the CMOS inverter circuit 1 will be described based on the circuit diagram of FIG.

  The first CMOS inverter circuit 10 is a circuit in which the drains and gates of the pMOS transistor 11 and the nMOS transistor 12 are connected in common, and receives the input signal Si and outputs the output signal So.

  The second CMOS inverter circuit 20 is a circuit in which the drains and gates of the pMOS transistor 21 and the nMOS transistor 22 are connected in common. The second CMOS inverter circuit 20 uses the output signal So of the first CMOS inverter circuit 10 as the input signal Si.

  A switch transistor 13 is connected to a connection point (node n1) between the first CMOS inverter circuit 10 and the high-level power supply VH. The switch transistor 13 is a pMOS transistor.

  A switch transistor 14 is connected to a connection point (node n2) between the first CMOS inverter circuit 10 and the low-level power supply VL. The switch transistor 14 is an nMOS transistor.

  On / off of the switch transistor 13 and the switch transistor 14 is respectively controlled by an output signal of the second CMOS inverter circuit 20.

  A diode 15 is connected with reverse bias between the node n1 and the high-level power supply VH. The diode 15 is obtained by short-circuiting the gate terminal and the source terminal of the nMOS transistor.

  A diode 16 is connected with a reverse bias between the node n2 and the low-level power supply VL. The diode 16 is obtained by short-circuiting the gate terminal and the source terminal of the pMOS transistor.

(2) Operating State of CMOS Inverter Circuit 1 Hereinafter, the operating state of the CMOS inverter circuit 1 will be described with reference to FIGS.

  When the switch transistor 13 is in the OFF state, the threshold voltage of the VH-switch transistor 13 is applied to the node n1 by the diode 15.

  When the switch transistor 13 is on, the potential of the high level power supply VH is applied to the node n1.

  When the switch transistor 14 is off, the threshold voltage of the VL-switch transistor 14 is applied to the node n2 by the diode 16.

  When the switch transistor 14 is on, the potential of the low level power supply VL is applied to the node n2.

  Since the switch transistors 13 and 14 are in a complementary relationship with a common gate signal, when one is on, the other is off. The gate signals of the switch transistors 13 and 14 are obtained by inverting the logic of the output of the first CMOS inverter circuit 10 by the second CMOS inverter circuit 20.

  That is, when the input signal Si of the first CMOS inverter circuit 10 transitions from the low level state to the high level, the state immediately before the input signal Si switches to the high level is the node n1 at the high level power supply VH. A potential is applied, and the threshold voltage of the VL-switch transistor 14 is applied to the node n2.

  Further, when the input signal Si of the first CMOS inverter circuit 10 transitions from the high level to the low level, the state immediately before the input signal Si switches to the low level is the node n1 at the VH-switch transistor. The threshold voltage of 13 is applied, and the potential of the low-level power supply VL is applied to the node n2.

  As described above, the first CMOS inverter circuit 10 can turn on the pMOS transistor 11 when the voltage level Vi of the input signal Si reaches the condition of the following expression (1).

VH−threshold voltage of the switch transistor 13−voltage level Vi of the input signal Si> threshold voltage of the pMOS transistor 11 (1)

The first CMOS inverter circuit 10 can turn on the nMOS transistor 12 when the voltage level Vi of the input signal Si reaches the condition of the following expression (2).

Voltage level of input signal Vi-VL-threshold voltage of switch transistor> threshold voltage of nMOS transistor 12 (2)

Whereas the logical threshold value of the conventional CMOS inverter circuit 100 is located between VH and VL as shown in the voltage waveform diagram of FIG. 4, the CMOS inverter circuit 10 of the present embodiment has the voltage waveform of FIG. As shown, the logic threshold is offset to the shallow side with respect to the power supply voltage.

  Therefore, even when the change in the voltage level Vi of the input signal Si is gentle, the first CMOS inverter circuit 10 can eliminate the period in which both the pMOS transistor 11 and the nMOS transistor 12 are on, Since the through current K can be cut by feedback of the CMOS inverter circuit 20, a significant current reduction effect can be obtained with respect to the conventional CMOS inverter circuit 100, and the CMOS inverter circuit 1 with low power consumption can be configured.

(3) Effect According to the CMOS inverter circuit 1 of the present embodiment, the pMOS transistor and the nMOS transistor are simultaneously connected even when the voltage level of the input signal is gradually switched due to the capacitive load of the wiring of the input signal. It is possible to prevent the through current from flowing in the on state.

  Further, the low power consumption CMOS inverter circuit 1 can be configured.

(4) Modification Example The low level VL may be GND.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... 1st CMOS inverter circuit, 11 ... pMOS transistor, 12 ... nMOS transistor, 13 ... Switch transistor, 14 ... Switch transistor, 15 ... Diode, 16 ... Diode 20 ... second CMOS inverter circuit, 21 ... pMOS transistor, 22 ... nMOS transistor

Claims (4)

A first CMOS inverter circuit in which drains and gates of the first pMOS transistor and the first nMOS transistor are connected in common;
A switch element for cutting off a through current between the first CMOS inverter circuit and a power source;
A diode reverse-biased between a connection point of the switch element and the first CMOS inverter circuit and the power source;
A second CMOS inverter circuit in which drains and gates of the second pMOS transistor and the second nMOS transistor are connected in common, and an output signal of the first CMOS inverter circuit is input as an input signal;
The second CMOS inverter circuit controls the switch element by its output signal.
CMOS inverter circuit. The switch element includes a first switch transistor connected between the first pMOS transistor and a high level power supply, and a second switch connected between the first nMOS transistor and a low level power supply. Consisting of transistors,
The CMOS inverter circuit according to claim 1. The diode includes a first diode connected between the first pMOS transistor and a high level power supply, and a second diode connected between the first nMOS transistor and a low level power supply. ,
The CMOS inverter circuit according to claim 1 or 2. The first diode is a short circuit between the gate terminal and the source terminal of the nMOS transistor, and the second diode is a short circuit between the gate terminal and the source terminal of the pMOS transistor.
The CMOS inverter circuit according to claim 3.

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