JP5595204B2 - Switching element drive circuit - Google Patents

Description

  The present invention relates to a drive circuit for driving a control electrode of a semiconductor switching element.

  A power converter such as a PWM (Pulse Width Modulation) inverter is provided with a plurality of arms in which two semiconductor switching elements of a positive electrode and a negative electrode of a DC power supply are connected in series (so-called totem pole type). In recent years, a so-called level shift circuit that does not perform insulation by a transformer or a photocoupler is used as a circuit for driving a switching element on the high potential side of each arm.

  For example, Japanese Patent Laid-Open No. 2000-252809 (Patent Document 1) discloses a configuration example of this type of level shift circuit. According to the document, the level shift circuit includes first and second controllable semiconductor elements, a DC power supply, first and second load resistors, a logic circuit, and signal invalidation means. Prepare. Each controllable semiconductor element has a potential reference electrode connected to a common potential, and a conduction signal is input between the potential reference electrode and the control electrode, and the potential reference electrode and the main electrode are electrically connected. It becomes a state. The direct current power source is connected to a predetermined part of an external circuit where one pole varies between a common potential and a predetermined high potential, and has a voltage lower than the voltage between the two potentials. One end of each of the first and second load resistors is connected to the other pole of the DC power source, and the other end is connected to the main electrode of each of the first and second controllable semiconductor elements. The logic circuit operates under the direct current power source. Pulse control signals are input to the control electrodes of the first and second controllable semiconductor elements at different timings. At this time, a pulsed voltage drop generated in the first and second load resistors due to the conduction of the controllable semiconductor element is transmitted as a signal to the logic circuit. The signal invalidating means prevents the signal of the voltage drop from being transmitted to the logic circuit when a pulse voltage drop occurs simultaneously in the first and second load resistors. Specifically, the signal invalidating means masks the voltage drop signal of the first load resistor transmitted to the logic circuit with the mask signal generated based on the voltage drop of the second load resistor, and transmits the signal to the logic circuit. The signal of the voltage drop of the second load resistor is masked by the mask signal generated based on the voltage drop of the first load resistor.

JP 2000-252809 A

  When driving a high-potential side switching element and making a transition from off to on using a driving circuit including the level shift circuit of the above document, or driving a low potential side switching element and making a transition from on to off, The midpoint potential of the totem pole rises. At this time, the junction capacitance (parasitic capacitance) between the main electrode of each controllable semiconductor element and the substrate (common potential) is charged, and the first and second load resistors are charged with the parasitic capacitance. Charging current flows. As a result, a voltage drop occurs simultaneously in the first and second load resistors. Usually, there is a shift in the parasitic capacitance of the first and second controllable semiconductor elements due to manufacturing variations and the like, so that the voltage drop due to the first and second load resistances also shifts. If the deviation of the voltage drop amount is large, the mask by the signal invalidation means does not work, so that an error signal may be transmitted to the logic circuit.

  An object of the present invention is to provide a driving circuit for a switching element, which is more reliable than before by preventing malfunction.

  In one aspect, the present invention provides a drive circuit for a high-potential side switching element among two switching elements connected in series between a first power supply node and a second power supply node set at a higher potential. In addition, a third power supply node, a logic circuit, first and second resistance units, a first control switching element, and a first comparison unit are provided. The third power supply node is set to a potential higher than the potential of the connection node of the two switching elements. The logic circuit has first and second states as internal states, and corresponds to the first and second states in order to switch the high-potential side switching element to an on state or an off state according to the internal state. Then, a control signal for switching to the first and second logic levels is output. The first resistance unit is provided between the third power supply node and the first node. The second resistance unit is provided between the first node and the second node. The first control switching element is provided between the second node and the first power supply node, and is turned on when receiving the first pulse signal. The first comparison unit switches the logic circuit from the first state to the second state in response to the first pulse signal, so that the active state is obtained when the potential of the first node is equal to or lower than the first threshold value. The first signal is output. The resistance value of at least one of the first and second resistance units changes at a timing based on at least a change in the control signal.

  According to the switching element drive circuit of one aspect of the present invention, malfunction is prevented by changing the resistance value of at least one of the first and second resistance portions at least at a timing based on the change of the control signal. Therefore, the reliability can be improved as compared with the prior art.

It is a circuit diagram which shows the structure of the drive circuit (high voltage IC) HVIC of the switching element by Embodiment 1 of this invention. It is a figure which shows the case where the drive circuit HVIC of FIG. 1 is connected to the high potential side switching element Q5 of the H bridge. FIG. 2 is a timing chart showing an operation of the drive circuit HVIC in FIG. 1. FIG. 6 is a circuit diagram showing a modification of the drive circuit HVIC in FIG. 1. It is a circuit diagram which shows the structure of the drive circuit HVICb of the switching element by Embodiment 2 of this invention. FIG. 6 is a timing chart showing the operation of the drive circuit HVIC in FIG. 1 in comparison with the operation of the drive circuit HVICb in FIG. 5. 6 is a timing chart when the low potential side switching element Q6 is turned off in the drive circuit HVICb of FIG. It is a circuit diagram which shows the structure of the drive circuit HVICc of the switching element by Embodiment 3 of this invention. It is a circuit diagram which shows an example of a structure of the constant current source I1 shown in FIG. FIG. 9 is a timing diagram illustrating an operation of the drive circuit HVICc of FIG. 8. It is a circuit diagram which shows the structure of the drive circuit HVICd of the switching element by Embodiment 4 of this invention. FIG. 12 is a timing diagram illustrating an operation of the drive circuit HVICd of FIG. 11. It is a circuit diagram which shows the structure of the drive circuit HVICe of the switching element by Embodiment 5 of this invention. FIG. 14 is a timing chart showing an operation of the drive circuit HVICe of FIG. 13. It is a circuit diagram which shows the structure of the drive circuit HVICf of the switching element by Embodiment 6 of this invention. FIG. 16 is a timing chart showing the operation of the drive circuit HVICe of FIG. 13 and the operation of the drive circuit HVICf of FIG. 15 in comparison. FIG. 16 is a timing chart when the low potential side switching element Q6 is turned off in the drive circuit HVICf of FIG. 15;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of Drive Circuit HVIC]
FIG. 1 is a circuit diagram showing a configuration of a switching element drive circuit (high voltage IC) HVIC according to Embodiment 1 of the present invention.

  Referring to FIG. 1, drive circuit HVIC is an integrated circuit (IC: Integrated Circuit) for driving high-potential side switching element Q5 connected totem pole in accordance with input signal IN to an on state and an off state. . High potential side switching element Q5 and low potential side switching element Q6 are connected in series between high potential side power supply node HVN to which high voltage power supply HV is connected and low potential side power supply node (ground node) GND. FIG. 1 shows an IGBT (Insulated Gate Bipolar Transistor) as an example of the high potential side switching element Q5 and the low potential side switching element Q6.

  A high potential side freewheel diode D3 is connected in the reverse bias direction between the collector and emitter of the high potential side switching element (IGBT) Q5. A low potential side freewheel diode D4 is connected in the reverse bias direction between the collector and emitter of the low potential side switching element (IGBT) Q6. A connection node ND0 between the high potential side switching element Q5 and the low potential side switching element Q6 is connected to a virtual ground node VS of the drive circuit HVIC. The control electrode (IGBT gate) of the high potential side switching element Q5 is connected to the signal output node HO of the drive circuit HVIC. A DC power supply V1 is connected between the power supply node VB and the virtual ground node VS of the drive circuit HVIC. The control electrode of the low potential side switching element Q6 is connected to the signal output node LO of the drive circuit for the low potential side.

  The drive circuit HVIC includes a one-shot pulse generation circuit C1, NMOS (Negative channel Metal Oxide Semiconductor) transistors Q1 and Q2 (control switching elements), and a high voltage circuit unit C2. The one-shot pulse generation circuit C1 generates and outputs a pulse signal PLS1 for turning on the high potential side switching element Q5 in synchronization with the rising edge of the input signal IN, and synchronizes with the falling edge of the input signal IN. Then, the pulse signal PLS2 for turning off the high potential side switching element Q5 is generated and output.

  The NMOS transistor Q1 is connected between the node ND2 of the high voltage circuit unit C2 and the ground node GND, and becomes conductive by receiving the pulse signal PLS1 from the one-shot pulse generation circuit C1 at the gate. As a result, the pulse signal PLS1 is transmitted to the high voltage circuit unit C2. The NMOS transistor Q2 is connected between the node ND4 of the high voltage circuit unit C2 and the ground node GND, and becomes conductive by receiving the pulse signal PLS2 from the one-shot pulse generation circuit C1 at the gate. As a result, the pulse signal PLS2 is transmitted to the high voltage circuit unit C2.

  The reason why the pulse signals PLS1 and PLS2 are supplied to the gates of the NMOS transistors Q1 and Q2 by the one-shot pulse generation circuit C1 is to suppress current consumption of the resistance elements R1 to R4 used as load resistors of the NMOS transistors Q1 and Q2. It is. Since the input signal is a pulse signal, an RS flip-flop U15 is provided in the high voltage circuit unit C2 to hold the input signal.

  The high voltage circuit unit C2 includes resistance elements R1 to R4, clamping diodes D1 and D2, inverters U1 to U4, a filter circuit C3, an RS flip-flop U15, and an output stage circuit C4.

Resistance elements R1 and R2 are connected in series between power supply node VB and node ND2 in this order (hereinafter, a connection node of resistance elements R1 and R2 is referred to as node ND1). When NMOS transistor Q1 is turned on by receiving pulse signal PLS1, a current flows from power supply node VB to ground node GND through resistance elements R1, R2 and NMOS transistor Q1. As a result, a pulse-like voltage drop generated in the resistance elements R1 and R2 becomes the nodes ND1 and ND2.
It is detected as a potential change at.

  Similarly, resistance elements R3 and R4 are connected in series between power supply node VB and node ND4 in this order (hereinafter, a connection node of resistance elements R3 and R4 is referred to as node ND3). When NMOS transistor Q2 is turned on by receiving pulse signal PLS2, a current flows from power supply node VB to ground node GND through resistance elements R3 and R4 and NMOS transistor Q2. As a result, a pulse voltage drop generated in the resistance elements R3 and R4 is detected as a potential change at the nodes ND3 and ND4.

  The potential change of the node ND1 is used as an on signal Son for turning on the high potential side switching element Q5. The potential change of the node ND3 is used as an off signal Soff for turning off the high potential side switching element Q5. The potential change of the node ND2 is used as a mask signal Mon for masking the off signal Soff. The potential change of the node ND4 is used as a mask signal Moff for masking the on signal Son.

  The diode D1 is connected between the virtual ground node VS and the node ND2 so that the virtual ground node VS side becomes an anode so that an excessive current does not flow through the resistance elements R1 and R2. The diode D2 is connected between the virtual ground node VS and the node ND4 so that the virtual ground node VS side becomes an anode so that an excessive current does not flow through the resistance elements R3 and R4.

Inverters U1-U4 are driven by DC power supply V1. The inverter U4 receives the ON signal Son from the node ND1, and outputs a high level (also referred to as H level) signal when the ON signal Son becomes equal to or lower than the threshold value of the inverter U4 . Inverter U3 receives mask signal Mon from node ND2, and outputs an H level signal when mask signal Mon falls below the threshold of inverter U3. Inverter U1 receives off signal Soff from node ND3, and outputs an H-level signal when off signal Soff falls below the threshold of inverter U1. Inverter U2 receives mask signal Moff from node ND4, and outputs an H-level signal when mask signal Moff falls below the threshold value of inverter U2. In the following description, it is assumed that the threshold values of the inverters U1 to U4 are all equal.

  Filter circuit C3 includes NAND circuits U5 to U7, inverters U8 to U12, and NOR circuits U13 and U14. Each of these elements and the RS flip-flop U15 are driven by a DC power supply V1.

  The NAND circuit U7 is used as a NOT circuit (inverter) that inverts the logic level of the output of the inverter U4. The output of the NAND circuit U7 is input to the first input node of the NOR circuit U14 via the inverters U10 and U12. Therefore, a low level (also referred to as L level) signal is input to the first input node of the NOR circuit U14 when the ON signal Son is equal to or lower than the threshold value of the inverter U4.

  The NAND circuit U5 is used as a NOT circuit (inverter) that inverts the logic level of the output of the inverter U1. The output of the NAND circuit U5 is input to the first input node of the NOR circuit U13 via the inverters U8 and U11. Therefore, an L level signal is input to the first input node of the NOR circuit U13 when the off signal Soff is equal to or lower than the threshold value of the inverter U1.

  NAND circuit U6 receives the outputs of inverters U2 and U3. The output of the NAND circuit U6 is input to the second input nodes of the NOR circuits U13 and U14 via the inverter U9. Therefore, an H level signal is input to each of the second input nodes of the NOR circuits U13 and U14 when the mask signal Mon is equal to or lower than the threshold value of the inverter U3 and the mask signal Moff is equal to or lower than the threshold value of the inverter U2. The

  The output of the NOR circuit U14 is input to the set terminal (S) of the RS flip-flop U15, and the output of the NOR circuit U13 is input to the reset terminal (R) of the RS flip-flop U15. Accordingly, an H level signal is input to the set terminal (S) of the RS flip-flop U15 if the ON signal Son is equal to or lower than the threshold value of the inverter U4 and the mask signal Moff exceeds the threshold value of the inverter U2. An H level signal is input to the reset terminal (R) of the RS flip-flop U15 if the off signal Soff is less than or equal to the threshold value of the inverter U1 and the mask signal Mon exceeds the threshold value of the inverter U3.

  Output stage circuit C4 includes NMOS transistors Q3 and Q4. NMOS transistors Q3 and Q4 are connected in series between power supply node VB and virtual ground node VS in this order. The gate of the NMOS transistor Q3 is connected to the output terminal (Q) of the RS flip-flop U15, and the gate of the NMOS transistor Q4 is connected to the inverting output terminal (QB) of the RS flip-flop U15. The connection node of the NMOS transistors Q3 and Q4 is connected to the control electrode (the gate of the IGBT) of the high potential side switching element Q5 via the signal output node HO. Therefore, when the RS flip-flop U15 is set, the high potential side switching element Q5 is turned on, and when the RS flip flop U15 is reset, the high potential side switching element Q5 is turned off.

  High voltage circuit unit C2 further includes resistance elements R5 and R6 and switches SW1 and SW2.

  Resistance element R5 is provided in parallel with resistance element R1 between power supply node VB and node ND1. Switch SW1 (control switching element) is provided in series with resistance element R5 between power supply node VB and node ND1. The switch SW1 is turned on when the output signal of the inverting output terminal (QB) of the RS flip-flop U15 becomes H level.

  Resistance element R6 is provided in parallel with resistance element R3 between power supply node VB and node ND3. Switch SW2 (control switching element) is provided in series with resistance element R6 between power supply node VB and node ND3. The switch SW2 is turned on when the output signal of the output terminal (Q) of the RS flip-flop U15 becomes H level.

  As the switches SW1 and SW2, for example, PMOS (Positive channel Metal Oxide Semiconductor) transistors or NMOS transistors can be used. When a PMOS transistor is used, an inverter is provided between the output terminal (Q) or the inverted output terminal (QB) of the RS flip-flop U15 and the gate of the PMOS transistor.

  In FIG. 1, the resistance element RP1 is configured by the resistance elements R1 and R5 and the switch SW1. The resistance value of the resistance unit RP1 changes according to the logic level of the inverting output terminal (QB) of the RS flip-flop U15. Resistance element RP3 is comprised by resistance element R3, R6 and switch SW2. The resistance value of the resistance unit RP3 changes according to the logic level of the output terminal (Q) of the RS flip-flop U15. In the drive circuit HVIC of FIG. 1, the malfunction of the drive circuit HVIC can be prevented by using the resistance portions RP1 and RP3 whose resistance values change as load resistances of the NMOS transistors Q1 and Q2.

[Malfunction mechanism]
Prior to describing the operation of the resistance parts RP1 and RP3, when the resistance elements R1 and R3 are provided instead of the resistance parts RP1 and RP3 (that is, the resistance elements R5 and R6 and the switches SW1 and SW2 are provided). The reason why a malfunction occurs in the drive circuit HVIC is described.

  FIG. 2 is a diagram showing a case where the drive circuit HVIC of FIG. 1 is connected to the high potential side switching element Q5 of the H bridge. Referring to FIG. 2, high potential side switching element Q5b and low potential side switching element Q6b are further connected in series in this order between high potential side power supply node HVN and ground node GND. Freewheel diodes D3b and D4b are provided in antiparallel with switching elements Q5b and Q6b, respectively. Inductive load L1 is connected between connection node ND0 of switching elements Q5 and Q6 and connection node ND0b of switching elements Q5b and Q6b. In FIG. 2, switching elements Q5, Q6, Q5b, and Q6b are IGBTs.

  In FIG. 2, it is assumed that the transistors Q5b and Q6 are on and the transistors Q5 and Q6b are off. When the transistor Q6 is turned off from this state, a free wheel current flows through the transistor Q5b in the on state, the load L1, and the diode D3. As a result, the potential of node ND0 (virtual ground node VS) rises (in other words, positive dV / dt is applied to virtual ground node VS). Since the potential of power supply node VB is equal to the value obtained by adding the voltage of DC power supply V1 to the potential of virtual ground node VS, when the potential of virtual ground node VS rises, the potential of power supply node VB also rises at the same voltage change rate.

  The same thing occurs when the transistors Q5b and Q6 are off and the transistors Q5 and Q6b are on. When the transistor Q6b is turned off from this state, the potential of the node ND0 (that is, the virtual ground node VS) may increase (that is, positive dV / dt is applied to the virtual ground node VS). In the case of a three-phase inverter, the potential of the virtual ground node VS may rise (that is, positive dV / dt is applied to the virtual ground node VS) as described above.

  Referring to FIG. 1 again, when the signal output node HO of the drive circuit HVIC is in the L level and the potential of the node LO is changed from the H level to the L level, the low potential side switching element Q6 is turned off from the on state. Assume that the state has changed. At this time, the potential of the virtual ground node VS and the potential of the power supply node VB rise according to the switching speed of the low potential side switching element Q6. As a result, the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged, so that a parasitic capacitance charging current flows through the resistance elements R1 and R2 and the resistance elements R3 and R4. Due to the voltage drop due to this charging current, the input potentials (Son, Mon, Soff, Moff) of the inverters U1 to U4 in the next stage are lowered. Here, if the parasitic capacitance of the NMOS transistor Q1 for the on signal is larger than the parasitic capacitance of the NMOS transistor Q2 for the off signal, the potentials of the nodes ND1 and ND2 (that is, the on signal Son and the mask signal Mon) are the nodes. This is lower than the potentials of ND3 and ND4 (that is, the off signal Soff and the mask signal Moff). As a result, if the ON signal Son falls below the threshold value of the inverter U4 before the mask signal Moff falls below the threshold value of the inverter U2, an H level signal is input to the set terminal (S) of the RS flip-flop U15. As a result, the high potential side switching element Q5 malfunctions from the off state to the on state.

[Operation of Drive Circuit HVIC]
FIG. 3 is a timing chart showing the operation of the drive circuit HVIC of FIG. In FIG. 3, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, and U4, inverted output terminal (QB), output terminal (Q), reset terminal (R), and set terminal (S) of RS flip-flop U15 ) And the voltage waveform of the signal output node HO of the drive circuit HVIC are shown. Hereinafter, the functions of the resistance units RP1 and RP3 in FIG. 1 will be described with reference to FIGS.

  In FIG. 3, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVIC becomes L level, the switch SW1 of the resistor unit RP1 is turned on, and the switch SW2 of the resistor unit RP3 is turned off. Since the switch SW1 is in the ON state, the resistance value of the resistance unit RP1 (resistance value between the power supply node VB and the node ND1) is a parallel combined resistance of the resistance elements R1 and R5 (described as R1 // R5). Thus, it is smaller than the resistance value when the switch SW1 is in the OFF state (resistance value of the resistance element R1). On the other hand, the resistance value of the resistance unit RP3 (resistance value between the power supply node VB and the node ND3) is the resistance value of the resistance element R3 because the switch SW2 is in the off state, and the parallel combination of the resistance elements R3 and R6. It is larger than the resistance (described as R3 // R6).

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, the resistance value (R1 // R5) of the resistance unit RP1 (between the power supply node VB and the node ND1) and the resistance value (R3) of the resistance unit RP3 (between the power supply node VB and the node ND3) Since the voltage drop amount differs depending on the difference, the potentials (Soff, Moff) of the nodes ND3, ND4 are lower than the potentials (Son, Mon) of the nodes ND1, ND2.

  For this reason, at time t2, the mask signal Moff first becomes equal to or lower than the threshold value TH of the inverter U2. As a result, the output of the inverter U2 is switched to the H level. Next, at time t3, the off signal Soff becomes equal to or lower than the threshold value TH of the inverter U1, whereby the output of the inverter U1 is switched to the H level. Next, when the mask signal Mon becomes equal to or lower than the threshold value TH of the inverter U3 at time t4, the output of the inverter U3 is switched to the H level. Next, at time t5, the ON signal Son becomes equal to or lower than the threshold value TH of the inverter U4, whereby the output of the inverter U4 is switched to the H level. Between time t3 and t4, the input to the reset terminal (R) of the RS flip-flop U15 becomes H level, but since the RS flip-flop U15 is originally reset, the output terminal (Q) and the inverted output terminal The logic level of (QB) does not change. As a result, the signal output node HO of the drive circuit HVIC maintains the L level, and the drive circuit HVIC can perform a normal operation.

  At the next time t6, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t7, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

[Modification]
FIG. 4 is a circuit diagram showing a modification of the drive circuit HVIC of FIG. In this modification, as shown in FIG. 4A, a resistance element R1, a resistance portion RP2, and a MOS transistor Q1 are provided in series in this order between a power supply node VB and a ground node GND. Further, as shown in FIG. 4B, a resistance element R3, a resistance unit RP4, and a MOS transistor Q2 are provided in series in this order between the power supply node VB and the ground node GND.

  Referring to FIG. 4A, resistance unit RP2 includes a resistance element R2 provided between nodes ND1 and ND2, and a resistance element provided between node ND2 and the drain of NMOS transistor Q1 (node ND7). R7 and switch SW1 provided in parallel with resistance element R7. The switch SW1 is turned on when the output terminal (Q) of the RS flip-flop U15 is at H level, and is turned off when it is at L level. Therefore, when the RS flip-flop U15 is in the set state, the charging current due to the parasitic capacitance of the NMOS transistor Q1 is bypassed via the switch SW1 without flowing through the resistance element R7. On the other hand, when the RS flip-flop U15 is in the reset state, the charging current due to the parasitic capacitance of the NMOS transistor Q1 flows through the resistance element R7, so that the decrease in the potentials of the nodes ND1 and ND2 is smaller than in the set state. As a result, malfunction can be prevented.

  Referring to FIG. 4B, resistance unit RP3 includes a resistance element R3 provided between nodes ND3 and ND4, and a resistance element provided between node ND4 and the drain of NMOS transistor Q2 (node ND8). R8 and switch SW2 provided in parallel with resistance element R8. The switch SW2 is turned on when the inverting output terminal (QB) of the RS flip-flop U15 is at H level, and is turned off when it is at L level. Therefore, when the RS flip-flop U15 is in the reset state, the charging current due to the parasitic capacitance of the NMOS transistor Q2 is bypassed via the switch SW2 without flowing through the resistance element R8. On the other hand, when the RS flip-flop U15 is in the set state, the charging current due to the parasitic capacitance of the NMOS transistor Q2 flows through the resistance element R8, so that the decrease in the potentials of the nodes ND3 and ND4 is reduced as compared with the set state. As a result, malfunction can be prevented.

  In summary, the resistor RP1 is provided between the power supply node VB and the node ND1 where the ON signal Son is detected, and the resistor RP2 is provided between the node ND1 and the NMOS transistor Q1. When the RS flip-flop U15 is in the reset state (the high potential side switching element Q5 is in the off state), the resistance value of the resistance unit RP1 is larger than that in the set state (the high potential side switching element Q5 is in the on state). The resistance value of at least one of the resistance parts RP1 and RP2 changes so that the ratio of the resistance values of the resistance part RP2 increases. As a result, it is possible to prevent the switching element Q5 on the high potential side from malfunctioning from the off state to the on state.

  Similarly, a resistance unit RP3 is provided between the power supply node VB and the node ND3 where the off signal Soff is detected, and a resistance unit RP4 is provided between the node ND3 and the NMOS transistor Q2. When the RS flip-flop U15 is in the set state (the high potential side switching element Q5 is in the on state), the resistance value of the resistance unit RP3 is larger than that in the reset state (the high potential side switching element Q5 is in the off state). The resistance value of at least one of the resistance parts RP3 and RP4 changes so that the ratio of the resistance values of the resistance part RP4 increases. This can prevent the switching element Q5 on the high potential side from malfunctioning from the on state to the off state.

<Embodiment 2>
In the drive circuit HVIC according to the first embodiment shown in FIG. 1, one of the switches SW1 and SW2 is always on. Therefore, the pulse width of the signal input to the set terminal (S) of the RS flip-flop U15 when the pulse signal PLS1 is input to the NMOS transistor Q1, and the RS when the pulse signal PLS2 is input to the NMOS transistor Q2 The pulse width of the signal input to the reset terminal (R) of the flip-flop U15 is shorter than before. As a result, there is a problem that the noise tolerance is lower than in the prior art.

  In the drive circuit HVICb according to the second embodiment, the control sequence of the switches SW1 and SW2 uses the mask signals Mon and Moff so that the switches SW1 and SW2 are turned on only when the potential of the virtual ground node VS rises. Change to As a result, it is possible to prevent a reduction in noise tolerance. This will be specifically described below.

  FIG. 5 is a circuit diagram showing a configuration of a switching element drive circuit HVICb according to the second embodiment of the present invention.

  The resistance unit RP1b provided in the high voltage circuit unit C2b of FIG. 5 is different from the resistance unit RP1 of FIG. 1 in that it further includes an AND circuit U16. The AND circuit U16 receives the output of the inverting output terminal (QB) of the RS flip-flop U15 and the output of the inverter U2, and supplies an H level signal to the switch SW1 when both outputs are at the H level. Switch SW1 becomes conductive when the signal received from AND circuit U16 is at the H level.

  The resistance unit RP3b provided in the high voltage circuit unit C2b of FIG. 5 is different from the resistance unit RP3 of FIG. 1 in that it further includes an AND circuit U17. The AND circuit U17 receives the output of the output terminal (Q) of the RS flip-flop U15 and the output of the inverter U3, and supplies an H level signal to the switch SW2 when both outputs are at the H level. Switch SW2 becomes conductive when the signal received from AND circuit U17 is at the H level.

  Since the other points of FIG. 5 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 6 is a timing chart showing the operation of the drive circuit HVIC in FIG. 1 in comparison with the operation of the drive circuit HVICb in FIG. The graph on the left side of FIG. 6 shows the voltage waveform of each part of the drive circuit HVIC (Embodiment 1) when the high potential side switching element Q5 is turned on. The graph on the right side of FIG. 6 shows the voltage waveform of each part of the drive circuit HVICb (second embodiment) in the same case. In the left and right graphs, the voltage waveforms of the input signal IN and the output pulse signals PLS1 and PLS2 of the one-shot pulse generation circuit C1, the on signal Son, the mask signal Mon, the off signal Soff, and the mask signal Moff are sequentially shown from the top. Voltage waveforms, output voltage waveforms of the inverters U3, U4, U2 and U1, voltage waveforms of the output terminal (Q) and the inverted output terminal (QB) of the RS flip-flop U15, ON / OFF states of the switches SW2 and SW1, RS Each voltage waveform of the set terminal (S) and the reset terminal (R) of the flip-flop U15 and the voltage waveform of the signal output node HO of the drive circuits HVIC and HVICb are shown.

  First, the case of the drive circuit HVIC according to the first embodiment will be described with reference to the graphs on the left side of FIGS. In this case, in the initial state, the input signal IN of the one-shot pulse generation circuit C1 is at L level. At this time, since the RS flip-flop U15 is in a reset state, the output terminal (Q) is at the L level and the inverted output terminal (QB) is at the H level. In the case of the drive circuit HVIC in FIG. 1, since the switch SW1 is in the on state, the resistance value of the resistance unit RP1 (between the node ND1 and the power supply node VB) is the resistance value of the resistance element R1 and the resistance element R5. The combined resistance (R1 // R5) with the resistance value of

  When the input signal IN is switched to the H level at time t1, the one-shot pulse generation circuit C1 outputs a pulse signal PLS1 (pulse width from time t1 to time t4). As a result, the potentials (Son, Mon) of the nodes ND1, ND2 are lowered.

  At the next time t2, since the potential of the node ND2 (mask signal Mon) becomes equal to or lower than the threshold value TH of the inverter U3, the output of the inverter U3 is switched to the H level.

  At the next time t3, since the potential of the node ND1 (ON signal Son) becomes equal to or lower than the threshold value TH of the inverter U4, the output of the inverter U4 is switched to the H level. As a result, the input of the set terminal (S) of the RS flip-flop U15 becomes H level, so that the output terminal (Q) of the RS flip-flop U15 is switched to H level and the inverting output terminal (QB) is switched to L level. Instead, the signal output node HO of the drive circuit HVIC is switched to the H level. Furthermore, the switch SW1 is turned off and the switch SW2 is turned on in accordance with the voltage change of the output terminal (Q) and the inverted output terminal (QB) of the RS flip-flop U15. When the switch SW1 is turned off, the resistance value of the resistance unit RP1 (between the node ND1 and the power supply node VB) increases to the resistance value of the resistance element R1, so that the on signal Son and the mask signal are steeper than before the time t3. Mon drops.

  At the next time t4, the gate input (PLS2) of the NMOS transistor Q1 returns to 0V, so that the potentials (Son, Mon) of the nodes ND1, ND2 return to the original potential (the potential of the power supply node VB). As a result, the outputs of the inverters U3 and U4 are switched to the L level, and the input to the set terminal (S) to the RS flip-flop U15 returns to the L level.

Next, with reference to the right of the graphs of FIGS. 5 and 6, it will be described for the case of the drive circuit HVICb according to the second embodiment. In this case, in the initial state, the graph is the same as that on the left side except that the switch SW1 is in the OFF state. The switch SW1 is controlled by the output of the inverting output terminal (QB) of the RS flip-flop U15 and the output of the inverter U2. In the initial state, the inverting output terminal (QB) is at the H level, but since the output of the inverter U2 is at the L level, the switch SW1 is in the OFF state. As a result, the resistance value of resistance unit RP1b (between node ND1 and power supply node VB) is equal to the resistance value of resistance element R1.

  At time t11, when the input signal IN is switched to the H level, the one-shot pulse generation circuit C1 outputs a pulse signal PLS1 (pulse width from time t11 to time t14). As a result, the potentials (Son, Mon) of the nodes ND1, ND2 are lowered. The speed of potential drop at this time becomes faster because the resistance value between the nodes VB and ND1 is increased as compared with the graph on the left side of FIG.

  At time t12, since the potential of the node ND2 (mask signal Mon) becomes equal to or lower than the threshold value TH of the inverter U3, the output of the inverter U3 is switched to the H level.

  At the next time t13, since the potential of the node ND1 (ON signal Son) becomes equal to or lower than the threshold value TH of the inverter U4, the output of the inverter U4 is switched to the H level. As a result, the input of the set terminal (S) of the RS flip-flop U15 becomes H level, so that the output terminal (Q) of the RS flip-flop U15 is switched to H level and the inverting output terminal (QB) is switched to L level. Instead, the signal output node HO of the drive circuit HVICb is switched to the H level. At this time, since the output of the inverter U3 is at the H level, the switch SW2 is turned on.

  At the next time t14, the gate input (PLS2) of the NMOS transistor Q1 returns to 0V, so that the potentials (Son, Mon) of the nodes ND1, ND2 return to the original potential (the potential of the power supply node VB). As a result, the outputs of the inverters U3 and U4 are switched to the L level, the input to the set terminal (S) to the RS flip-flop U15 returns to the L level, and the switch SW2 returns to the off state.

  The pulse width of the signal input to the set terminal (S) of the RS flip-flop U15 is set to the case of the first embodiment (from time t3 to time t4) and the case of the second embodiment (from time t13 to time t14). Compare Then, the pulse width in the second embodiment (from time t13 to time t14) is longer than the pulse width in the first embodiment (from time t3 to time t4). As a result, the noise tolerance in the case of the second embodiment is improved as compared with the case of the first embodiment.

  FIG. 7 is a timing chart when the low potential side switching element Q6 is turned off in the drive circuit HVICb of FIG. In FIG. 7, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, U4, voltage waveforms of inverted output terminal (QB) and output terminal (Q) of RS flip-flop U15, ON / OFF of switches SW1, SW2 The OFF state, the voltage waveforms of the reset terminal (R) and the set terminal (S) of the RS flip-flop U15, and the voltage waveform of the signal output node HO of the drive circuit HVICb are shown.

  In FIG. 7, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVICb becomes L level, and the switch SW2 of the resistor unit RP3 is turned off. The switch SW1 of the resistor unit RP1 is turned off because the output of the inverter U2 is at the L level. Therefore, the resistance value of the resistance unit RP1b (between the power supply node VB and the node ND1) is equal to the resistance value of the resistance element R1, and the resistance value of the resistance unit RP3b (between the power supply node VB and the node ND3) is It becomes equal to the resistance value of the resistance element R3.

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, if the resistance values of the resistance elements R1 and R2 are equal to the resistance values of the resistance elements R3 and R4 and the parasitic capacitances of the NMOS transistors Q1 and Q2 are equal to each other, the potential of the node ND1 (ON signal Son) The potential of the node ND3 (off signal Soff) decreases at the same speed, and the potential of the node ND2 (mask signal Mon) and the potential of the node ND4 (mask signal Moff) decrease at the same speed.

  At the next time t2, since the mask signals Mon and Moff become equal to or lower than the threshold value TH, the outputs of the inverters U2 and U3 are switched to the H level. Since the inverting output terminal (QB) of the RS flip-flop U15 is at the H level and the output of the inverter U2 is at the H level, the switch SW1 is turned on. As a result, the resistance value of the resistance unit RP1b (between the node ND1 and the power supply node VB) becomes a parallel combined resistance (R1 // R5) of the resistance value of the resistance element R1 and the resistance value of the resistance element R5. As a result, after time t2, the ON signal Son and the mask signal Mon decrease more slowly than the OFF signal Soff and the mask signal Moff.

  At the next time t3, the off signal Soff becomes equal to or lower than the threshold value TH, so that the output of the inverter U1 is switched to the H level. Since the mask signal Mon is already below the threshold value TH, the input of the reset terminal (R) of the RS flip-flop U15 remains at the L level.

At the next time t4, the ON signal Son becomes equal to or lower than the threshold value TH of the inverter U4, whereby the output of the inverter U4 is switched to the H level. Since the mask signal Moff is already below the threshold value TH, the input of the set terminal (S) of the RS flip-flop U15 remains at the L level.

  At the next time t5, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t6, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

  As described above, even when the potential of the virtual ground node VS of the drive circuit HVICb increases, the signal output node HO maintains the L level, and the drive circuit HVICb can perform a normal operation.

<Embodiment 3>
FIG. 8 is a circuit diagram showing a configuration of a switching element drive circuit HVICc according to the third embodiment of the present invention.

  The high voltage circuit unit C2c of FIG. 8 differs from the high voltage circuit unit C2 of FIG. 1 in that constant current supply units CS1 and CS2 are provided instead of the resistance elements R5 and R6 and the switches SW1 and SW2 of FIG. .

  Specifically, the constant current supply unit CS1 includes a constant current source I1 provided in parallel with the resistance element R1 between the power supply node VB and the node ND1, and a constant current source between the constant current source I1 and the node ND1. A switch SW1 provided in series with I1. The switch SW1 receives the output of the output terminal (Q) of the RS flip-flop U15, and becomes conductive when the output terminal (Q) is at the H level. Therefore, the constant current source I1 supplies a current to the NMOS transistor Q1 for generating the on signal Son via the resistor element R2 when the high potential side switching element Q5 is in the on state (the RS flip-flop U15 is in the set state). Supply.

  The constant current supply section CS2 is connected in series with the constant current source I2 provided in parallel with the resistor element R3 between the power supply node VB and the node ND3, and between the constant current source I2 and the node ND3. And a provided switch SW2. The switch SW2 receives the output of the inverting output terminal (QB) of the RS flip-flop U15, and becomes conductive when the output terminal (QB) is at the H level. The constant current source I2 supplies a current to the NMOS transistor Q2 for generating the off signal Soff via the resistor element R4 when the high potential side switching element Q5 is in the off state (the RS flip-flop U15 is in the reset state). . Since the other points of FIG. 8 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In FIG. 8, each of the resistance elements R1 to R4 can be replaced with a plurality of resistance elements connected in series and / or in parallel. In this specification, the case where there is one resistance element and the case where there are a plurality of resistance elements are referred to as a resistance portion.

  FIG. 9 is a circuit diagram showing an example of the configuration of the constant current source I1 shown in FIG. Since the configuration of the constant current source I2 is the same as that of the constant current source I1, FIG. 9 shows the configuration of the constant current source I1 as a representative.

  Referring to FIG. 9, constant current source I1 includes an NMOS transistor Q101, PMOS transistors Q102 and Q103, a resistance element R101, a reference power supply VREF, and a differential amplifier U101. Differential amplifier U101 operates with a voltage (DC power supply V1 in FIG. 8) between power supply node VB and virtual ground node VS. PMOS transistor Q103, NMOS transistor Q101, and resistance element R101 are connected in series between power supply node VB and virtual ground node VS in this order. The PMOS transistors Q102 and Q103 constitute a current mirror. The negative electrode of reference power supply VREF is connected to virtual ground node VS, and the positive electrode is connected to the non-inverting input terminal of differential amplifier U101. The inverting input terminal of the differential amplifier U101 is connected to the source (node ND101) of the NMOS transistor Q101, and the output terminal of the differential amplifier U101 is connected to the gate of the NMOS transistor Q101.

  With the above configuration, a reference current corresponding to the voltage of the reference power supply VREF flows through the NMOS transistor Q101. This reference current is copied by the PMOS transistor Q102 that constitutes a current mirror with the PMOS transistor Q103, and is supplied to the resistance element R3 and the NMOS transistor Q1 via the switch SW1.

  FIG. 10 is a timing chart showing the operation of the drive circuit HVICc of FIG. In FIG. 10, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, and U4, inverted output terminal (QB), output terminal (Q), reset terminal (R), and set terminal (S) of RS flip-flop U15 ) And the voltage waveform of the signal output node HO of the drive circuit HVICc are shown. The functions of the constant current supply units CS1 and CS2 in FIG. 8 will be described below with reference to FIGS.

  In FIG. 10, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVICc becomes L level, the switch SW1 of the constant current supply unit CS1 is turned off, and the switch SW2 of the constant current supply unit CS2 is turned on.

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, since the switch SW2 is in the ON state, a larger amount of charging current flows through the resistance element R4 than the charging current flowing through the resistance element R2 by the amount of the current from the constant current source I2. As a result, the potentials of the nodes ND3 and ND4 (off signal Soff and mask signal Moff) are lower than the potentials of the nodes ND1 and ND2 (on signal Son and mask signal Mon).

  Therefore, at the next time t2, the mask signal Moff first becomes equal to or lower than the threshold value TH of the inverter U2. As a result, the output of the inverter U2 is switched to the H level.

  At the next time t3, the OFF signal Soff becomes equal to or lower than the threshold value TH of the inverter U1, so that the output of the inverter U1 is switched to the H level. When the mask signal Mon becomes equal to or lower than the threshold value TH of the inverter U3 at the next time t4, the output of the inverter U3 is switched to the H level.

  Between time t3 and t4, the input to the reset terminal (R) of the RS flip-flop U15 becomes H level, but since the RS flip-flop U15 is originally reset, the output terminal (Q) and the inverted output terminal The logic level of (QB) does not change. As a result, the signal output node HO of the drive circuit HVICc maintains the L level, and the drive circuit HVICc can perform a normal operation.

  At the next time t5, when the ON signal Son becomes equal to or lower than the threshold value TH of the inverter U4, the output of the inverter U4 is switched to the H level.

  At the next time t6, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t7, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

  In the drive circuits HVIC and HVICb of the first and second embodiments, the resistance elements R5 and R6 are provided instead of the constant current sources I1 and I2. When the resistance elements R5 and R6 are used, depending on the potential change rate (dV / dt) of the virtual ground node VS, the potential difference between the on signal Son and the off signal Soff and the potential difference between the mask signals Mon and Moff. Changes. On the other hand, in the case of the third embodiment, the potential difference between the ON signal Son and the OFF signal Soff and the potential difference between the mask signals Mon and Moff depend on the potential change rate (dV / dt) of the virtual ground node VS. Can be generated without. Therefore, in the case of the third embodiment, a drive circuit with higher reliability can be realized as compared with the first and second embodiments.

  As another advantage, by using the constant current sources I1 and I2, the on / off timings of the switches SW1 and SW2 are reversed compared to the drive circuit HVIC of the first embodiment. For this reason, since the resistance value of the load connected to the NMOS transistor to which the pulse signal is input next from the one-shot pulse generation circuit C1 does not change, the design is facilitated.

  In the above description, the currents from the constant current sources I1 and I2 are injected into the nodes ND1 and ND3, respectively. For example, a resistance element may be further provided in series with the resistance element R2 between the nodes ND1 and ND2, and a current from the constant current source I1 may be injected into a connection node of these resistance elements. Alternatively, a resistance element may be further provided in series with the resistance element R1 between the power supply node VB and the node ND1, and a current from the constant current source I1 may be injected into a connection node of these resistance elements. That is, in the case where a resistance portion composed of one or more resistance elements is provided between the node ND1 and the NMOS transistor Q1, a current is supplied to the NMOS transistor Q1 via at least one of these resistance elements. What should I do? The same applies to the constant current source I2.

<Embodiment 4>
FIG. 11 is a circuit diagram showing a configuration of a switching element drive circuit HVICd according to the fourth embodiment of the present invention.

  A constant current supply unit CS1b provided in the high voltage circuit unit C2d of FIG. 11 is different from the constant current supply unit CS1 of FIG. 8 in that it further includes an AND circuit U16. The AND circuit U16 receives the output of the output terminal (Q) of the RS flip-flop U15 and the output of the inverter U3, and supplies an H level signal to the switch SW1 when both outputs are at the H level. Switch SW1 becomes conductive when the signal received from AND circuit U16 is at the H level.

  A constant current supply unit CS2b provided in the high voltage circuit unit C2d of FIG. 11 is different from the constant current supply unit CS2 of FIG. 8 in that it further includes an AND circuit U17. The AND circuit U17 receives the output of the inverting output terminal (QB) of the RS flip-flop U15 and the output of the inverter U2, and supplies an H level signal to the switch SW2 when both outputs are at the H level. Switch SW2 becomes conductive when the signal received from AND circuit U17 is at the H level.

  By providing the AND circuits U16 and U17, only when the high potential side switching element Q5 is switched between the on state and the off state in response to the pulse signals PLS1 and PLS2, and only when the potential of the virtual ground node VS is increased. Since the constant current sources I1 and I2 are operated, the power consumption of the drive circuit can be reduced. Other points in FIG. 11 are the same as those in FIG. 8, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 12 is a timing chart showing the operation of the drive circuit HVICd of FIG. In FIG. 12, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, U4, voltage waveforms of inverted output terminal (QB) and output terminal (Q) of RS flip-flop U15, ON / OFF of switches SW2, SW1 The OFF state, the voltage waveforms of the reset terminal (R) and the set terminal (S) of the RS flip-flop U15 and the voltage waveform of the signal output node HO of the drive circuit HVICd are shown.

  In FIG. 12, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVICd becomes L level, and the switch SW1 of the constant current supply unit CS1b is turned off. The switch SW2 of the constant current supply unit CS2b is turned off because the output of the inverter U2 is L level.

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, since the switches SW1 and SW2 are in the OFF state, current supply by the constant current sources I1 and I2 is not performed. Therefore, if the resistance values of the resistance elements R1 and R2 are equal to the resistance values of the resistance elements R3 and R4 and the parasitic capacitances of the NMOS transistors Q1 and Q2 are equal to each other, the potential of the node ND1 (ON signal Son) and the node The potential of ND3 (off signal Soff) decreases at the same speed, and the potential of node ND2 (mask signal Mon) and the potential of node ND4 (mask signal Moff) decrease at the same speed.

  At the next time t2, since the mask signals Mon and Moff become equal to or lower than the threshold value TH, the outputs of the inverters U2 and U3 are switched to the H level. Since the inverting output terminal (QB) of the RS flip-flop U15 is at the H level and the output of the inverter U2 is at the H level, the switch SW2 is turned on. As a result, the charging current is supplied from the constant current source I2 to the off-signal NMOS transistor Q2 via the resistor element R4, so that the off signal Soff and the mask signal Moff become the on signal Son and the mask signal Mon after time t2. Compared to a faster decline.

  At the next time t3, the off signal Soff becomes equal to or lower than the threshold value TH, so that the output of the inverter U1 is switched to the H level. Since the mask signal Mon is already below the threshold value TH, the input of the reset terminal (R) of the RS flip-flop U15 remains at the L level.

  At the next time t4, the ON signal Son becomes equal to or lower than the threshold value TH of the inverter U4, whereby the output of the inverter U4 is switched to the H level. Since the mask signal Moff is already below the threshold value TH, the input of the set terminal (S) of the RS flip-flop U15 remains at the L level.

  At the next time t5, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t6, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

  As described above, even when the potential of the virtual ground node VS of the drive circuit HVICd rises, the signal output node HO maintains the L level, and the drive circuit HVICd can perform a normal operation.

<Embodiment 5>
FIG. 13 is a circuit diagram showing a configuration of a switching element drive circuit HVICe according to the fifth embodiment of the present invention.

  The high voltage circuit unit C2e in FIG. 13 differs from the high voltage circuit unit C2 in FIG. 1 in that threshold value changing units THC1 and THC2 are provided instead of the resistance elements R5 and R6 and the switches SW1 and SW2 in FIG. .

  Specifically, the threshold changing unit THC1 includes an NMOS transistor Q9 provided between the output node of the inverter U3 and the virtual ground node VS, and an NMOS provided between the output node of the inverter U4 and the virtual ground node VS. Transistor Q10. The gates of the NMOS transistors Q9 and Q10 are connected to the inverting output terminal (QB) of the RS flip-flop U15.

  The threshold changing unit THC2 includes an NMOS transistor Q7 provided between the output node of the inverter U1 and the virtual ground node VS, and an NMOS transistor Q8 provided between the output node of the inverter U2 and the virtual ground node VS. Including. The gates of the NMOS transistors Q7 and Q8 are connected to the output terminal (Q) of the RS flip-flop U15.

  In FIG. 13, inverters U1 to U4 are CMOS inverters. That is, a PMOS transistor is provided between the output node of each inverter and the power supply node VB, and an NMOS transistor is provided between the output node of each inverter and the virtual ground node VS. The gates of these PMOS and NMOS transistors are connected to corresponding nodes among nodes ND1 to ND4.

  In each of inverters U1-U4, when the corresponding NMOS transistors (Q7-Q10) connected to the output node are on, the output does not change to the H level unless the input signal level is sufficiently lowered. That is, when the corresponding NMOS transistor connected to the output node is on, the threshold value of the inverter is lowered. Therefore, the thresholds of the corresponding inverters U1 to U4 can be controlled by controlling on / off of the NMOS transistors Q7 to Q10, respectively.

  The other points in FIG. 13 are the same as those in FIG. 1, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In FIG. 13, each of the resistance elements R1 to R4 can be replaced with a plurality of resistance elements connected in series and / or in parallel. In this specification, the case where there is one resistance element and the case where there are a plurality of resistance elements are referred to as a resistance portion.

  FIG. 14 is a timing chart showing the operation of the drive circuit HVICe of FIG. In FIG. 14, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, and U4, inverted output terminal (QB), output terminal (Q), reset terminal (R), and set terminal (S) of RS flip-flop U15 ) And the voltage waveform of the signal output node HO of the drive circuit HVICe are shown.

  In FIG. 14, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVICe becomes L level, the NMOS transistors Q9 and Q10 of the threshold changing unit THC1 are turned on, and the NMOS transistors Q7 and Q8 of the threshold changing unit THC2 are turned off. As a result, the threshold value TH2 of the inverters U3 and U4 is lower than the threshold value TH1 of the inverters U1 and U2.

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, if the resistance values of the resistance elements R1 and R2 are equal to the resistance values of the resistance elements R3 and R4 and the parasitic capacitances of the NMOS transistors Q1 and Q2 are equal to each other, the potential of the node ND1 (ON signal Son) The potential of the node ND3 (off signal Soff) decreases at the same speed, and the potential of the node ND2 (mask signal Mon) and the potential of the node ND4 (mask signal Moff) decrease at the same speed.

  At the next time t2, since the mask signal Moff becomes equal to or lower than the threshold value TH1 of the inverter U2, the output of the inverter U2 is switched to the H level.

  At the next time t3, the off signal Soff becomes equal to or lower than the threshold value TH1 of the inverter U1, so that the output of the inverter U1 is switched to the H level. As a result, the input signal of the reset terminal (R) of the RS flip-flop U15 is switched to the H level. Since the RS flip-flop U15 has already been reset, the output terminal Q and the inverted output terminal QB remain at the L level and the H level, respectively, and do not change.

  At the next time t4, since the mask signal Mon becomes equal to or lower than the threshold value TH2 of the inverter U3, the output of the inverter U3 is switched to the H level. As a result, the off signal Soff is masked, so that the input signal of the reset terminal (R) of the RS flip-flop U15 is switched to the L level.

  At the next time t5, since the ON signal Son becomes equal to or lower than the threshold value TH2 of the inverter U4, the output of the inverter U4 is switched to the H level.

  At the next time t5, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t6, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

  As described above, even when the potential of the virtual ground node VS of the drive circuit HVICe increases, the signal output node HO maintains the L level, and the drive circuit HVICe can perform a normal operation.

  In the drive circuits HVIC and HVICb of the first and second embodiments, the resistance parts RP1 and RP2 whose resistance values change are provided as load resistances of the NMOS transistors Q1 and Q2. When the resistance value of the load resistance is changed in this way, the potential difference between the on signal Son and the off signal Soff or the mask signals Mon, Moff depends on the potential change rate (dV / dt) of the virtual ground node VS. The potential difference between them changes. On the other hand, in the case of the fifth embodiment, since the threshold value compared with the on signal Son, the off signal Soff, and the mask signals Mon and Moff is changed, the timing at which the outputs of the inverters U1 to U4 are switched is changed. Control can be performed without depending on the change rate (dV / dt) of the potential of the virtual ground node VS. Therefore, in the case of the fifth embodiment, the design is easier than in the case of the first and second embodiments, and a drive circuit with higher reliability can be realized.

<Embodiment 6>
FIG. 15 is a circuit diagram showing a configuration of a switching element drive circuit HVICf according to the sixth embodiment of the present invention.

  Threshold change unit THC1b provided in high voltage circuit unit C2f in FIG. 15 differs from threshold change unit THC1 in FIG. 13 in that it further includes AND circuit U16. The AND circuit U16 receives the output of the inverting output terminal (QB) of the RS flip-flop U15 and the output of the inverter U2, and outputs an H level signal to the gates of the NMOS transistors Q9 and Q10 when both outputs are at the H level. To do.

  The threshold changing unit THC2b provided in the high voltage circuit unit C2f of FIG. 15 is different from the threshold changing unit THC2 of FIG. 13 in that it further includes an AND circuit U17. The AND circuit U17 receives the output of the output terminal (Q) of the RS flip-flop U15 and the output of the inverter U3, and outputs an H level signal to the gates of the NMOS transistors Q7 and Q8 when both outputs are at the H level. . Other points in FIG. 15 are the same as those in FIG. 13, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 16 is a timing chart showing the operation of the drive circuit HVICe of FIG. 13 and the operation of the drive circuit HVICf of FIG. The graph on the left side of FIG. 16 shows the voltage waveform of each part of the drive circuit HVICe (Embodiment 5) when the high potential side switching element Q5 is turned on. The graph on the right side of FIG. 16 shows the voltage waveform of each part of the drive circuit HVICf (sixth embodiment) in the same case. In the left and right graphs, the voltage waveforms of the input signal IN and the output pulse signals PLS1 and PLS2 of the one-shot pulse generation circuit C1, the on signal Son, the mask signal Mon, the off signal Soff, and the mask signal Moff are sequentially shown from the top. Voltage waveforms, output voltage waveforms of the inverters U3, U4, U2 and U1, voltage waveforms of the output terminal (Q) and the inverted output terminal (QB) of the RS flip-flop U15, on / off states of the NMOS transistors Q7 and Q8, The on / off states of the NMOS transistors Q9 and Q10, the voltage waveforms of the RS flip-flop U15, the set terminal (S) and the reset terminal (R), and the voltage waveform of the signal output node HO of the drive circuits HVICe and HVICf are shown. .

  First, the case of the drive circuit HVICe according to the fifth embodiment will be described with reference to the graphs on the left side of FIGS. In this case, in the initial state, the input signal IN of the one-shot pulse generation circuit C1 is at L level. At this time, since the RS flip-flop U15 is in a reset state, the output terminal (Q) is at the L level and the inverted output terminal (QB) is at the H level. In the case of the drive circuit HVICe in FIG. 13, since the NMOS transistors Q9 and Q10 are on, the threshold value TH2 of the inverters U3 and U4 is lower than the threshold value TH1 of the inverters U1 and U2.

  When the input signal IN is switched to the H level at time t1, the one-shot pulse generation circuit C1 outputs a pulse signal PLS1 (pulse width from time t1 to time t4). As a result, the potentials (Son, Mon) of the nodes ND1, ND2 are lowered.

  At the next time t2, since the potential of the node ND2 (mask signal Mon) becomes equal to or lower than the threshold value TH2 of the inverter U3, the output of the inverter U3 is switched to the H level.

  At the next time t3, since the potential of the node ND1 (ON signal Son) becomes equal to or lower than the threshold value TH2 of the inverter U4, the output of the inverter U4 is switched to the H level. As a result, the input of the set terminal (S) of the RS flip-flop U15 becomes H level, so that the output terminal (Q) of the RS flip-flop U15 is switched to H level and the inverting output terminal (QB) is switched to L level. Instead, the signal output node HO of the drive circuit HVICe is switched to the H level. Further, the NMOS transistors Q7 and Q8 are turned on and the NMOS transistors Q9 and Q10 are turned off in accordance with the voltage change of the output terminal (Q) and the inverted output terminal (QB) of the RS flip-flop U15.

  At the next time t4, the gate input (PLS1) of the NMOS transistor Q1 returns to 0V, so that the potentials (Son, Mon) of the nodes ND1, ND2 return to the original potential (the potential of the power supply node VB). As a result, the outputs of the inverters U3 and U4 are switched to the L level, and the input to the set terminal (S) to the RS flip-flop U15 returns to the L level.

Next, the case of the drive circuit HVICf according to the sixth embodiment will be described with reference to the graphs on the right side of FIGS. 15 and 16. In this case, in the initial state, it is the same as the left graph except that the NMOS transistors Q9 and Q10 are in the off state. Since the NMOS transistors Q9 and Q10 are controlled by the output of the inverting output terminal (QB) of the RS flip-flop U15 and the output of the inverter U2, the inverting output terminal (QB) is at the H level in the initial state. Since it is at the L level, the NMOS transistors Q9 and Q10 are in the off state. As a result, the threshold value of the inverters U3 and U4 is TH1, and has not decreased to TH2.

  When the input signal IN is switched to the H level at time t11, the pulse signal PLS1 (pulse width is from time t11 to time t14) is output from the one-shot pulse generation circuit C1. As a result, the potentials (Son, Mon) of the nodes ND1, ND2 are lowered.

  At the next time t12, the potential of the node ND2 (mask signal Mon) becomes equal to or lower than the threshold value TH1 of the inverter U3 (however, TH1> TH2), so that the output of the inverter U3 is switched to the H level.

  At the next time t13, since the potential of the node ND1 (ON signal Son) becomes equal to or lower than the threshold value TH1 of the inverter U4, the output of the inverter U4 is switched to the H level. As a result, the input of the set terminal (S) of the RS flip-flop U15 becomes H level, so that the output terminal (Q) of the RS flip-flop U15 is switched to H level and the inverting output terminal (QB) is switched to L level. Instead, the signal output node HO of the drive circuit HVICf is switched to the H level. At this time, since the output of the inverter U3 is at the H level, the NMOS transistors Q7 and Q8 are turned on.

  At the next time t14, the gate input (PLS1) of the NMOS transistor Q1 returns to 0V, so that the potentials (Son, Mon) of the nodes ND1, ND2 return to the original potential (the potential of the power supply node VB). As a result, the outputs of the inverters U3 and U4 are switched to the L level, the input to the set terminal (S) to the RS flip-flop U15 returns to the L level, and the transistors Q7 and Q8 are turned off.

  The pulse width of the signal input to the set terminal (S) of the RS flip-flop U15 is set to the case of the fifth embodiment (from time t3 to time t4) and the case of the sixth embodiment (from time t13 to time t14). Compare Then, the pulse width (from time t13 to time t14) in the sixth embodiment is longer than the pulse width (from time t3 to time t4) in the fifth embodiment. As a result, the noise tolerance in the case of the sixth embodiment is improved as compared with the case of the fifth embodiment.

FIG. 17 is a timing chart when the low potential side switching element Q6 is turned off in the drive circuit HVICf of FIG.
In FIG. 17, in order from the top, the waveform (LO) of the gate drive signal of the low potential side switching element Q6, the voltage change of the virtual ground node VS (power supply node VB), the on signal Son, the mask signal Mon, the off signal Soff, Voltage waveform of mask signal Moff, output voltage waveforms of inverters U2, U1, U3, U4, voltage waveforms of inverted output terminal (QB) and output terminal (Q) of RS flip-flop U15, NMOS transistors Q9, Q10 being turned on / Off state, NMOS transistors Q7 and Q8 on / off state, voltage waveforms of reset terminal (R) and set terminal (S) of RS flip-flop U15 and voltage waveform of signal output node HO of drive circuit HVICf Indicated.

  In FIG. 17, in the initial state, the RS flip-flop U15 is in a reset state, its output terminal (Q) is at L level, and its inverted output terminal (QB) is at H level. As a result, the signal output node HO of the drive circuit HVICf becomes L level. Since the outputs of inverters U2 and U3 are at the L level, all of NMOS transistors Q7 to Q10 are turned off. The threshold values of the inverters U1 to U4 are relatively high TH1 (TH1> TH2).

  At time t1, the signal output node LO of the gate driving circuit for the low potential side switching element Q6 is switched from the H level to the L level. As a result, the potential of the virtual ground node VS rises according to the switching speed of the low potential side switching element Q6, so that the junction capacitance (parasitic capacitance) between the drains of the NMOS transistors Q1 and Q2 and the substrate is charged. At this time, if the resistance values of the resistance elements R1 and R2 are equal to the resistance values of the resistance elements R3 and R4 and the parasitic capacitances of the NMOS transistors Q1 and Q2 are equal to each other, the potential of the node ND1 (ON signal Son) The potential of the node ND3 (off signal Soff) decreases at the same speed, and the potential of the node ND2 (mask signal Mon) and the potential of the node ND4 (mask signal Moff) decrease at the same speed.

  At the next time t2, since the mask signal Moff becomes equal to or lower than the threshold value TH1 of the inverter U2, the output of the inverter U2 is switched to the H level. As a result, the NMOS transistors Q9 and Q10 are turned on, and the threshold values of the inverters U3 and U4 are lowered from TH1 to TH2.

  At the next time t3, the off signal Soff becomes equal to or lower than the threshold value TH1 of the inverter U1, so that the output of the inverter U1 is switched to the H level. As a result, the input signal of the reset terminal (R) of the RS flip-flop U15 is switched to the H level. Since the RS flip-flop U15 has already been reset, the output terminal Q and the inverted output terminal QB remain at the L level and the H level, respectively, and do not change.

  At the next time t4, since the mask signal Mon becomes equal to or lower than the threshold value TH2 of the inverter U3, the output of the inverter U3 is switched to the H level. As a result, the off signal Soff is masked, so that the input signal of the reset terminal (R) of the RS flip-flop U15 is switched to the L level.

  At the next time t5, since the ON signal Son becomes equal to or lower than the threshold value TH2 of the inverter U4, the output of the inverter U4 is switched to the H level.

  At the next time t5, the diodes D1 and D2 are turned on, and the potentials (Son, Mon, Soff, Moff) of the nodes ND1 to ND4 are clamped to a constant value. Since the potential rise of the virtual ground node VS becomes 0 at the next time t6, the potentials of the nodes ND1 to ND4 (Son, Soff, Mon, Moff) return to the original potential (the potential of the power supply node VB).

  As described above, even when the potential of the virtual ground node VS of the drive circuit HVICf increases, the signal output node HO maintains the L level, and the drive circuit HVICf can perform a normal operation.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  C1 one-shot pulse generation circuit, CS1, CS2, CS1b, CS2b constant current supply unit, GND ground node, HO signal output node (high potential side), HV high voltage power supply, HVIC, HVICb to HVICf drive circuit, HVN high potential side Power supply node, I1, I2 constant current source, LO signal output node (low potential side), Moff, Mon mask signal, ND1-ND4 node, PLS1, PLS2 pulse signal, Q1, Q2 NMOS transistor (control switching element), Q5 High-potential side switching element, Q6 Low-potential side switching element, R1-R6 resistance element, RP1-RP4, RP1b, RP2b resistance section, SW1, SW2 switch, Soff off signal, Son on signal, TH, TH1, TH2 threshold, THC1 , THC2, THC1 , THC2b threshold changing unit, U15 flip-flop, V1 DC power supply, VB power supply node, VS virtual ground node.

Claims (15)

A driving circuit for a switching element on a high potential side of two switching elements connected in series between a first power supply node and a second power supply node set at a higher potential than the first power supply node,
A third power supply node set to a potential higher than the potential of the connection node of the two switching elements;
In order to switch the high-potential side switching element to an on state or an off state according to the internal state, the first state and the second state correspond to the first state and the second state, respectively. A logic circuit for outputting a control signal for switching to the first and second logic levels;
A first resistance unit provided between the third power supply node and the first node;
A second resistance portion provided between the first node and the second node;
A first switching element for control provided between the second node and the first power supply node and conducting when receiving a first pulse signal;
In order to switch the logic circuit from the first state to the second state in response to the first pulse signal, the logic circuit is activated when the potential of the first node is equal to or lower than a first threshold value. A first comparator that outputs a signal of 1;
The switching element drive circuit, wherein a resistance value of at least one of the first and second resistance units changes at a timing based on a change of at least the control signal. A third resistance portion provided between the third power supply node and the third node;
A fourth resistance unit provided between the third node and the fourth node;
A second switching element for control provided between the fourth node and the first power supply node and conducting when receiving a second pulse signal having a timing different from that of the first pulse signal;
In order to switch the logic circuit from the second state to the first state in response to the second pulse signal, the logic circuit is activated when the potential of the third node is equal to or lower than a second threshold value. A second comparator that outputs a signal of 2;
A third comparison unit that outputs a third signal that is activated when the potential of the fourth node is equal to or lower than a third threshold;
The resistance value of at least one of the first and second resistance units is such that when the control signal is at the first logic level and the third signal is in an active state, the control signal is the second resistance value. 2. The switching element drive circuit according to claim 1, wherein a ratio of a resistance value of the second resistor unit to a resistance value of the first resistor unit is increased as compared with a case of a logic level.   The resistance value of at least one of the first and second resistance units is greater than the first resistance value when the control signal is at the first logic level compared to when the control signal is at the second logic level. The switching element drive circuit according to claim 1, wherein the ratio of the resistance value of the second resistance part to the resistance value of the resistance part changes so as to increase. The first resistance portion is
A first resistance element provided between the third power supply node and the first node;
A second resistance element provided in parallel with the first resistance element between the third power supply node and the first node;
Provided in series with the second resistance element between the third power supply node and the first node, the control signal is at the first logic level, and the third signal is in an active state. The switching element drive circuit according to claim 2, further comprising a third control switching element that conducts in some cases. The first resistance portion is
A first resistance element provided between the third power supply node and the first node;
A second resistance element provided in parallel with the first resistance element between the third power supply node and the first node;
A third control switching element provided in series with the second resistance element between the third power supply node and the first node and conducting when the control signal is at the first logic level. The drive circuit of the switching element of Claim 3 containing these. A driving circuit for a switching element on a high potential side of two switching elements connected in series between a first power supply node and a second power supply node set at a higher potential than the first power supply node,
A third power supply node set to a potential higher than the potential of the connection node of the two switching elements;
In order to switch the high-potential side switching element to an on state or an off state according to the internal state, the first state and the second state correspond to the first state and the second state, respectively. Logic circuits for outputting control signals for switching to the first and second logic levels,
A first resistance unit provided between the third power supply node and the first node;
A second resistance portion provided between the first node and the second node;
A first switching element for control provided between the second node and the first power supply node and conducting when receiving a first pulse signal;
In order to switch the logic circuit from the first state to the second state in response to the first pulse signal, the logic circuit is activated when the potential of the first node is equal to or lower than a first threshold value. A first comparator that outputs a signal of 1;
A constant current capable of supplying a constant current to the first control switching element via at least one of the one or more resistance elements constituting the second resistance unit at a timing based on at least the change of the control signal. A switching element drive circuit comprising a current supply unit. A second comparison unit that outputs a second signal that is activated when the potential of the second node is equal to or lower than a second threshold;
The constant current supply unit includes at least one of one or more resistance elements constituting the second resistance unit when the control signal is at the second logic level and the second signal is in an active state. The switching element drive circuit according to claim 6, wherein a constant current can be supplied to the first control switching element via a switch.   When the control signal is at the second logic level, the constant current supply unit is configured to switch the first control switching via at least one of one or a plurality of resistance elements constituting the second resistance unit. The switching element drive circuit according to claim 6, wherein a constant current can be supplied to the element. The constant current supply unit is
A constant current source provided in parallel with the first resistor between the third power supply node and the first node;
Provided in series with the constant current source between the constant current source and the first node, and conducts when the control signal is at the second logic level and the second signal is in an active state. The switching element drive circuit according to claim 7, further comprising a second control switching element. The constant current supply unit is
A constant current source provided in parallel with the first resistor between the third power supply node and the first node;
A second control switching element provided in series with the constant current source between the constant current source and the first node and conducting when the control signal is at the second logic level; The drive circuit of the switching element according to claim 8. A driving circuit for a switching element on a high potential side of two switching elements connected in series between a first power supply node and a second power supply node set at a higher potential than the first power supply node,
A third power supply node set to a potential higher than the potential of the connection node of the two switching elements;
In order to switch the high-potential side switching element to an on state or an off state according to the internal state, the first state and the second state correspond to the first state and the second state, respectively. A first logic circuit for outputting a control signal for switching to the first and second logic levels,
A first resistance unit provided between the third power supply node and the first node;
A first switching element for control provided between the first node and the first power supply node and conducting when receiving a first pulse signal;
In order to switch the first logic circuit from the first state to the second state in response to the first pulse signal, the active state is obtained when the potential of the first node is equal to or lower than a first threshold value. A first comparator that outputs a first signal,
A switching element drive circuit comprising: a threshold value changing unit that changes the magnitude of the first threshold value at least based on a change in the control signal. A second resistance portion provided between the third power supply node and the second node;
A third resistance portion provided between the second node and the third node;
A second switching element for control provided between the third node and the first power supply node and conducting when receiving a second pulse signal having a timing different from that of the first pulse signal;
In order to switch the first logic circuit from the second state to the first state in response to the second pulse signal, the active state is obtained when the potential of the second node is equal to or lower than a second threshold value. A second comparison unit that outputs a second signal to be
A third comparison unit that outputs a third signal that is activated when the potential of the third node is equal to or lower than a third threshold;
The threshold value changing unit may be configured such that when the control signal is at the first logic level and the third signal is in an active state, the control signal is at the first logic level compared to when the control signal is at the second logic level. The switching element driving circuit according to claim 11, wherein the threshold value is decreased.   The threshold value changing unit reduces the magnitude of the first threshold value when the control signal is at the first logic level compared to when the control signal is at the second logic level. A switching element driving circuit according to claim 1. The first comparison unit is a MOS inverter that operates with a voltage supplied between the third power supply node and the connection node;
The threshold value changing unit is
A MOS transistor provided between the output node of the first comparator and the connection node;
A second logic circuit for supplying a signal for turning on the MOS transistor to the gate of the MOS transistor when the control signal is at the first logic level and the third signal is in an active state; The switching element drive circuit according to claim 12, further comprising: The first comparison unit is a MOS inverter that operates with a voltage supplied between the third power supply node and the connection node;
The threshold change unit includes a MOS transistor that is provided between an output node of the first comparison unit and the connection node, and is turned on when the control signal is at the first logic level. 14. A drive circuit for a switching element according to item 13.

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