JP2006340579A - Gate circuit of insulating gate semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate circuit of insulating gate type semiconductor element which can shorten the turn-off time of the semiconductor element. <P>SOLUTION: In order to drive the insulating gate semiconductor element 10, two sets of serially connected units, in which semiconductor elements 1, 2 and 3, 4 are connected in a totem pole connection, are provided. Positive and negative power sources are connected to anodes via resistors 5, 6, 7 and 8, The mid-point of the elements 1, 2 is connected via a resistor 11 and the mid-point of the elements 3, 4 is connected directly to the gate of the semiconductor element 10 so that a switching signal is delayed by delay circuits 13, 14 and is supplied to the elements 3, 4. A switching element 17 is provided, in parallel with the resistor 5, and the switching element 17 is controlled on or off by an output signal of a one-shot signal generator circuit 18 to early charge in the semiconductor element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gate circuit of an insulated gate semiconductor element.

  Insulated gate semiconductor elements having a MOS gate structure include, for example, MOSFETs, IGBTs, and IEGTs (Injection Enhanced Gate Transistors).

  These insulated gate type semiconductor devices are of voltage drive type, and the current for charging and discharging the capacitance between the gate and the emitter flows for a short time when switching on and off, and the gate current does not flow in a steady state. Therefore, there is an advantage that the gate power of the insulated gate semiconductor element can be made very small as compared with the bipolar element. Further, the insulated gate semiconductor element can operate at a high speed peculiar to the MOS gate structure.

  For these reasons, in recent years, this type of voltage-driven semiconductor element has been developed, and an insulated gate semiconductor element having a high voltage and large current (for example, 4.5 kV-5000 A class) has been developed and applied to a power converter. Is expanding.

  However, the capacitance of the insulated gate semiconductor element has increased with the increase in voltage and current, respectively, between the collector and emitter, between the collector and gate, and between the gate and emitter. In particular, the trench type has a gate-emitter capacitance larger than that of the conventional planar type due to its gate structure, and may be about 1.5 to 2 times.

  In the insulated gate semiconductor device, the gate-collector voltage becomes a constant voltage due to the capacitance characteristic between the gate and the emitter at the time of gate turn-on and turn-off transitions, and a so-called mirror voltage time during which the control becomes impossible appears. In particular, at the time of turn-on, the mirror voltage time tends to be longer as the high breakdown voltage element. This is particularly because the gate-emitter capacitance depends on the collector-emitter voltage, and the gate-emitter capacitance increases when the collector-emitter voltage decreases due to turn-on.

  In a PWM (pulse width modulation) inverter, it is desirable to increase the switching frequency in order to make the load current closer to a sine wave. However, the above-mentioned mirror time causes restrictions on the minimum on-time and dead time, resulting in an upper limit frequency. Will be limited.

  This mirror time can be shortened by reducing the gate resistance. However, when the gate resistance is reduced, the switching characteristics of the insulated gate semiconductor device are also accelerated, and the current rises sharply (dI / dt) at turn-on, and at turn-off. Since the voltage rises steeply (dV / dt), the device is damaged by such a rapid change in current and voltage, EMI noise increases, or the load side is adversely affected.

  In order to prevent such adverse effects as described above, a dead time is provided in the gate signal during turn-on and turn-off to prevent the upper and lower arms from being short-circuited.

  However, when the insulated gate semiconductor device of the opposite arm is turned on or turned off, the gate voltage is increased by charging or discharging the capacitance between the gate and the emitter due to a sudden change in current (dI / dt) or a sudden change in voltage (dV / dt). Has been confirmed to lift in the positive or negative direction.

  In order to prevent the above phenomenon, it is effective to provide a capacitor between the gate and the emitter. However, if a capacitor is provided, the switching time of the insulated gate semiconductor element is delayed, resulting in an increase in switching loss. To do.

  A gate circuit of an insulated gate semiconductor element for solving the problems as described above is proposed in Patent Document 1.

In order to drive an insulated gate semiconductor device, the gate circuit of the insulated gate semiconductor device described in Patent Document 1 is provided with two sets of serially connected bodies each having a semiconductor element connected to a totem pole, and each of the anode and the cathode is connected to each of the anode and cathode. A positive and negative power source is connected via a resistor, a midpoint of the first set of semiconductor elements is connected via a resistor, and a midpoint of the second set of semiconductor elements is directly connected to the gate of the insulated gate semiconductor element. The switching signal is supplied to the semiconductor element after being delayed by a delay circuit, and the switching element is provided in parallel with the resistor connected in series to the negative side semiconductor element of the first set of serially connected bodies. By controlling on / off by the output signal of the signal generating circuit, the charge charged in the insulated gate semiconductor element at the time of turn-off can be discharged quickly. .
JP 2004-88892 A (page 3-4, FIG. 1)

  In particular, the trench type semiconductor device has a gate-emitter capacitance larger than that of the conventional planar type due to its gate structure, which may be about 1.5 to 2 times.

  The technology described in Patent Document 1 has made it possible to solve various problems up to now. However, as described above, the gate capacitance of a trench gate type insulated gate semiconductor device has a planar gate as described above. Since it increases about 1.5 to 2 times that of the insulated gate semiconductor element, the mirror time at turn-on tends to be further extended, that is, the turn-on time tends to be extended.

  For this reason, in recent insulated gate type semiconductor devices, it is necessary to increase the dead time between the upper and lower arm devices.

  There is a correlation between the gate resistance and the turn-on time, and reducing the gate resistance value is effective for shortening the turn-on time. However, when the gate resistance value is lowered, in the case of a trench gate type insulated gate semiconductor device, the switching characteristic is faster than that of the planar type, and the voltage drop (−dV / dt) at turn-on becomes steeper, and the collector Concerned about damage to semiconductor elements due to increased current rise (dI / dt), damage to diode elements connected in reverse parallel to insulated gate semiconductor elements due to increased surge voltage, induction of EMI noise, and adverse effects on loads Is done.

  Therefore, it has been desired to improve the gate circuit so that the turn-on time can be shortened without increasing -dV / dt or dI / dt.

  The present invention has been made in view of the above problems, and provides a gate circuit for an insulated gate semiconductor device capable of further reducing the turn-on time of the insulated gate semiconductor device without adversely affecting the device. Objective.

  In order to achieve the above object, the gate circuit of the insulated gate semiconductor device according to the first aspect of the present invention has one end connected to the positive power supply, and the first semiconductor control device and the first resistor connected in series. And a second semiconductor control element having one end connected to the other end of the first series circuit and the other end connected to a negative power source, and having a polarity opposite to that of the first semiconductor control element And a second series circuit formed by connecting a second resistor in series, one end connected to the positive power supply, the other end connected to the gate of an insulated gate semiconductor element, and the same polarity as the first semiconductor control element A third series control circuit comprising a third semiconductor control element and a third resistor connected in series, one end connected to the other end of the third series circuit and the other end connected to the negative power source, A fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. 4, a fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element, and the first resistor connected to each other. A switching signal source for supplying a switching signal to the control pole of the semiconductor control element and the control pole of the second semiconductor control element via a sixth resistor, the third semiconductor control element, and the fourth semiconductor control Two delay circuits for supplying a switching signal from the switching signal source to each control pole of the element with a predetermined time delay respectively, a switching element provided in parallel with the first resistor, and the switching element And a control means for on / off control.

  The gate circuit of the insulated gate semiconductor device according to the second invention of the present invention is a first circuit in which one end is connected to a positive power source and a first semiconductor control device and a first resistor are connected in series. A series circuit, one end connected to the other end of the first series circuit, the other end connected to a negative power source, a second semiconductor control element and a second resistor having a polarity opposite to that of the first semiconductor control element And a third semiconductor circuit having one end connected to the positive power source and the other end connected to the gate of the insulated gate semiconductor element, and having the same polarity as the first semiconductor control element A third series circuit comprising a control element and a third resistor connected in series; one end connected to the other end of the third series circuit; the other end connected to the negative power supply; and the third semiconductor control A fourth series circuit comprising a fourth semiconductor control element having a polarity opposite to that of the element and a fourth resistor connected in series; The fifth resistor connected between the connection point of the first series circuit and the second series circuit and the gate of the insulated gate semiconductor element, and the control of the first semiconductor control element connected to each other A switching signal source for supplying a switching signal to a control pole of the second semiconductor control element via a sixth resistor, and control poles of the third semiconductor control element and the fourth semiconductor control element, respectively. In addition, two delay circuits for supplying a switching signal from the switching signal source with a predetermined time delay, respectively, and a capacitance greater than the gate capacitance of the insulated gate semiconductor element are provided in parallel with the first resistor. It is characterized by having a capacitor.

The gate circuit of the insulated gate semiconductor element according to the third aspect of the present invention is:
One end connected to the positive power source, a first series circuit formed by connecting a first semiconductor control element and a first resistor in series, one end to the other end of the first series circuit, and the other end to negative A second series circuit formed by connecting a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor in series, and one end of the second power supply A third series circuit having the other end connected to the gate of the insulated gate semiconductor element, a third semiconductor control element having the same polarity as the first semiconductor control element, and a third resistor connected in series; Is connected to the other end of the third series circuit, the other end is connected to the negative power source, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. And a connection point between the first series circuit and the second series circuit and the insulated gate semiconductor. A fifth resistor connected between the gates of the element, and a switching signal via a sixth resistor to the control pole of the first semiconductor control element and the control pole of the second semiconductor control element connected to each other And a switching signal source for supplying a switching signal from the switching signal source to each control pole of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay respectively. A second delay circuit, a one-shot signal generation means triggered by an ON command signal output from the switching signal source, a logical sum of the output of the one-shot signal generation means and the output of the first delay circuit; And a logical sum generation means for giving to the control pole of the third semiconductor control element.

The gate circuit of the insulated gate semiconductor device according to the fourth aspect of the present invention is:
One end connected to the positive power source, a first series circuit formed by connecting a first semiconductor control element and a first resistor in series, one end to the other end of the first series circuit, and the other end to negative A second series circuit formed by connecting a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor in series, and one end of the second power supply A third series circuit having the other end connected to the gate of the insulated gate semiconductor element, a third semiconductor control element having the same polarity as the first semiconductor control element, and a third resistor connected in series; Is connected to the other end of the third series circuit, the other end is connected to the negative power source, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. And a connection point between the first series circuit and the second series circuit and the insulated gate semiconductor. A fifth resistor connected between the gates of the element, and a switching signal via a sixth resistor to the control pole of the first semiconductor control element and the control pole of the second semiconductor control element connected to each other A switching signal source for supplying the switching signal, and two delays for supplying the switching signal from the switching signal source to the control poles of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively. A circuit, a positive addition power supply connected in series in the positive direction of the positive power supply, and a voltage addition connected from the positive electrode of the positive addition power supply to the positive power supply via a third diode A switching element, and the voltage adding switching element is turned on by a one-shot signal triggered by an on command signal output from the switching signal source. It is set to.

  Further, the gate circuit of the insulated gate semiconductor device according to the fifth aspect of the present invention is a first circuit in which one end is connected to a positive power source and a first semiconductor control element and a first resistor are connected in series. A series circuit, one end connected to the other end of the first series circuit, the other end connected to a negative power source, a second semiconductor control element and a second resistor having a polarity opposite to that of the first semiconductor control element And a third semiconductor circuit having one end connected to the positive power source and the other end connected to the gate of the insulated gate semiconductor element, and having the same polarity as the first semiconductor control element A third series circuit comprising a control element and a third resistor connected in series; one end connected to the other end of the third series circuit; the other end connected to the negative power supply; and the third semiconductor control A fourth series circuit comprising a fourth semiconductor control element having a polarity opposite to that of the element and a fourth resistor connected in series; The fifth resistor connected between the connection point of the first series circuit and the second series circuit and the gate of the insulated gate semiconductor element, and the control of the first semiconductor control element connected to each other A switching signal source for supplying a switching signal via a sixth resistor to the pole and the control pole of the second semiconductor control element, one end connected to the positive power supply, and the other end connected to the gate of the insulated gate semiconductor element A fifth series circuit comprising a fifth semiconductor control element having the same polarity as the first semiconductor control element and a seventh resistor connected in series, the third semiconductor control element and the fourth semiconductor Each control pole of the control element is provided with two delay circuits for supplying a switching signal from the switching signal source with a predetermined time delay, respectively, and triggered by an ON command signal output from the switching signal source. It is characterized in that so as to turn on the fifth semiconductor control element by Tsu preparative signal.

  According to the present invention, since the mirror time of the insulated gate semiconductor device can be shortened without adversely affecting the gate of the insulated gate semiconductor device, the turn-on time of the insulated gate semiconductor device can be further shortened. A circuit can be provided.

Embodiments of the present invention will be described below with reference to the drawings.

  The gate circuit of the insulated gate semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit configuration diagram of a gate circuit of an insulated gate semiconductor device according to the first embodiment of the present invention.

  An NPN-type semiconductor element (N-channel semiconductor element) 1 which is a semiconductor control element having a control pole and a PNP-type semiconductor element (P-channel semiconductor element) 2 having a polarity opposite to that of the NPN-type semiconductor element 1 are connected in a totem pole connection in series. Thus, a first series connection body is formed. Similarly, the NPN-type semiconductor element 3 and the PNP-type semiconductor element 4 that are totem-pole connected form a second series connection body. Here, the NPN type semiconductor element 1, the PNP type semiconductor element 2, the NPN type semiconductor element 3, and the PNP type semiconductor element 4 are all bipolar transistors.

  The positive side of the first series connection body, that is, the collector of the NPN type semiconductor element 1 is connected to the power source P (positive) via the resistor 5, and the negative side, ie, the collector of the PNP type semiconductor element 2 is connected to the power source via the resistor 6. Connected to N (negative). Similarly, the positive side of the second series connection body, that is, the collector of the NPN semiconductor element 3 is connected to the power source P (positive) through the resistor 7, and the negative side, that is, the collector of the PNP type semiconductor element 4 is connected to the resistor 8. To the power supply N (negative). Further, the midpoint of each of the first series connection body and the second series connection body (the connection point between the NPN type semiconductor element 1 and the PNP type semiconductor element 2 and the connection point between the NPN type semiconductor element 3 and the PNP type semiconductor element 4). ) Are connected to each other, and the middle point of the second series connection body is connected to the gate G of the insulated gate semiconductor element 10 to be driven.

  Here, the resistors 3 and 4 are low-impedance resistors, but in order to stably drive the insulated gate semiconductor element 10 without causing an abnormality such as an oscillation phenomenon, a voltage drop during energization is: It is necessary to select a resistance value so as to be a sufficiently large value with respect to the ON voltage of the NPN type semiconductor element 3 or the PNP type semiconductor element 4.

  Bases that are control poles of the NPN semiconductor element 1 and the PNP semiconductor element 2 constituting the first series connection body are connected to each other, and one end of the resistor 11 is connected thereto.

  The other end of the resistor 11 is connected to an output end of a switching signal source 12 that supplies a switching signal (output signal A).

  The output signal A supplied from the switching signal source 12 is controlled by the respective control poles of the NPN semiconductor element 3 and the PNP semiconductor element 4 constituting the second series connection body via the delay circuits 13 and 14, respectively. Is being supplied to the base.

  A switching element 15 is connected in parallel with the resistor 6 provided in series on the negative side of the first series connection body. Here, the switching element 15 is a so-called switching transistor (hereinafter, the same applies to other switching elements).

  The switching element 15 is driven by an output signal of a one-shot signal generation circuit 16 that supplies a one-shot signal with an off control signal of the output signal A of the switching signal source 12 as a trigger.

  Further, a switching element 17 is connected in parallel with the resistor 5 provided in series on the positive side of the first series connection body. Here, the switching element 17 is also a switching transistor.

  The switching element 17 is driven by an output signal of a one-shot signal generation circuit 18 that supplies a one-shot signal with an ON control signal of the output signal A of the switching signal source 12 as a trigger.

  The operation and effect of the present embodiment will be described below with reference to FIG.

  FIG. 2 is an operation time chart when the insulated gate semiconductor element is driven by the gate circuit shown in FIG.

  First, the ON signal is supplied to the PNP semiconductor element 2 (SW2) and the PNP semiconductor element 4 (SW4) by the output signal A of the switching signal source 12 until time t = t0. At this time, the NPN semiconductor element 1 (SW1) and the NPN semiconductor element 3 (SW3) are off.

  When the output signal A of the switching signal source 12 is inverted to become an ON control signal at time t = t0, an OFF signal is output to the PNP semiconductor element 2 (SW2) and the PNP semiconductor element 4 (SW4), and the NPN semiconductor element 1 (SW1) and the NPN semiconductor element 3 (SW3) are supplied with an ON signal. At the same time, the one-shot signal generation circuit 18 receives the on-control signal and outputs a one-shot signal, and the switching element 17 (SW17) is turned on for a predetermined period.

  As a result, electric charges begin to be charged between the gate and the emitter of the insulated gate semiconductor element 10 through the charging route of the resistor 9, the NPN semiconductor element 1, and the switching element 17.

  The switching element 17 is turned off at time t = t1 before reaching the mirror voltage, and then the above charging is continued through the resistor 5. When the gate-emitter voltage reaches the mirror voltage at time t = t2, the insulated gate semiconductor element 10 is turned on, the collector-emitter voltage (Vce) is lowered, and the collector current (Ic) starts to flow.

  As a result, the arrival time (t2′−t0) until the mirror time when the switching element 17 indicated by the broken line in FIG. 2 is not used is shorter due to the quick charge due to the one-shot effect by the switching element 17. Until reaching time (t2-t0).

  This is due to the following reason. For example, at the time of turn-on, the charge Q to be accumulated in the capacitance between the gate and the emitter of the insulated gate semiconductor element 10 is 20 μcoulomb, and the total value of the resistor 9 and the resistor 5 when the switching element 17 is not used. When the on-gate current determined by 2 is 2 A, it takes about 10 μs to charge the charge Q.

  On the other hand, if the switching element 17 is turned on at the time of turn-on and the on-gate current is caused to flow, for example, by 10 A only by the resistor 9, the charge between the gate and the emitter is charged in 2 μsec because Q = current × time. Will be able to.

  On the other hand, as shown in FIG. 2, the gate voltage (Vge) of the insulated gate semiconductor device 10 continues to have a mirror voltage level until the charging of the gate-emitter capacitance is completed. This time is 20 to 30 μs although it depends on the resistance value of the resistor 9.

  The gate-emitter capacitance is such that the NPN-type semiconductor element 3 (SW3) of the second series connection body is turned on at a time t = t3 after a time set by the delay circuit 13 (for example, 10 μsec), and the low impedance The battery is immediately charged through the resistor 7.

  Thus, by increasing the arrival time to the mirror voltage, the timing of t = t3 at which the ON control of the NPN semiconductor element 3 (SW3) can be performed is advanced from t = t3 ′.

  Next, the gate voltage (Vge) of the insulated gate semiconductor element 10 rises to the level of the positive power supply P, and the insulated gate semiconductor element 10 is stably turned on. In this state, even if the gate voltage is lowered due to disturbance or the like, the gate voltage is maintained without being lowered by the resistor 7 connected in series with the NPN semiconductor element 3 (SW3).

  When the output signal A of the switching signal source 12 is inverted at time t = t4 and becomes an off control signal, the NPN semiconductor elements 1 (SW1) and 3 (SW3) are turned off and the PNP semiconductor element 2 (SW2) is turned on. A signal is given. At the same time, the one-shot signal generation circuit 18 receives the off-control signal and simultaneously outputs the one-shot signal to turn on the switching element 15 (SW15) for a predetermined period.

  As a result, the electric charge charged between the gate and the emitter of the insulated gate semiconductor element 10 starts to be discharged through the discharge route of the resistor 9, the NPN semiconductor element 2 and the switching element 15.

  Then, the switching element 15 is turned off before the mirror time is completed, and the discharge is continued through the resistor 6. The collector-emitter voltage (Vce) starts to rise at time t = t5 after the discharge is completed, and the current is cut off at time t = t6 to complete the turn-off. Thereafter, the PNP semiconductor element 4 (SW4) is turned on by the output signal A of the switching signal source 12 delayed by the delay circuit 14.

  With the above operation, the mirror time (t5′-t4) when the switching element 15 at the time of turn-off indicated by the broken line in FIG. 2 is not used is shorter due to the early discharge by the one-shot by the switching element 15. (T5-t4) and the turn-off time can be shortened.

  For example, the charge Q accumulated in the capacitance between the gate and the emitter of the insulated gate semiconductor element 10 is 20 μcoulomb, and the off-gate current determined by the total value of the resistor 9 and the resistor 6 when the switching element 15 is not used. In the case of 2A, it takes about 10 μsec until the charge Q is extracted.

  On the other hand, if the switching element 15 is turned on at the time of turn-off and only the resistor 9 is applied, for example, an off-gate current of 10 A flows, Q = current × time, so that the charge between the gate and the emitter can be extracted in 2 μsec. Turn-off time is greatly reduced.

  The delay time set by the delay circuit 14 of the gate circuit is set to be equal to or longer than the turn-off time (t6-t4) of the insulated gate semiconductor element 10.

  After this delay time, when the NPN semiconductor element 4 of the second series connection body is turned on, the gate voltage (Vge) of the insulated gate semiconductor element 10 falls to the level of the negative power supply N, and the insulated gate semiconductor element 10 Is in a stable off state. In this state, even if the gate voltage increases due to disturbance or the like, the gate voltage is maintained without increasing by the resistor 8 connected in series with the PNP semiconductor element 4 (SW4).

  FIG. 3 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the second embodiment of the present invention.

  In the second embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the first embodiment of the present invention shown in FIG. The second embodiment is different from the first embodiment in that an N-channel semiconductor element 3A, which is a field effect transistor (MOSFET), and the N-channel semiconductor element 3A are opposite as semiconductor control elements constituting the second series connection body. This is a point using a polar P-channel semiconductor element 4A.

  As described above, even when a MOSFET is used for the second series connection body, the operation is performed when a bipolar transistor is used as the NPN semiconductor element 3 and the PNP semiconductor element 4 as in the first embodiment. Similarly to the above, the turn-on time of the insulated gate semiconductor element 10 can be shortened.

  Although illustration is omitted, it is also possible to use a MOSFET for the first series connection body, and similarly, the turn-on time of the insulated gate semiconductor element 10 can be shortened.

  Although illustration is omitted, MOSFETs can be used as the switching elements 15 and 17, and the turn-on time of the insulated gate semiconductor element 10 can be shortened in the same manner.

  FIG. 4 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the third embodiment of the present invention.

  In the third embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the first embodiment of the present invention shown in FIG. The third embodiment is different from the first embodiment in that a capacitor 19 is connected in parallel with the resistor 7 connected in series with the second series connection body, that is, in series with the positive-side NPN semiconductor element 3. Further, the capacitor 20 is connected in parallel with the resistor 8 connected in series to the second series connection body, that is, in series with the negative side PNP semiconductor element 4.

  Thus, by providing the capacitor 19 in parallel with the resistor 7 connected in series with the second series connection body to reduce the impedance, the gate positive bias during the ON period has a noisy sudden disturbance. Even in this case, the fluctuation can be further reduced.

  Similarly, by providing a capacitor 20 in parallel with the resistor 8 connected in series with the second series connection body to reduce the impedance, there is a noise-like sudden change disturbance in the gate negative bias during the off period. In addition, the fluctuation can be further reduced.

  FIG. 5 is a drawing showing an example of a one-shot signal generating circuit used for the gate circuit of the gate type semiconductor device of the present invention.

  As shown in FIG. 5, the one-shot signal generation circuit 18 receives the output signal A of the switching signal source 12 with a capacitor 181 and connects its output to the middle point of a series circuit of a resistor 182 and a resistor 183. The point is used as the output of the one-shot signal generation circuit 18. If a control voltage is applied to both ends of the series circuit of the resistor 182 and the resistor 183, the capacitor 181, the resistor 182 and the resistor 183 form a differentiation circuit.

  The signal width of the one-shot signal by this differentiation circuit can be determined by the time constants of the capacitor 181, the resistor 182, and the resistor 183, as is well known.

  Thus, by generating a one-shot signal by the differentiation circuit, the gate circuit of the insulated gate semiconductor element can be operated as in the first to third embodiments.

  Although not shown, a circuit using a commercially available monostable multi-IC or the like may be applied as means for creating a one-shot signal using the output signal A of the switching signal source 12 as a trigger.

  FIG. 6 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the fifth embodiment of the present invention.

  In the fifth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the third embodiment of the present invention shown in FIG. The fifth embodiment is different from the third embodiment in that the collector voltage of the insulated gate semiconductor element 10 is detected via the Zener diode 21 and applied to the base of the switching element 17 via the resistor 23. Further, the collector voltage of the insulated gate semiconductor element 10 is detected via the diode 23 and applied to the base of the switching element 15 via the resistor 24.

  First, consider the operation at turn-on. By selecting the resistor 23 to an appropriate value, when the collector voltage becomes equal to or lower than the predetermined voltage value, the switching element 17 that was turned on before the turn-on can be turned off.

  Similarly, at the time of turn-off, by selecting the resistor 24 to an appropriate value, the switching element 15 that was turned on before the turn-off can be turned off when the collector voltage exceeds a predetermined voltage value.

  In this embodiment, since the switching element 17 is turned on based on the collector voltage of the insulated gate semiconductor element 10, the insulated gate semiconductor element 10 can be softly turned on by the resistors 9 and 5. .

  Therefore, the turn-on time of the insulated gate semiconductor element 10 can be shortened, and the turn-on can be made soft so that the voltage rise at the turn-on can be made smooth.

  Similarly, in the present embodiment, the turn-off time of the insulated gate semiconductor element 10 can be shortened, and the turn-off voltage can be made smooth by making the turn-off soft.

  FIG. 7 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the sixth embodiment of the present invention.

  In the sixth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the third embodiment of the present invention shown in FIG. The difference between the sixth embodiment and the third embodiment is that the gate voltage of the insulated gate semiconductor element 10 is detected via the comparator 25, and the output of the comparator 25 is used as the gate input of the switching element 17. The gate voltage of the insulated gate semiconductor element 10 is detected through the comparator 26, and the output of the comparator 25 is used as the gate input of the switching element 15.

  The comparator 25 compares the gate voltage of the insulated gate semiconductor element 10 with the reference voltage V1 using the internal power supply of the gate circuit (for example, dividing the P / N potential), and the gate voltage becomes equal to or higher than a predetermined voltage value. At that time, the switching element 17 is turned off. Similarly, the comparator 26 compares the gate voltage of the insulated gate semiconductor element 10 with a reference voltage V2 using an internal power supply (for example, P / N potential is divided) of the gate circuit, and the gate voltage is a predetermined voltage value. The switching element 15 is turned off at the time point below.

  Here, the reference voltage V1 of the comparator 25 that controls the switching element 17 is set slightly lower than the mirror voltage when the insulated gate semiconductor 10 shown in FIG. 2 is turned on. The reference voltage V2 of the comparator 26 that controls the switching element 16 is set slightly higher than the mirror voltage at the time of turn-off of the insulated gate semiconductor 10 shown in FIG.

  According to the gate circuit of the insulated gate semiconductor element according to the present embodiment, since the switching element 17 and the switching element 15 are turned off based on the gate voltage of the insulated gate semiconductor element 10, the insulated gate semiconductor element It is not necessary to determine the timing for turning off the switching element 17 and the switching element 15 in consideration of the influence of the arrival time variation to the mirror voltage at the turn-on and turn-off caused by the variation in the gate capacitance of 10.

  Therefore, according to the present embodiment, the turn-on and turn-off times of the insulated gate semiconductor element 10 can be shortened with certainty.

  Although not shown, as a means for generating the reference voltages V1 and V2 using the internal power supply of the gate circuit (for example, dividing the P / N potential), a commercially available three-terminal regulator or the like is applied. Also good.

  FIG. 8 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the seventh embodiment of the present invention.

  In the seventh embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the sixth embodiment of the present invention shown in FIG. The difference between the seventh embodiment and the sixth embodiment is that the reference voltage of the comparator 25 is a value obtained by dividing the P potential by the resistor 251 and the Zener diode 252, and the reference voltage of the comparator 26 is The point is that the P potential is divided by the resistor 261 and the Zener diode 262.

  The breakdown voltage of the Zener diode 252 is selected so that the reference voltage of the comparator 25 is slightly lower than the mirror voltage when the insulated gate semiconductor element 10 is turned on. Similarly, the breakdown voltage of the Zener diode 262 is selected so that the reference voltage of the comparator 26 is slightly higher than the mirror voltage when the insulated gate semiconductor element 10 is turned off.

  According to the gate circuit of the insulated gate semiconductor element of this embodiment, the switching element 17 and the switching element 15 are turned off based on the gate voltage of the insulated gate semiconductor element 10, so that the insulated gate semiconductor element It is not necessary to determine the timing for turning off the switching element 17 and the switching element 15 in consideration of the influence of the arrival time variation to the mirror voltage at the turn-on and turn-off caused by the variation in the gate capacitance of 10.

  Therefore, according to the present embodiment, the turn-on and turn-off time of the insulated gate semiconductor element 10 can be further shortened as in the case of the sixth embodiment. In addition, since the reference voltage in this embodiment is not affected by fluctuations in the internal voltage of the gate circuit of P potential and N potential, it is possible to provide a gate circuit of an insulated gate semiconductor element with higher reliability. .

  Although not shown, the reference voltage of the comparator 25 may be connected directly from the emitter.

  FIG. 9 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the eighth embodiment of the present invention.

  In the eighth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the sixth embodiment of the present invention shown in FIG. The eighth embodiment is different from the sixth embodiment in that a collector current detector 27 is provided and the output of the collector current detector 27 is configured as one input of the comparator 25 and the comparator 26.

  With the above configuration, when the collector current applied to the comparator 25 becomes equal to or higher than the reference voltage value Vi1 that is the other input of the comparator 25, the switching element 17 is turned off, and the collector current applied to the comparator 26 is The switching element 15 performs an off operation when the reference voltage value Vi2 which is the other input of 26 becomes equal to or higher.

  Here, the reference voltage Vi1 of the comparator 25 that controls the switching element 17 is set to a lower value that can detect that the collector current Ic of the insulated gate semiconductor 10 has started to flow, and dI / dt increases at turn-on. The switching element 17 can be turned off during the period. Further, the reference voltage Vi2 of the comparator 26 that controls the switching element 15 is set to a higher value that can detect that the collector current Ic of the insulated gate semiconductor 10 finishes flowing, and −dI / dt at the time of turn-off increases. The switching element 15 can be turned off during the period.

  According to the gate circuit of the insulated gate semiconductor element of this embodiment, the switching element 17 and the switching element 15 are turned off based on the collector current of the insulated gate semiconductor element 10, so that the insulated gate semiconductor element 10 can be softly turned on / off.

  Therefore, according to the present embodiment, the turn-on time of the insulated gate semiconductor element 10 can be shortened and the turn-on is made soft, so that the voltage rise at the turn-on can be made smooth. Further, according to the present embodiment, the turn-off time of the insulated gate semiconductor element 10 can be shortened and the turn-off is made soft, so that the voltage rise at the turn-off can be made smooth.

  FIG. 10 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to the ninth embodiment of the present invention.

  In the ninth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the third embodiment of the present invention shown in FIG. The ninth embodiment is different from the third embodiment in that the switching elements 15 and 17 and the one-shot generation circuits 16 and 18 are omitted, and a capacitor 28 is provided in parallel with the resistor 5 and a capacitor 29 is provided in parallel with the resistor 6. It is.

  The capacities of the capacitors 28 and 29 are sufficiently larger than the capacity between the gate and the emitter of the insulated gate semiconductor element 10, and the capacitors 28 and 29 are capacitors having excellent high frequency characteristics, such as PP (polypropylene) film capacitors. To do.

  As a result, the gate circuit of the insulated gate semiconductor device of this embodiment secures a one-shot time similar to the case where the switching devices 15 and 17 are provided, and charges quickly when the insulated gate semiconductor device 10 is turned on. Therefore, the turn-on time of the insulated gate semiconductor element 10 can be shortened, and the charged charge can be discharged quickly at the time of turn-off, thereby shortening the turn-off time of the insulated gate semiconductor element 10.

  Further, by applying a capacitor having excellent high frequency characteristics, it is possible to reliably operate with low loss even when the on / off operating frequency of the insulated gate semiconductor element 10 is fast.

  FIG. 11 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to Example 10 of the present invention.

  In the tenth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the first embodiment of the present invention shown in FIG. The difference between the tenth embodiment and the first embodiment is that the outputs of the delay circuits 13 and 14 are supplied to the gates of the NPN semiconductor element 3 and the PNP semiconductor element 4 via the diodes 30 and 31, respectively. On the other hand, a one-shot generation circuit 32 is provided at the output of the switching signal source 17, and this output is supplied to the gate of the NPN semiconductor element 3 via the diode 33. The shot generating circuit 34 is provided, and this output is supplied to the gate of the PNP type semiconductor element 4 through the diode 35.

  In the gate circuit of the insulated gate semiconductor element of this embodiment, a logical sum signal of the delayed switching signal from the delay circuit 13 and the one-shot signal from the one-shot signal generation circuit 32 is generated by the diode 30 and the diode 33. The logical sum signal is supplied to the base of the NPN semiconductor element 3 on the positive side of the second series connection body. The diode 31 and the diode 35 make a logical sum signal of the delayed switching signal from the delay circuit 14 and the one-shot signal generation circuit 34, and this logical sum signal is connected to the second serial connection body. The negative side PNP type semiconductor element 4 is configured to be supplied to the base.

  When the output signal A of the switching signal source 17 is turned on, first, the NPN semiconductor element 3 on the positive side is turned on by the one-shot signal from the one-shot signal generation circuit 32, and the insulated gate is caused by a large current via the resistor 7. Charge is started between the gate and emitter of the type semiconductor element 10. After the one-shot time elapses, the NPN semiconductor element 3 is temporarily turned off, and the insulated gate semiconductor element 10 is softly turned on by the charging route of the NPN semiconductor element 1, the resistor 9, and the resistor 5.

  After the turn-on, the NPN semiconductor element 3 is turned on again by the output signal of the delay circuit 13 and enters a positive bias state via the resistor 7.

  Next, when the output signal A of the switching signal source 17 becomes an off signal, the negative PNP semiconductor element 4 is first turned on by the one-shot signal from the one-shot signal generation circuit 34, and a large current through the resistor 8 Discharge of the charge between the gate and the emitter of the insulated gate semiconductor element 10 starts. After the one-shot time has elapsed, the PNP semiconductor element 4 is temporarily turned off, and the insulated gate semiconductor element 10 is softly turned off by the discharge route of the PNP semiconductor element 2, the resistor 9, and the resistor 6.

  After the turn-off, the PNP type semiconductor element 4 is turned on again by the output signal of the delay circuit 14 to enter a negative bias state via the resistor 8.

  With the above operation, in this embodiment, the turn-on and turn-off time of the insulated gate semiconductor element 10 can be shortened, and the turn-on / off becomes soft, so that the voltage rise at the turn-on / off is smooth. Can be.

  The one-shot signal generation circuits 32 and 34 applied to the present embodiment are configured by a differentiation circuit composed of a resistor and a capacitor, or a commercially available monostable multi IC as described in the fourth embodiment. It is possible.

  FIG. 12 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to Example 11 of the present invention.

  The same parts as those of the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the tenth embodiment of the present invention shown in FIG. The difference between the eleventh embodiment and the tenth embodiment is that a P-channel semiconductor element 2A, a resistor 5, a resistor 6, and an N-channel semiconductor element 1A are used instead of the series circuit including the first series connection body and the resistors at both ends thereof. A P-channel semiconductor, instead of a series circuit composed of a second series connection body and resistors at both ends thereof, a point in which the middle point of the resistors 5 and 6 is connected to one end of the resistor 9 A series circuit composed of the element 4A, the resistor 7, the resistor 8 and the N-channel semiconductor element 3A is provided, and the middle point of the resistor 7 and the resistor 8 is connected to the other end of the resistor 9 and the gate of the insulated gate semiconductor element 10 In addition, an inversion circuit 35 for inverting the signal of the switching signal source 17 is added, and instead of the diode OR circuit composed of the diodes 30 and 33 and the diodes 31 and 35, OR circuits 36 and 37, respectively. Is the point provided.

  Here, since the arm configuration of the P-channel semiconductor element and the N-channel semiconductor element in the series circuit is reversed, the inverting circuit 35 is necessary. Even when a MOSFET is applied as a semiconductor element applied to a series circuit as in the present embodiment, it is not always necessary to reverse the polarity of the arm as shown in the second embodiment. Since this may be advantageous, the polarity configuration of the arm is reversed in this embodiment.

  The reason why the resistance of the series circuit is set not to the outside (control power supply side) but to the inside (gate side) as shown in the second embodiment is because it may be advantageous in terms of stability. There is no need to do so.

  Thus, even when the configuration of the series circuit is changed, the turn-on and turn-off times of the insulated gate semiconductor element 10 can be shortened as described in the tenth embodiment.

  Although not shown in the figure, the P-channel semiconductor elements 2A and 4A and the N-channel semiconductor elements 1A and 3A are MOSFETs. However, these may be formed of bipolar transistors.

  Further, the configuration of the series circuit shown in FIG. 12 can also be applied to the first to third embodiments and the fifth to tenth embodiments, and the same applies to the following embodiments.

  FIG. 13 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to Embodiment 12 of the present invention.

  The same parts as those of the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the eleventh embodiment of the present invention shown in FIG. The difference between the twelfth embodiment and the eleventh embodiment is that a first positive power source E1 and a second positive power source E2 connected in series are provided, and the switching element 17A is connected from the second positive power source E2 via the diode 38. The control power is supplied from the first positive power source E1 to the positive power source P through the diode 39, and the inverter 35 is connected to the collector, and the emitter of the switching element 17A is connected to the positive power source P. The base driving of the switching element 17A is performed from the output of the first through the one-shot signal generation circuit 18, and further, a first negative power source E3 and a second negative power source E4 connected in series are provided, The negative power source E4 is connected to the emitter of the switching element 15A via the diode 40, and the collector of the switching element 15A is connected to the negative power source N. From a source E3 through a diode 41 supplies control power to the negative supply N, lies in that to perform the base drive of the switching element 15A from the output of the inverting circuit 35 through a one-shot signal generating circuit 16.

  The switching element 17A is turned on for a predetermined time by the output signal of the one-shot signal generation circuit 18 triggered by the ON control signal of the output signal A from the switching signal source 17. Then, when the insulated gate semiconductor element 10 is turned on, a voltage of E1 + E2 is supplied to the line of the positive power supply P, and the potential on the on gate power supply side of the insulated gate semiconductor element 10 is increased.

  When the potential of E1 + E2 is supplied to the line of the positive power supply P and the potential rises, it becomes possible to charge more quickly between the gate and the emitter of the insulated gate semiconductor element 10, and reach the mirror time. The time can be shortened, and the turn-on time of the insulated gate semiconductor element 10 can be shortened.

  The switching element 15A is turned on for a predetermined time by the output signal of the one-shot signal generation circuit 16 triggered by the off control signal of the output signal A from the switching signal source 17. Then, when the insulated gate semiconductor element 10 is turned off, the voltage of E3 + E4 is supplied to the line of the negative power supply N, and the potential on the off gate power supply side of the insulated gate semiconductor element 10 is lowered.

  When the voltage of E3 + E4 is supplied to the negative power supply N line and the potential drops, the charge between the gate and the emitter of the insulated gate semiconductor element 10 can be extracted more quickly, and the mirror time is shortened. Thus, the turn-off time of the insulated gate semiconductor element 10 can be shortened.

  As described above, the turn-on and turn-off time can be shortened also by changing the voltage of the control power supply as in this embodiment.

  FIG. 14 is a circuit configuration diagram showing a gate circuit of an insulated gate semiconductor device according to Embodiment 13 of the present invention.

  In the thirteenth embodiment, the same parts as those in the circuit configuration diagram of the gate circuit of the insulated gate semiconductor device according to the eleventh embodiment of the present invention shown in FIG. The difference between the thirteenth embodiment and the eleventh embodiment is that the third series circuit includes a PNP type semiconductor element 42, a resistor 43, a resistor 44, and an NPN type semiconductor element 45, both ends of which are connected to positive and negative power supplies. The one-shot signal generating circuits 18 and 16 are respectively connected from the point where the middle point of the resistors 43 and 44 is connected to the middle point of the second series circuit and the gate of the insulated gate semiconductor element 10 and from the output of the inverting circuit 35. And the gates of the P-channel semiconductor element 4A and the N-channel semiconductor element 3A constituting the second series circuit are respectively driven. The output from the inverting circuit 35 is driven through the delay circuits 13 and 14, respectively.

  When the insulated gate semiconductor element 10 is turned on, the charge for charging between the gate and the emitter of the insulated gate semiconductor element 10 during the predetermined time when the PNP semiconductor element 42 is turned on by the one-shot signal is PNP type. It is charged through the charging route of the semiconductor element 42 and the resistor 43. Therefore, the turn-on time can be shortened by this quick one-shot charging.

  Further, when the insulated gate semiconductor element 10 is turned off, the charge for discharging between the gate and the emitter of the insulated gate semiconductor element 10 during a predetermined time when the NPN semiconductor element 45 is turned on by the one-shot signal, It is discharged through the discharge route of the NPN semiconductor element 45 and the resistor 44. Therefore, the turn-off time can be shortened by this quick discharge of the one-shot time.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, it is possible to combine the respective embodiments to obtain further modified embodiments. it is obvious.

The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 1 of this invention. 4 is a time chart showing the operation of the gate circuit of the insulated gate semiconductor element according to the first embodiment. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 2 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 3 of this invention. The circuit block diagram which shows an example of the one shot signal generation circuit used for the gate circuit of the insulated gate semiconductor element which concerns on this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 5 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 6 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 7 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 8 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 9 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 10 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 11 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 12 of this invention. The circuit block diagram of the gate circuit of the insulated gate semiconductor element which concerns on Example 13 of this invention.

Explanation of symbols

1, 3 NPN type semiconductor element 2, 4 PNP type semiconductor element 3A N channel semiconductor element 3B P channel semiconductor element 5, 6, 7, 8, 9 Resistance 10 Insulated gate type semiconductor element 11 Resistance 12 Switching signal source 13, 14 Delay Circuits 15 and 17 Switching elements 16 and 18 One-shot signal generation circuit 19 and 20 Capacitor 21 Zener diode 22 Diode 23 and 24 Resistor 25 and 26 Comparator 27 Current detector 28 and 29 Capacitors 30, 31, 33 and 35 Diodes 32 and 34 One-shot signal generation circuit 35 Inversion circuit 36, 37 OR circuit 38, 39, 40, 41 Diode 42 N-channel semiconductor element 43, 44 Resistance 45 P-channel semiconductor element

Claims (15)

A first series circuit in which one end is connected to a positive power source, and the first semiconductor control element and the first resistor are connected in series;
One end is connected to the other end of the first series circuit, the other end is connected to a negative power source, and a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor are connected in series. A second series circuit comprising:
One end is connected to the positive power supply, the other end is connected to the gate of the insulated gate semiconductor element, and a third semiconductor control element having the same polarity as the first semiconductor control element and a third resistor are connected in series. A third series circuit;
One end is connected to the other end of the third series circuit, the other end is connected to the negative power supply, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. A fourth series circuit comprising:
A fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element;
A switching signal source for supplying a switching signal to a control pole of the first semiconductor control element and a control pole of the second semiconductor control element connected to each other via a sixth resistor;
Two delay circuits for supplying a switching signal from the switching signal source to each control pole of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively;
A switching element provided in parallel with the first resistor;
A gate circuit for an insulated gate semiconductor element, comprising control means for controlling on / off of the switching element. The control means includes
2. The insulated gate semiconductor according to claim 1, wherein a one-shot signal is generated using an on command signal output from the switching signal source as a trigger, and the switching element is turned on by the one-shot signal. The gate circuit of the element. A collector voltage detecting means for detecting a collector voltage of the insulated gate semiconductor element;
The control means includes
2. The gate circuit for an insulated gate semiconductor device according to claim 1, wherein the switching element is turned off when a voltage value detected by the collector voltage detection means becomes a predetermined value or less. The voltage detection means includes
4. The gate circuit for an insulated gate semiconductor device according to claim 3, wherein the collector voltage is detected via a Zener diode. Gate voltage detecting means for detecting a gate voltage of the insulated gate semiconductor element;
The control means includes
2. The gate circuit for an insulated gate semiconductor device according to claim 1, wherein the switching element is turned off when a voltage value detected by the gate voltage detection means exceeds a predetermined reference voltage value. . The reference voltage value is
6. The gate circuit for an insulated gate semiconductor device according to claim 5, wherein the gate circuit is obtained by using an internal voltage of the gate circuit. The reference voltage value is
6. The gate circuit for an insulated gate semiconductor device according to claim 5, wherein the positive power source is obtained by dividing a voltage with a resistor and a Zener diode. A collector current detecting means for detecting a collector current of the insulated gate semiconductor element;
The control means includes
2. The gate circuit for an insulated gate semiconductor device according to claim 1, wherein the switching element is turned off when a current value detected by the collector current detecting means exceeds a predetermined reference current value. . A first series circuit in which one end is connected to a positive power source, and the first semiconductor control element and the first resistor are connected in series;
One end is connected to the other end of the first series circuit, the other end is connected to a negative power source, and a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor are connected in series. A second series circuit comprising:
One end is connected to the positive power supply, the other end is connected to the gate of the insulated gate semiconductor element, and a third semiconductor control element having the same polarity as the first semiconductor control element and a third resistor are connected in series. A third series circuit;
One end is connected to the other end of the third series circuit, the other end is connected to the negative power supply, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. A fourth series circuit comprising:
A fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element;
A switching signal source for supplying a switching signal to a control pole of the first semiconductor control element and a control pole of the second semiconductor control element connected to each other via a sixth resistor;
Two delay circuits for supplying a switching signal from the switching signal source to each control pole of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively;
A gate circuit for an insulated gate semiconductor device, comprising: a capacitor provided in parallel with the first resistor and having a capacity equal to or greater than a gate capacitance of the insulated gate semiconductor device.   10. The gate circuit for an insulated gate semiconductor device according to claim 9, wherein the capacitor has high frequency characteristics. A first series circuit in which one end is connected to a positive power source, and the first semiconductor control element and the first resistor are connected in series;
One end is connected to the other end of the first series circuit, the other end is connected to a negative power source, and a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor are connected in series. A second series circuit comprising:
One end is connected to the positive power supply, the other end is connected to the gate of the insulated gate semiconductor element, and a third semiconductor control element having the same polarity as the first semiconductor control element and a third resistor are connected in series. A third series circuit;
One end is connected to the other end of the third series circuit, the other end is connected to the negative power supply, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. A fourth series circuit comprising:
A fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element;
A switching signal source for supplying a switching signal to a control pole of the first semiconductor control element and a control pole of the second semiconductor control element connected to each other via a sixth resistor;
First and second delay circuits for supplying a switching signal from the switching signal source to the respective control poles of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively;
One-shot signal generation means triggered by an ON command signal output from the switching signal source,
Insulated gate semiconductor comprising: an OR generation means for giving an OR of an output of the one-shot signal generation means and an output of the first delay circuit to a control pole of the third semiconductor control element The gate circuit of the element. The logical sum generation means includes
A first diode for supplying a signal from an output of the first delay circuit to a control pole of the third semiconductor control element;
12. The gate circuit for an insulated gate semiconductor device according to claim 11, comprising a second diode for supplying a signal from an output of the one-shot signal generating means to a control pole of the third semiconductor control device. . A first series circuit in which one end is connected to a positive power source, and the first semiconductor control element and the first resistor are connected in series;
One end is connected to the other end of the first series circuit, the other end is connected to a negative power source, and a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor are connected in series. A second series circuit comprising:
One end is connected to the positive power supply, the other end is connected to the gate of the insulated gate semiconductor element, and a third semiconductor control element having the same polarity as the first semiconductor control element and a third resistor are connected in series. A third series circuit;
One end is connected to the other end of the third series circuit, the other end is connected to the negative power supply, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. A fourth series circuit comprising:
A fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element;
A switching signal source for supplying a switching signal to a control pole of the first semiconductor control element and a control pole of the second semiconductor control element connected to each other via a sixth resistor;
Two delay circuits for supplying a switching signal from the switching signal source to each control pole of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively;
A positive addition power source connected in series in the positive electrode direction of the positive power source;
A voltage addition switching element connected to the positive power supply via a third diode from the positive electrode of the positive addition power supply,
A gate circuit for an insulated gate semiconductor device, wherein the voltage adding switching device is turned on by a one-shot signal triggered by an on command signal output from the switching signal source. A first series circuit in which one end is connected to a positive power source, and the first semiconductor control element and the first resistor are connected in series;
One end is connected to the other end of the first series circuit, the other end is connected to a negative power source, and a second semiconductor control element having a polarity opposite to that of the first semiconductor control element and a second resistor are connected in series. A second series circuit comprising:
One end is connected to the positive power supply, the other end is connected to the gate of the insulated gate semiconductor element, and a third semiconductor control element having the same polarity as the first semiconductor control element and a third resistor are connected in series. A third series circuit;
One end is connected to the other end of the third series circuit, the other end is connected to the negative power supply, and a fourth semiconductor control element having a polarity opposite to that of the third semiconductor control element and a fourth resistor are connected in series. A fourth series circuit comprising:
A fifth resistor connected between a connection point of the first series circuit and the second series circuit and a gate of the insulated gate semiconductor element;
A switching signal source for supplying a switching signal to a control pole of the first semiconductor control element and a control pole of the second semiconductor control element connected to each other via a sixth resistor;
One end is connected to the positive power source, the other end is connected to the gate of the insulated gate semiconductor element, and a fifth semiconductor control element having the same polarity as the first semiconductor control element and a seventh resistor are connected in series. A fifth series circuit;
Two delay circuits for supplying a switching signal from the switching signal source to each control pole of the third semiconductor control element and the fourth semiconductor control element with a predetermined time delay, respectively;
5. A gate circuit for an insulated gate semiconductor element, wherein the fifth semiconductor control element is turned on by a one-shot signal triggered by an on command signal output from the switching signal source. 15. The gate circuit for an insulated gate semiconductor device according to claim 1, wherein a capacitor is connected in parallel with at least one of the third resistor and the fourth resistor. .

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