WO2021189282A1

WO2021189282A1 - Drive circuit and related chip

Info

Publication number: WO2021189282A1
Application number: PCT/CN2020/081033
Authority: WO
Inventors: 李宗隆; 范铨奇; 徐建昌
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2021-09-30
Also published as: CN111936949A

Abstract

A drive circuit (200) and a related chip. The drive circuit comprises a logic circuit (110), a push-pull circuit (120), and a control circuit (210). The logic circuit is used to generate a data signal. The push-pull circuit comprises a first transistor (M1). When the data signal transitions from a first logic state to a second logic state, the first transistor is used to change, during a first transition period, the potential at an output terminal of the drive circuit from a first potential corresponding to the first logic state to a second potential corresponding to the second logic state. The control circuit is coupled to the push-pull circuit, and controls, during the first transition period and before the potential at the output terminal reaches the second potential, a current flowing through the first transistor to be a first constant current (ics1).

Description

Drive circuit and related chips

Technical field

This application relates to a circuit, in particular to a driving circuit and related chips.

Background technique

The interface of the integrated circuit usually needs to comply with some design specifications of electronic components. For example, a general-purpose input/output interface (general-purpose input/output) needs to comply with the design specifications of electromagnetic interference (EMI). Therefore, an innovative design is needed to reduce the EMI of the existing interface.

Summary of the invention

One of the objectives of the present application is to disclose a circuit, especially a driving circuit and related chips, to solve the above-mentioned problems.

An embodiment of the present application discloses a driving circuit: including a logic circuit, a push-pull circuit, and a control circuit, wherein the logic circuit is used to generate a data signal; the push-pull circuit includes: a first transistor for When the data signal transitions from the first logic state to the second logic state, the potential of the output terminal of the driving circuit is transitioned from the first potential corresponding to the first logic state to the corresponding state during the first transition period. The second potential of the second logic state; the control circuit, coupled to the push-pull circuit, is used during the first transition period, before the potential of the output terminal reaches the second potential, The current flowing through the first transistor is controlled to be a first constant current.

An embodiment of the present application discloses a chip including the aforementioned driving circuit.

The driving circuit disclosed in the present application can control the current flowing through the turned-on pull-up transistor or the turned-on pull-down transistor to a constant current. Accordingly, during each on period, the slew rate of the pull-up transistor and the pull-down transistor can be controlled to improve the EMI problem.

Description of the drawings

The circuit diagram of FIG. 1A illustrates the charging operation of the driving circuit.

The voltage waveform diagram of FIG. 1B illustrates the relationship between the voltage at the output terminal of the driving circuit and the time during the operation of charging the equivalent capacitor.

The circuit diagram of FIG. 1C illustrates the discharging operation of the driving circuit.

The voltage waveform diagram of FIG. 1D illustrates the relationship between the voltage at the output terminal of the driving circuit in the operation of discharging the equivalent capacitance with respect to time.

The circuit diagram of FIG. 2A illustrates the charging operation of the driving circuit of the present application.

The voltage waveform diagram of FIG. 2B illustrates the relationship between the voltage at the output terminal of the driving circuit of FIG. 2A during the operation of charging the equivalent capacitor with respect to time.

The circuit diagram of FIG. 2C illustrates the discharging operation of the driving circuit of the present application.

The voltage waveform diagram of FIG. 2D illustrates the relationship between the voltage at the output terminal of the driving circuit of FIG. 2C in the operation of discharging the equivalent capacitance with respect to time.

FIG. 3 is a circuit diagram of yet another embodiment of the driving circuit of the application.

FIG. 4 is a circuit diagram of still another embodiment of the driving circuit of the application.

FIG. 5 is a circuit diagram of another embodiment of the driving circuit of the application.

Detailed ways

The following disclosure provides multiple implementations or examples, which can be used to realize different features of the disclosure. The specific examples of components and configurations described below are used to simplify the present disclosure. When conceivable, these narratives are only examples, and they are not intended to limit the content of this disclosure. For example, in the following description, forming a first feature on or on a second feature may include some embodiments where the first and second features are in direct contact with each other; and may also include In some embodiments, additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms here, such as "below", "below", "below", "above", "above" and similar, may be used to facilitate the description of the drawing in the figure The relationship between one component or feature relative to another component or feature is shown. The original meaning of these spatially-relative vocabulary covers not only the orientation shown in the figure, but also the various orientations of the device in use or operation. The device may be placed in other orientations (for example, rotated 90 degrees or in other orientations), and these spatially-relative description vocabulary should be explained accordingly.

Although the numerical ranges and parameters used to define the broader scope of the present application are approximate numerical values, the relevant numerical values in the specific embodiments have been presented here as accurately as possible. However, any value inevitably contains standard deviations due to individual test methods. Here, "same" usually means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a specific value or range. Or, the term "same" means that the actual value falls within the acceptable standard error of the average value, depending on the consideration of a person with ordinary knowledge in the technical field to which this application belongs. It should be understood that all ranges, quantities, values and percentages used herein (for example, used to describe the amount of material, time length, temperature, operating conditions, quantity ratio and other Those who are similar) are all modified with the "same" modification. Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying patent scope are approximate values and can be changed according to requirements. At least these numerical parameters should be understood as the indicated effective number of digits and the value obtained by applying the general carry method. Here, the numerical range is expressed from one end point to the other end point or between the two end points; unless otherwise specified, the numerical range described here includes the end points.

Generally speaking, input/output interfaces, such as general-purpose input/output (GPIO), are usually composed of transistors. During operation, the equivalent capacitance seen at the output terminal of the input/output interface is charged or discharged through the transistor, so that the input/output interface outputs a high potential or a low potential. For example, the circuit diagrams of FIGS. 1A and 1C illustrate the charging operation and the discharging operation of the driving circuit 100, respectively.

1A, the driving circuit 100 includes a logic circuit 110 and a push-pull circuit 120. The push-pull circuit 120 includes a P-type transistor M1 and an N-type transistor M2, which are connected in series between a specific voltage VDD and VSS. Specifically, the source and drain of the transistor M1 are respectively coupled to a specific voltage VDD and the drain of the transistor M2, and the source of the transistor M2 is coupled to a specific voltage VSS. In some embodiments, the specific voltages VDD and VSS have the same magnitude and opposite polarities. In some embodiments, the specific voltage VSS is the reference ground.

The logic circuit 110 is coupled to the transistors M1 and M2, and is used to turn on only one of the transistors M1 and M2 at any time according to the enable signal EN and the data signal D (ie, the transistors M1 and M2 are not turned on at the same time). For example, the logic circuit 110 includes a NOT gate 112, a NAND gate 114, and a NOR gate 116. The data signal D is transmitted to the gates of the transistors M1 and M2 via the NAND gate 114 and the NOR gate 116, respectively. In detail, based on the enable signal EN of logic 1, the NAND gate 114 reverses the logic state of the received data signal D, and then outputs the reversed data signal D to the gate of the transistor M1. Based on the enable signal EN of logic 1, the NOR gate 116 inverts the logic state of the received data signal D, and then outputs the inverted data signal D to the gate of the transistor M2.

The drains of the transistor M1 and M2 form the output terminal OUT. In Figure 1A, the transistor M2 is not conducting and the transistor M1 is conducting. The transistor M1 uses a specific voltage VDD to charge the equivalent capacitance CL seen at the output terminal OUT to charge the output The potential of the terminal OUT changes from the first potential (approximately VSS, corresponding to logic 0) to the second potential (approximately VDD, corresponding to logic 1) during the rising transition period. It should be noted that the rising transition period refers to a period in which the potential continues to rise, and does not include a period in which the potential remains at the second potential after reaching the second potential without further rising. In FIG. 1C, when the transistor M1 is not conducting and the transistor M2 is conducting, the transistor M2 uses a specific voltage VSS to discharge the equivalent capacitor CL to change the potential of the output terminal OUT from the second potential (approximately VDD) during the falling transition period. ) Transition to the first potential (approximately VSS). The falling transition period refers to a period in which the potential continues to fall, and does not include a period in which the potential remains at the first potential after reaching the first potential and does not continue to fall.

The voltage waveform diagrams of FIG. 1B and FIG. 1D respectively illustrate the relationship between the voltage of the output terminal OUT of the driving circuit 100 during the charging operation and the discharging operation of the equivalent capacitor CL with respect to time. In FIGS. 1B and 1D, the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 100, and the horizontal axis represents time. 1B, observing the curve change of the waveform 130, the potential of the output terminal OUT rapidly climbs to Vr with a steep slope in the initial stage of charging (period dTr), causing the drain-source voltage of the transistor M1 to change greatly in a short time, namely The slew rate (slew rate) is too large; similarly, observe the change of the waveform 135 in Figure 1D, the potential of the output terminal OUT rapidly decreases to Vf with a steep slope at the beginning of discharge (period dTf), which will also cause the slew rate of the transistor M2 is too big. Since the higher the conversion rate, the greater the EMI, and subsequent embodiments will improve the EMI problem by controlling the conversion rates of the transistors M1 and M2 of the push-pull circuit 120.

The circuit diagrams of FIGS. 2A and 2C illustrate the charging operation and the discharging operation of the driving circuit 200, respectively. 2A, the driving circuit 200 is similar to the driving circuit 100 of FIG. 1A, except that the driving circuit 200 further includes a control circuit 210, which is coupled to the push-pull circuit 120. In this embodiment, the control circuit 210 includes a current source Ir and a current tank Ik.

The current source Ir receives a specific voltage VDD and is coupled to the source of the transistor M1. In FIG. 2A, the transistor M2 is not turned on and the transistor M1 is turned on. The current source Ir is used to continuously provide a constant current ics1 through the transistor M1 to the output terminal OUT during the on period of the transistor M1 to charge the equivalent capacitor CL. In short, the current source Ir controls the current flowing through the transistor M1 to a constant current ics1. In this embodiment, the constant current means that the magnitude of the current does not change with time.

In some embodiments, the current source Ir can be implemented by a single P-type transistor, wherein the source of the P-type transistor receives a specific voltage VDD, the gate is controlled by the control voltage, and the drain is coupled to the source of the transistor M1 pole.

The current tank Ik receives a specific voltage VSS and is coupled to the source of the transistor M2. In FIG. 2C, the transistor M1 is not turned on and the transistor M2 is turned on, and the current tank Ik is used to continuously draw a constant current ics2 from the output terminal OUT through the transistor M2 during the on period of the transistor M2 to discharge the equivalent capacitor CL. In short, the current tank Ik controls the current flowing through the transistor M2 to be a constant current ics2.

In some embodiments, the current tank Ik can be implemented by a single N-type transistor, wherein the source of the N-type transistor receives a specific voltage VSS, the gate is controlled by another control voltage, and the drain is coupled to the transistor M2 Of the source.

The voltage waveform diagrams of FIGS. 2B and 2D respectively illustrate the relationship between the voltage at the output terminal OUT of the driving circuit 200 during the charging operation and the discharging operation of the equivalent capacitor CL with respect to time. In FIGS. 2B and 2D, the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 200, and the horizontal axis represents time.

For the convenience of comparison, in FIG. 2B, the waveform 130 of FIG. 1B is drawn. Comparing the

waveforms

230 and 130, it can be observed that the potential of the output terminal OUT indicated by the waveform 230 climbs to Vr at a relatively small absolute value and a substantially fixed slope in the initial charging stage (period dTr) compared to the waveform 130 of FIG. 1B. This means that in the early stage of charging, the drain-source voltage slew rate of the transistor M1 of FIG. 2A is lower than that of the transistor M1 of FIG. 1A.

Similarly, for the convenience of comparison, in FIG. 2D, the waveform 135 in FIG. 1D is drawn. Comparing the

waveforms

235 and 135, it can be observed that the potential of the output terminal OUT indicated by the waveform 235 decreases to Vr at a relatively small absolute value and a substantially constant slope compared to the waveform C135 of FIG. 1D at the initial stage of discharge (period dTf). This means that in the early stage of discharge, the drain-source voltage slew rate of the transistor M2 of FIG. 2C is lower than that of the transistor M2 of FIG. 1C.

Since the respective slew rates of the transistors M1 and M2 can be controlled, the EMI problems in the initial stage of discharge and the initial stage of charging can be improved, and the EMI can meet the specifications.

FIG. 3 is a circuit diagram of an embodiment of the driving circuit 300 of the application. 3, the driving circuit 300 is similar to the driving circuit 200 of FIG. 2A. The difference is that compared with the control circuit 210 of FIG. 2A, the control circuit 310 of the driving circuit 300 further includes: a reference current source Iref and transistors M3, M4, M5, M6 and M7.

Transistors M3 and M4 form a current mirror. Since this current mirror receives a constant current iref from a reference current source Iref (which may be referred to as a reference constant current where appropriate), this current mirror may be referred to as a source current mirror where appropriate, and transistors M3 and M4 may be referred to as reference where appropriate Transistor. In detail, the gate and drain of the transistor M3 are short-circuited and connected to the gate of the transistor M4. The source current mirror replicates the constant current iref received by the transistor M3, and outputs a constant current icof through the transistor M4 (which may be referred to as a replicated constant current where appropriate). In addition to the source current mirror, the driving circuit 300 also includes other current mirrors, which are described in detail as follows.

Transistor M3 and transistor M7 also form a current mirror, which can be called a first current mirror where appropriate. In detail, the gate of the transistor M3 is further short-circuited with the gate of the transistor M7. The first current mirror replicates the constant current iref received by the transistor M3, and outputs the constant current ic1 through the transistor M7. Since the transistor M7 provides the function of a current sink, it can also be referred to as a current sink transistor where appropriate.

The transistors M5 and M6 constitute a current mirror, which can be called a second current mirror where appropriate. In detail, the gate and drain of the transistor M5 are short-circuited and connected to the gate of the transistor M6. The second current mirror copies the constant current icof received by the transistor M5, and outputs the constant current ic2 through the transistor M6. Since the transistor M6 provides the function of a current source, it can also be referred to as a current source transistor where appropriate.

During the charging operation, since the transistors M1 and M6 are connected in series, when the transistor M1 is turned on, the transistor M6 continues to provide a constant current ic2 to the output terminal OUT via the transistor M1.

In the discharging operation, since the transistors M2 and M7 are connected in series, when the transistor M2 is turned on, the transistor M7 continues to draw a constant current ic1 from the output terminal OUT through the transistor M2.

Based on the same reason as described in the first embodiment, since the slew rate of each of the transistors M1 and M2 can be controlled, the driving circuit 300 of the present application can improve the problem of EMI in the initial stage of discharge and the initial stage of charging, and make EMI meet the specifications.

FIG. 4 is a circuit diagram of an embodiment of the driving circuit 400 of this application. 4, the driving circuit 400 is similar to the driving circuit 300 of FIG. 3, the difference is that compared with the control circuit 310 of FIG. 3, the control circuit 410 of the driving circuit 400 further includes: transistors M8, M9, and M10, and transistors M3 and M5 The respective connection modes are different from the respective connection modes of the transistors M3 and M5 of the control circuit 310. In this embodiment, each of the transistors M8, M9, and M10 can be used as a resistor, which is described in detail as follows.

The circuit operator can change the current gear of the reference current source Iref as needed to adjust the size of the constant current iref, so that the charging and discharging time of the parasitic capacitor CL can meet the specification requirements. In order to accurately adjust the charge and discharge time of the parasitic capacitor CL, it is necessary to accurately adjust the constant currents ic1 and ic2.

In order to achieve the above objective, a feasible way is to make the changes of the constant current iref and ic1 as equal as possible to each other, and to make the changes of the constant current iref and ic2 as equal to each other as possible. Incidentally, since the constant current ic2 is directly copied from the constant current icof and indirectly copied from the constant current iref, the amount of change between the constant current iref, icof and ic2 is also equal.

One possible way to achieve this goal is to (1) make the equivalent circuits of constant current iref and ic1 flow as equal as possible to each other; and (2) make the equivalent circuits of constant current iref, icof and ic2 flow as equal to each other as possible .

Regarding the above (1), the equivalent circuit through which the constant current ic1 flows is composed of transistors M2 and M7 connected in series, and the transistor M2 receives a voltage equal to the specific voltage VDD. Accordingly, the transistor M8 is added, and the transistor M8 and M3 are connected in series. In addition, in order for the transistor M8 to follow the behavior of the transistor M2 when it is turned on, the gate of the transistor M8 receives a specific voltage VDD. In this way, the equivalent circuits through which the constant currents ic1 and iref flow are as equal as possible to each other.

Regarding the above (2), the equivalent circuit through which the constant current ic2 flows is composed of transistors M1 and M6 connected in series, and the transistor M1 receives a voltage equivalent to the specific voltage VSS. Accordingly, the transistor M10 is added, and the transistor M10 and M5 are connected in series. In addition, in order for the transistor M10 to follow the behavior of the transistor M1 when it is turned on, the gate of the transistor M10 receives a specific voltage VSS. In this way, the equivalent circuits through which the constant currents ic2 and icof flow are as equal as possible to each other. In addition, the equivalent circuit through which the constant current iref flows is composed of transistors M3 and M8 connected in series, and the transistor M8 receives a specific voltage VDD. Accordingly, the transistor M9 is added, and the transistor M9 and M4 are connected in series. In addition, in order for the transistor M9 to follow the behavior of the transistor M8 when the transistor M8 is turned on, the gate of the transistor M9 also receives a specific voltage VDD. In this way, the equivalent circuits through which the constant current icof and iref flow are as equal as possible to each other. In summary, the equivalent circuits through which constant currents iref, icof, and ic2 flow are as equal as possible to each other.

In addition to viewing from the viewpoint of equivalent circuit, it can also be viewed from the viewpoint of equivalent impedance. To put it simply, let the impedance value with respect to the drain of the transistor M3 be as the same as the impedance value with respect to the drain of the transistor M7. Therefore, the transistor M8 and the transistor M3 are stacked in series. Accordingly, the transistor M8 can be referred to as a stacked transistor where appropriate. Furthermore, the impedance value relative to the drain of the transistor M3 is related to the on-resistance of the transistor M8, and the impedance value relative to the drain of the transistor M7 is related to the on-resistance of the transistor M2. In other words, the transistor M8 can be used as a resistor.

In the same way, let the impedance value with respect to the drain of the transistor M5 be as the same as the impedance value with respect to the drain of the transistor M6. Therefore, a transistor M10 is added to be stacked in series with the transistor M5. Accordingly, the transistor M10 can be referred to as a stacked transistor where appropriate. Furthermore, the impedance value relative to the drain of the transistor M5 is related to the on-resistance of the transistor M10, and the impedance value relative to the drain of the transistor M6 is related to the on-resistance of the transistor M1. In other words, the transistor M10 can be used as a resistor.

In addition, the resistance value with respect to the drain of the transistor M4 is made to be the same as the resistance value with respect to the drain of the transistor M3 as much as possible. Therefore, a transistor M9 is added to be stacked in series with the transistor M4. Accordingly, the transistor M9 can be referred to as a stacked transistor where appropriate. Furthermore, the impedance value relative to the drain of the transistor M4 is related to the on-resistance of the transistor M9, and the impedance value relative to the drain of the transistor M3 is related to the on-resistance of the transistor M8. In other words, the transistor M9 can be used as a resistor.

In summary, the driving circuit 400 of the present application can not only improve the EMI problems in the initial stage of discharge and the initial stage of charging, but also can accurately adjust the constant currents ic1 and ic2.

FIG. 5 is a circuit diagram of an embodiment of the driving circuit 500 of the application. 5, the driving circuit 500 is similar to the driving circuit 400 of FIG. 4, the main difference is that the stacking method of the transistor M1 of the push-pull circuit 120 and the transistor M6 of the control circuit 510 is opposite to the stacking method of FIG. The transistor M2 of the pull circuit 120 and the transistor M7 of the control circuit 510 are opposite to the stacking manner of FIG. 4 in the vertical direction.

In detail, the transistor M1 becomes stacked above the transistor M6, that is, the transistor M1 is coupled between the source of the transistor M6 and the specific voltage VDD. The transistor M2 becomes stacked under the transistor M7, that is, coupled between the source of the transistor M7 and the specific voltage VSS.

In order to accurately adjust the constant currents ic1 and ic2, based on the same reason as in the embodiment of FIG. 4, in response to the stacking changes of the transistors M1 and M6, the transistor M10 becomes stacked on the transistor M5 and is coupled to the transistor M5. Between the source and a specific voltage VDD. In addition, in order for the transistor M10 to follow the behavior of the transistor M1 when it is turned on, the gate of the transistor M10 receives a specific voltage VSS. In addition, in order to form a current mirror, the drain and gate of the transistor M5 are short-circuited to each other, and the drain of the transistor M5 is also short-circuited to the gate of the transistor M6. Overall, the transistors M5, M6, and M10 form the aforementioned second current mirror.

Similarly, in response to the stacking changes of the transistors M2 and M7, the transistor M3 becomes stacked above the transistor M8 and is coupled between the reference current source Iref and the drain of the transistor M8. In addition, in order to make the transistor M8 follow the behavior when the transistor M2 is turned on, the gate of the transistor M8 receives a specific voltage VDD. In order to form a current mirror, the drain and gate of the transistor M3 are short-circuited to each other, and the drain of the transistor M3 is also short-circuited to the gate of the transistor M7. Overall, the transistors M3, M7, and M8 form the aforementioned first current mirror.

Similarly, in response to the stacking changes of the transistors M3 and M8, the transistor M4 becomes stacked above the transistor M9 and coupled between the drain of the transistor M9 and the drain of the transistor M5. In addition, in order for the transistor M9 to follow the behavior of the transistor M8 when it is turned on, the gate of the transistor M9 receives a specific voltage VDD. In order to form a current mirror, the gate of the transistor M4 is coupled to the gate of the transistor M3. Overall, the transistors M3, M4, M8, and M9 form the aforementioned source current mirror.

In summary, the driving circuit 500 of the present application can not only improve the EMI problems in the initial stage of discharge and the initial stage of charging, but also can accurately adjust the constant currents ic1 and ic2.

The present application also provides a chip, which includes a

driving circuit

200, 300, 400, or 500. For example, the chip may be a semiconductor chip realized by a different process.

The above description briefly presents the features of certain embodiments of the present application, so that those with ordinary knowledge in the technical field to which the present application belongs can have a more comprehensive understanding of the various aspects of the present disclosure. Those with ordinary knowledge in the technical field to which this application pertains should understand that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same purpose and/or as the embodiments described herein. To achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equal implementations still belong to the spirit and scope of this disclosure, and various changes, substitutions and alterations can be made without departing from the spirit of this disclosure. With scope.

Claims

A drive circuit, including a logic circuit, a push-pull circuit, and a control circuit, in which

The logic circuit is used to generate a data signal;

The push-pull circuit includes: a first transistor, which is used to change the potential of the output terminal of the drive circuit from the corresponding value during the first transition period when the data signal transitions from the first logic state to the second logic state. The first potential transition of the first logic state is a second potential corresponding to the second logic state;

The control circuit, coupled to the push-pull circuit, is used for controlling the current flowing through the first transistor to be before the potential of the output terminal reaches the second potential during the first transition period The first constant current.
The driving circuit of claim 1, wherein the push-pull circuit further comprises:

The second transistor, when turned on, is used to switch the potential of the output terminal from the second potential to the first potential during the second transition period,

The first transistor and the second transistor are not turned on at the same time.
3. The driving circuit of claim 2, wherein the control circuit is configured to control the current flowing through the second transistor to a second constant current during the second transition period.
The driving circuit of claim 3, wherein the first constant current is the same as the second constant current.
The driving circuit of claim 3, wherein the control circuit comprises:

The current source is used to continuously provide the first constant current to the output terminal via the first transistor during the on-period of the first transistor.
The driving circuit of claim 5, wherein the control circuit further comprises:

The current sink is used for continuously drawing the second constant current from the output terminal through the second transistor during the on period of the second transistor.
The driving circuit of claim 6, wherein the control circuit further comprises:

A source current mirror for receiving a reference constant current, and copying the constant current by copying the reference constant current output; and

A second reference transistor is coupled to the source current mirror to receive the replicated constant current, wherein the second reference transistor and the current source constitute a second current mirror.
7. The driving circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink constitute a first current mirror, and the first reference transistor receives the Reference constant current, wherein the gate and drain of the first reference transistor are short-circuited.
8. The driving circuit of claim 8, wherein the gate and drain of the second reference transistor are short-circuited.
7. The driving circuit of claim 7, wherein the source current mirror comprises: a first reference transistor, wherein the first reference transistor and the current sink constitute a first current mirror, wherein the current sink comprises:

A current sink transistor connected in series with the second transistor, and the gate of the current sink transistor is short-circuited with the gate of the first reference transistor,

The equivalent impedance relative to the current sink transistor is the same as the equivalent impedance relative to the first reference transistor.
The driving circuit of claim 10, wherein the source current mirror further comprises:

A first stacked transistor, connected in series with the first reference transistor,

The equivalent impedance relative to the first reference transistor is related to the on-resistance of the first stacked transistor.
The driving circuit of claim 11, wherein the current source comprises:

A current source transistor connected in series with the first transistor, and the gate of the current source transistor is short-circuited with the gate of the second reference transistor,

The equivalent impedance relative to the current source transistor is the same as the equivalent impedance relative to the second reference transistor.
The driving circuit of claim 12, wherein the second current mirror further comprises:

A second stacked transistor, connected in series with the second reference transistor,

The equivalent impedance relative to the second reference transistor is related to the on-resistance of the second stacked transistor.
The driving circuit of claim 13, wherein the source current mirror further comprises:

A third reference transistor, the gate of the third reference transistor is short-circuited with the gate of the first reference transistor; and

The third stacked transistor is connected in series with the third reference transistor, and the gate of the third stacked transistor is short-circuited with the gate of the first stacked transistor.
The driving circuit of claim 14, wherein the gate of the first stacked transistor is used to receive the first supply voltage.
15. The driving circuit of claim 15, wherein the gate of the second stacked transistor is used to receive a second supply voltage, which is different from the first supply voltage.
15. The driving circuit of claim 16, wherein the drain of the first stacked transistor, the gate of the first reference transistor, and the gate of the current sink transistor are short-circuited to each other.
17. The driving circuit of claim 17, wherein the drain of the second stacked transistor, the gate of the second reference transistor, and the gate of the current source transistor are short-circuited to each other.
16. The driving circuit of claim 16, wherein the drain and gate of the first reference transistor are short-circuited with the gate of the current sink transistor.
19. The driving circuit of claim 19, wherein the drain and gate of the second reference transistor and the gate of the current source transistor are short-circuited to each other.
3. The driving circuit of claim 2, wherein the first transistor and the second transistor have different polarities, and the digital signals received by the gates of each have the same logic state.
A chip, characterized in that the chip includes:

The drive circuit according to any one of claims 1-21.