CN111277261B

CN111277261B - Level conversion circuit

Info

Publication number: CN111277261B
Application number: CN202010260150.1A
Authority: CN
Inventors: 严慧婕; 蒋宇
Original assignee: Shanghai IC R&D Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2023-10-20
Anticipated expiration: 2040-04-03
Also published as: CN111277261A

Abstract

The present invention provides a level shift circuit, the circuit comprising: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first regulation circuit, at least one second pull-down transistor, at least one second regulation circuit; the first regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the first regulating circuit is connected with a first node, the second port is grounded, and the third port is connected with a first signal end; the second regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the second regulating circuit is connected with the second node, the second port is grounded, and the third port is connected with the second signal end. The circuit structure of the invention is simpler, and the output end of the level conversion circuit can successfully realize the high-low level turnover even if the input signal turnover speed is higher under the condition that the voltage change amplitude of the power end is larger.

Description

Level conversion circuit

Technical Field

The present disclosure relates to electronic circuits, and particularly to a level shifter circuit.

Background

In integrated chips, I/O circuitry and core circuitry are typically included. The I/O circuit is used for enabling the kernel circuit and an external circuit of the integrated chip to realize bidirectional data transmission. However, the power supply voltage of the core circuit is usually different from the power supply voltage of the external circuit, so the I/O circuit needs to have voltage conversion capability (i.e., the I/O circuit needs to include a level conversion circuit) to convert the power supply voltage of the core circuit to the power supply voltage suitable for the external circuit for outputting to the external circuit. However, as the functionality of integrated chip products becomes more and more diverse, the integrated chips are typically connected to different external circuits, and the level shifting circuits in the I/O circuits should also have the capability of converting the power supply voltage of the core circuit into a plurality of different voltages, accordingly.

The level shift circuit In the related art is shown In fig. 1, wherein In the circuit shown In fig. 1, when the voltage input by the input terminal In is a low level signal, the NMOS tube 4 and the PMOS tube 1 are turned on, the PMOS tube 2 and the NMOS tube 3 are turned off, and the output voltage of the output terminal Out is 0V; when the input voltage of the input end In is the high-level signal VDDC, the NMOS tube 3 and the PMOS tube 2 are conducted, the NMOS tube 4 and the PMOS tube 1 are cut off, and the output voltage of the output end Out is VDDIO. Based on this, the level conversion circuit can convert the input voltage VDDC into a different voltage output by changing the magnitude of the voltage VDDIO.

However, in the level shift circuit of the related art, when the voltage VDDIO is smaller or larger, and when the input signal flip speed is too fast, the output terminal cannot successfully flip the high and low levels.

Disclosure of Invention

The invention aims to provide a level conversion circuit, which solves the technical problem that the output end cannot successfully realize the high-low level turnover when the voltage VDDIO of the power end is smaller or larger and the turnover speed of an input signal is higher in the related art.

In order to solve the above technical problems, the present invention provides a level shift circuit, including: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first regulation circuit, at least one second pull-down transistor, at least one second regulation circuit;

the grid electrode of the first pull-down transistor is connected with the input end, the source electrode is grounded, and the drain electrode is connected with the first node; the drain electrode of the first pull-up transistor is connected with the first node, the grid electrode of the first pull-up transistor is connected with the second node, and the source electrode of the first pull-up transistor is connected with the power supply end; the input end of the inverter is connected with the grid electrode of the first pull-down transistor, and the output end of the inverter is connected with the grid electrode of the second pull-down transistor; the source electrode of the second pull-down transistor is grounded, and the drain electrode of the second pull-down transistor is connected with the second node; the drain electrode of the second pull-up transistor is connected with the second node, the grid electrode of the second pull-up transistor is connected with the first node, and the source electrode of the second pull-up transistor is connected with the power supply end; the second node is connected with the output end; the first regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the first regulating circuit is connected with a first node, the second port is grounded, and the third port is connected with a first signal end; the second regulating circuit is provided with a first port, a second port and a third port, the first port of the second regulating circuit is connected with the second node, the second port is grounded, and the third port is connected with the second signal end;

When the voltage of the power supply end is greater than or equal to a preset voltage, the first signal end is used for providing an opening voltage for the first regulating circuit so as to enable the first regulating circuit to be conducted, and the output signal of the first node can be turned to a low-level signal; the second signal end is used for providing an opening voltage for the second regulating circuit so as to enable the second regulating circuit to be conducted, and the output signal of the second node can be turned to a low-level signal;

when the voltage of the power supply end is smaller than a preset voltage, the first signal end is used for providing cut-off voltage for the first regulating circuit so that the first regulating circuit is disconnected, and the output signal of the first node can be turned to a high-level signal; the second signal terminal is used for providing cut-off voltage for the second regulating circuit so as to disconnect the second regulating circuit, and the output signal of the second node can be inverted to a high-level signal.

Optionally, the first adjusting circuit includes a first switching transistor and a first adjusting transistor connected in series, and the second adjusting circuit includes a second switching transistor and a second adjusting transistor connected in series;

The drain electrode of the first switch transistor is used as a first port of the first regulating circuit to be connected with the first node, the grid electrode of the first switch transistor is used as a third port of the first regulating circuit to be connected with the first signal end, the source electrode of the first switch transistor is connected with the drain electrode of the first regulating transistor, the grid electrode of the first regulating transistor is connected with the grid electrode of the first pull-down transistor, and the source electrode of the first regulating transistor is used as a second port of the first regulating circuit to be grounded;

the drain electrode of the second switch transistor is used as a first port of the second regulating circuit to be connected with the second node, the grid electrode of the second switch transistor is used as a third port of the second regulating circuit to be connected with the second signal end, the source electrode of the second switch transistor is connected with the drain electrode of the second regulating transistor, the grid electrode of the second regulating transistor is connected with the grid electrode of the second pull-down transistor, and the source electrode of the second regulating transistor is used as a second port of the second regulating circuit to be grounded;

when the voltage of the power supply end is larger than or equal to the preset voltage, the first signal end is used for inputting an opening voltage to the grid electrode of the first switching transistor so as to enable the first switching transistor to be opened; the second signal terminal is used for inputting an opening voltage to the gate of the second switching transistor so as to enable the second switching transistor to be opened

When the voltage of the power supply terminal is smaller than the preset voltage, the first signal terminal is used for outputting an off voltage to the grid electrode of the first switching transistor so as to enable the first switching transistor to be disconnected; the second signal terminal is used for outputting a cut-off voltage to the grid electrode of the second switching transistor so as to disconnect the second switching transistor.

Optionally, the first pull-down transistor and the second pull-down transistor have the same polarity, the first pull-up transistor and the second pull-up transistor have the same polarity, and the polarities of the first pull-down transistor and the first pull-up transistor are opposite.

Optionally, the first adjusting transistor and the first pull-down transistor have the same polarity, and the second adjusting transistor and the second pull-down transistor have the same polarity.

Optionally, the first pull-down transistor and the second pull-down transistor are NMOS transistors, the first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first adjusting transistor and the second adjusting transistor are NMOS transistors.

Optionally, the first signal end and the second signal end are the same signal end.

Optionally, the polarities of the first switching transistor and the second switching transistor are the same.

Optionally, the first switching transistor and the second switching transistor are both NMOS transistors.

Optionally, the first signal end and the second signal end each include a comparison circuit, and the first signal end and the second signal end are connected to the power source end, and are configured to receive a voltage value of the power source end and compare the voltage value with a predetermined voltage.

Optionally, the first pull-down transistor and the second pull-down transistor are the same size; the first pull-up transistor and the second pull-up transistor are the same size.

In summary, the level shifter circuit provided by the present invention includes at least one first adjusting circuit and at least one second adjusting circuit. In the invention, when the voltage of the power supply end is larger so that the pull-up capability of the level conversion circuit is stronger, the first regulating circuit and the second regulating circuit can be conducted to correspondingly improve the pull-down capability of the level conversion circuit, the phenomenon that the pull-up capability of the level conversion circuit is far greater than the pull-down capability is avoided, and the signal of the output end of the level conversion circuit can be quickly turned over to a low-level signal. And when the voltage of the power supply end is smaller so that the pull-up capability of the level conversion circuit is weaker, the first regulating circuit and the second regulating circuit can be disconnected to correspondingly reduce the pull-down capability of the level conversion circuit, the phenomenon that the pull-up capability of the level conversion circuit is far smaller than the pull-down capability is avoided, and the signal of the output end of the level conversion circuit can be quickly turned over to a high-level signal.

Therefore, for the level conversion circuit, when the voltage change amplitude of the power supply end is large so that the pull-up capacity of the level conversion circuit is greatly reduced or improved, the pull-down capacity of the level conversion circuit can be flexibly adjusted correspondingly by controlling the on or off of the first regulating circuit and the second regulating circuit, so that the situation that the pull-up capacity of the level conversion circuit is far away from the pull-down capacity is avoided, and the output end can be ensured to rapidly output a high-level signal or a low-level signal in a short time. Even if the signal turning speed of the input signal is high, the output end can be ensured to successfully realize the turning of the high level and the low level, so that the level conversion circuit can adapt to the diversified requirements of the current chip products.

In addition, the level conversion circuit has a simpler structure.

Drawings

Fig. 1 is a schematic diagram of a level shifter circuit according to the related art;

fig. 2 is a schematic structural diagram of a level shifter circuit according to an embodiment of the present invention.

Detailed Description

As described in the background art, the level shift circuit in the related art is generally shown in fig. 1, and specifically, the level shift circuit includes two PMOS transistors 1 and 2, two NMOS transistors 3 and 4, and an inverter 5. The sources of the PMOS tubes 1 and 2 are connected to a power supply end VDDIO; the grid electrode of the PMOS tube 2 is connected with the node a, and the drain electrode of the PMOS tube 2 is connected with the node b; the grid electrode of the PMOS tube 1 is connected with the node b, and the drain electrode of the PMOS tube 1 is connected with the node a. The grid electrode of the NMOS tube 3 is connected with the input end In and the input end of the inverter 5, the drain electrode of the NMOS tube 3 is connected with the node a, and the source electrode of the NMOS tube 3 is grounded; the grid of NMOS pipe 4 connects the output of inverter 5, and NMOS pipe 4 drain electrode connects node b, and NMOS pipe 4 source electrode ground.

When the input end In of the level conversion circuit inputs a low level signal, the gate of the NMOS tube 3 receives the low level signal, the NMOS tube 3 is turned off, meanwhile, the low level signal is inverted into a high level signal by the inverter 5 and is input to the gate of the NMOS tube 4, the NMOS tube 4 is turned on, then b point charges flow to the ground through the NMOS tube 4, so that b point voltage is pulled down to a low potential, and the output end Out of the level conversion circuit outputs the low level signal, meanwhile, based on the b point voltage being the low potential, the PMOS tube 1 is turned on, the charges of the power supply end VDDIO flow to the node a through the PMOS tube 1, so that a point potential is pulled up to the high potential, and the PMOS tube 2 is turned off.

And when the input end In is input with the high level signal VDDC, the NMOS tube 3 is turned on, the charge of the node a flows to the source of the NMOS tube 3, so that the voltage of the node a is pulled down to be the low level signal, the PMOS tube 2 is turned on, the charge at the power supply end VDDIO flows to the node b through the PMOS tube 2, the voltage of the node b is pulled up to be the high level signal VDDIO at this time, and the output end Out outputs the high level signal VDDIO. Meanwhile, the high level signal VDDC input by the input terminal In is inverted to a low level signal by the inverter 5 and input to the gate of the NMOS transistor 4, and the NMOS transistor 4 is turned off.

As can be seen from the above, in the related art, when the voltage input at the input terminal In of the level conversion circuit is a low level signal, the NMOS transistor 4 and the PMOS transistor 1 are turned on, the PMOS transistor 2 and the NMOS transistor 3 are turned off, and the output voltage at the output terminal Out is a low level signal 0V; when the input voltage of the input end In is the high level signal VDDC, the NMOS tube 3 and the PMOS tube 2 are turned on, the NMOS tube 4 and the PMOS tube 1 are turned off, and the output voltage of the output end Out is the high level signal VDDIO. Based on this, the level conversion circuit can convert the input voltage VDDC into different voltage outputs by changing the voltage of the power supply terminal VDDIO.

However, it should be noted that, due to the short delay between the input signal and the output signal, when the signal at the output terminal is inverted from the low level signal to the high level signal, the PMOS transistor 2 and the NMOS transistor 4 are turned on simultaneously. At this time, for the level shift circuit in the related art, when the voltage of VDDIO is smaller, the drain current of the PMOS transistor 2 is correspondingly smaller, so that the speed of the charge flowing from the power supply terminal VDDIO to the node b is greatly reduced, that is, the pull-up capability of the charge at the node b is weaker. At this time, when the PMOS transistor 2 and the NMOS transistor 4 are turned on simultaneously, compared with the situation that the charge pull-up capability at the node b is weak when the voltage of the power supply terminal VDDIO is small, the pull-down capability of the charge at the node b is strong by the NMOS transistor 4, so that the phenomenon that the charge pull-down capability at the node b is far greater than the charge pull-up capability can occur. When the PMOS transistor 2 and the NMOS transistor 4 are turned on simultaneously, the speed of the charge flowing to the node b through the PMOS transistor 2 is lower than the speed of the charge flowing from the node b through the NMOS transistor 4, so that the time required for the charge at the node b (i.e. the output terminal Out) to reach the high level signal is longer, and the charge cannot be quickly turned over to the high level signal. At this time, if the signal inversion speed of the input signal is high, the output terminal Out may not output a high-level signal, which may affect the circuit function of the subsequent circuit.

Similarly, due to the short delay between the input signal and the output signal, when the signal at the output end is turned from the high level signal to the low level signal, the PMOS transistor 2 and the NMOS transistor 4 are turned on simultaneously. At this time, for the level shift circuit in the related art, when the voltage of VDDIO is larger, the drain current of the PMOS transistor 2 is correspondingly larger, so that the speed of the charge flowing from the power supply terminal VDDIO to the node b is greatly improved, that is, the pull-up capability of the charge at the node b is stronger. At this time, when the PMOS transistor 2 and the NMOS transistor 4 are turned on simultaneously, the pull-down capability of the charge at the node b is far smaller than the pull-up capability of the charge, so that the signal at the node b cannot be turned over to the low level signal rapidly. Based on this, if the signal flip speed of the input signal is high, the output terminal Out is most likely unable to output a low level signal, so that the subsequent circuit will be affected to realize the circuit function.

And, it should be further noted that, when the voltage of the power supply terminal VDDIO is larger, the drain current of the PMOS transistor 2 is larger, and when the PMOS transistor 2 is turned on and the NMOS transistor 4 is turned off, the speed of the electric charge flowing from the power supply terminal VDDIO to the node b is also faster, that is, the pull-up capability of the electric charge at the node b is stronger, so that the node b can accumulate more electric charge and output a high-level signal. At this time, if the output terminal Out (i.e., the node b) is turned from the high level signal to the low level signal later, the PMOS transistor 2 is turned off and the NMOS transistor 4 is turned on, so that the NMOS transistor 4 pulls down the charge at the node b. However, compared to the situation that the voltage at the power supply terminal VDDIO is larger, so that the pull-up capability of the charge at the node b is stronger, the pull-down capability of the charge at the node b is weaker by the NMOS transistor 4, and the phenomenon that the pull-down capability of the charge at the node b is far smaller than the pull-up capability of the charge occurs, so that the time required for the charge signal at the node b (i.e., the output terminal Out) to become a low level signal is longer, and the signal cannot be quickly flipped to the low level signal. At this time, if the signal inversion speed of the output signal is high, the output terminal Out cannot output a low level signal, so that the operation of the subsequent circuit is affected.

In addition, based on the symmetry of the level conversion circuit, when the voltage of VDDIO is larger or smaller and the signal inversion speed of the input signal is faster, the node a cannot successfully realize the inversion of the high-low level signal, so that the on and off of the PMOS transistor 2 cannot be reasonably controlled, and the node b cannot successfully output the low-level signal or the high-level signal, so that the level conversion cannot be realized.

It is known that the level shifter circuit in the related art cannot adjust the pull-down capability. Thus, when VDDIO changes the pull-up capability of the level shifter circuit greatly due to a large change amplitude, there is a gap between the pull-up capability and the pull-down capability of the level shifter circuit, so that the flip-up speed of the high level and the low level of the output signal is slower. At this time, when the signal inversion speed of the input signal is high, the output end of the input signal cannot successfully invert the high-low level signal.

The present invention is directed to a level shifter circuit for solving the above-mentioned problems. The level shifter circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Fig. 2 is a schematic structural diagram of a level shifter circuit according to an embodiment of the present invention, as shown in fig. 2, where the circuit includes: the first pull-up transistor P1, the second pull-up transistor P2, the inverter 01, at least one first pull-down transistor N1 (illustrated by way of example as including one in the present invention), at least one first regulating circuit 02 (illustrated by way of example as including one in the present invention), at least one second pull-down transistor N2 (illustrated by way of example as including one in the present invention), and at least one second regulating circuit 03.

The gate of the first pull-down transistor N1 is connected to the input terminal In, the source of the first pull-down transistor N1 is grounded, and the drain of the first pull-down transistor N1 is connected to the first node a. An input end of the inverter 01 is connected with a gate of the first pull-down transistor N1, and an output end of the inverter 01 is connected with a gate of the second pull-down transistor N2. The source electrode of the second pull-down transistor N2 is grounded, and the drain electrode of the second pull-down transistor N2 is connected with the second node B. The drain electrode of the first pull-up transistor P1 is connected with the first node A, the grid electrode of the first pull-up transistor P1 is connected with the second node B, and the source electrode of the first pull-up transistor P1 is connected with the power supply end VDDIO. The drain electrode of the second pull-up transistor P2 is connected to the second node B, the gate electrode of the second pull-up transistor P2 is connected to the first node a, and the source electrode of the second pull-up transistor P2 is connected to the power supply terminal VDDIO.

In this embodiment, the polarities of the first pull-down transistor N1 and the second pull-down transistor N2 are the same, the polarities of the first pull-up transistor P1 and the second pull-up transistor P2 are the same, and the polarities of the first pull-down transistor N1 and the first pull-up transistor P1 are opposite. For example, the first pull-down transistor and the second pull-down transistor may be NMOS transistors, and the first pull-up transistor and the second pull-up transistor may be PMOS transistors.

And, with continued reference to fig. 2, a first port of the first adjusting circuit 02 is connected to the first node a, a second port of the first adjusting circuit 02 is grounded, and a third port of the second adjusting circuit 02 is connected to the first signal terminal 04. A first port of the second adjusting circuit 03 is connected to the second node B, a second port of the first adjusting circuit 03 is grounded, and a third port of the second adjusting circuit 03 is connected to the second signal terminal 05.

The first signal terminal 04 is mainly used for controlling the on/off of the first adjusting circuit 02, and the second signal terminal 05 is mainly used for controlling the on/off of the second adjusting circuit 03, so as to adjust the pull-down capability of the level shifter circuit.

Specifically, when the voltage of the power supply terminal VDDIO is greater than or equal to the predetermined voltage, so that the pull-up capability of the level shifter circuit for the charges at the first node a and the second node B is improved, the first signal terminal 04 is configured to provide an on voltage to the first regulator circuit 02, so that the first regulator circuit 02 is turned on, so as to improve the pull-down capability of the level shifter circuit for the charges at the first node a, so that the pull-up capability and the pull-down capability of the level shifter circuit for the charges at the first node a are mutually matched, and the situation that the pull-up capability is far greater than the pull-down capability is avoided, thereby enabling the signal at the first node a to be quickly flipped to a low-level signal. And the second signal terminal 05 is configured to provide an on voltage to the second adjusting circuit 03, so that the second adjusting circuit 03 is turned on to improve a pull-down capability of the level shifter circuit to the charge at the second node B, so that the pull-up capability and the pull-down capability of the level shifter circuit to the charge at the second node B are matched with each other, and a situation that the pull-up capability is far greater than the pull-down capability is avoided, so that the signal of the second node B can be quickly flipped to a low level signal.

When the voltage of the power supply terminal VDDIO is smaller than a predetermined voltage, so that the pull-up capability of the level shifter circuit for the charges at the first node a and the second node B is reduced, the first signal terminal 04 is configured to provide a cut-off voltage to the first regulator circuit 02, so that the first regulator circuit 02 is disconnected, the pull-down capability of the level shifter circuit for the charges at the first node a is reduced, the pull-up capability and the pull-down capability of the level shifter circuit for the charges at the first node a are matched with each other, and the situation that the pull-up capability is far smaller than the pull-down capability is avoided, so that the signal of the first node can be quickly flipped to a high level signal. And the second signal terminal 05 is configured to provide a cut-off voltage to the second adjusting circuit 03, so that the second adjusting circuit 03 is turned off, and the pull-down capability of the level conversion circuit on the charge at the second node B is reduced, so that the pull-up capability and the pull-down capability of the level conversion circuit on the charge at the second node B are matched with each other, the situation that the pull-up capability is far smaller than the pull-down capability is avoided, and the signal of the second node B can be quickly flipped to a high level signal.

In this embodiment, when the voltage of the power supply terminal VDDIO is equal to or greater than a predetermined voltage, the first adjusting circuit and the second adjusting circuit are not always turned on. Specifically, when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage and the first pull-down transistor N1 is turned on, the first adjusting circuit 02 is turned on, otherwise, the first adjusting circuit 02 is turned off. And when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage and the second pull-down transistor N2 is turned on, the second regulating circuit 03 is turned on, otherwise, the second regulating circuit 03 is turned off.

And, further, in this embodiment, the range of the predetermined voltage should be between the operating voltage range of the integrated circuit chip, and the integrated circuit chip is specifically a chip including the level shifter circuit in the present invention. And, it should be appreciated that different integrated circuit process nodes correspond to different operating voltages, and that the diverse product requirements require that the same integrated circuit chip be provided with multiple operating voltages. Based on this, the predetermined voltage is reasonably valued between the minimum operating voltage and the maximum operating voltage of the integrated circuit chip. For example, the predetermined voltage may be between 2 and 3V when the integrated circuit chip is a 55nm process.

Therefore, for the level conversion circuit, no matter the voltage of the power supply end is larger or smaller, the output end of the level conversion circuit can realize the rapid turning of the high level and the low level, and at the moment, even if the signal turning speed of the input signal of the input end is higher, the level conversion circuit can be ensured to output the correct signal so as to ensure that the subsequent circuit can normally operate.

Further, the first adjusting circuit 02 and the second adjusting circuit 03 will be described in detail. As shown in fig. 2, in the present embodiment, the first adjusting circuit 02 may include a first switching transistor N3 and a first adjusting transistor N4 connected in series, and the second adjusting circuit 03 may include a second switching transistor N5 and a second adjusting transistor N6 connected in series.

The drain of the first switching transistor N3 is connected to the first node a as a first port of the first adjusting circuit 02, the gate of the first switching transistor N3 is connected to the first signal terminal 04 as a third port of the first adjusting circuit 02, the source of the first switching transistor N3 is connected to the drain of the first adjusting transistor N4, the gate of the first adjusting transistor N4 is connected to the gate of the first pull-down transistor N1, and the source of the first adjusting transistor N4 is grounded as a second port of the first adjusting circuit 02.

The drain electrode of the second switching transistor N5 is connected to the second node B as the first port of the second adjusting circuit 03, the gate electrode of the second switching transistor N5 is connected to the second signal terminal 05 as the third port of the second adjusting circuit 03, the source electrode of the second switching transistor N5 is connected to the drain electrode of the second adjusting transistor N6, the gate electrode of the second adjusting transistor N5 is connected to the gate electrode of the second pull-down transistor N2, and the source electrode of the second adjusting transistor N5 is grounded as the second port of the second adjusting circuit 03.

In this embodiment, when the first pull-down transistor N1 is turned on, the first adjusting transistor N3 should also be turned on; when the second pull-down transistor N2 is turned on, the second adjusting transistor N5 should also be turned on. Based on this, in the present embodiment, the polarities of the first adjusting transistor N3 and the first pull-down transistor N1 may be made the same, and the polarities of the second adjusting transistor N5 and the second pull-down transistor N2 may be made the same, for example, the first adjusting transistor and the second adjusting transistor may be NMOS transistors.

In addition, it should be noted that, in this embodiment, the first signal terminal 04 and the second signal terminal 04 may be both connected to the power supply terminal VDDIO. The first signal terminal 04 and the second signal terminal 05 may further include a comparison circuit, in which a value of a predetermined voltage is stored, the predetermined voltage may be specifically stored in the comparison circuit through an external input or a manner set by an internal circuit, and the comparison circuit in the first signal terminal and the second signal terminal may be configured to receive a voltage value of the power supply terminal VDDIO and compare the voltage value with the predetermined voltage, so as to control the first switching transistor N3 or the second switching transistor N5 to be turned on or off.

Specifically, in this embodiment, when the first signal terminal 04 and the second signal terminal 05 determine that the voltage of the power supply terminal VDDIO is greater than or equal to the predetermined voltage, the first signal terminal 04 is configured to input an on voltage to the gate of the first switching transistor N3, so that the first switching transistor N3 is turned on; the second signal terminal 05 is configured to input an on voltage to the gate of the second switching transistor N5, so that the second switching transistor N5 is turned on.

And when the first signal terminal 04 and the second signal terminal 05 determine that the voltage of the power supply terminal VDDIO is less than the predetermined voltage, the first signal terminal 04 is configured to output an off voltage to the gate of the first switching transistor N3, so that the first switching transistor N3 is turned off; the second signal terminal 05 is configured to output an off voltage to the gate of the second switching transistor N5, so that the second switching transistor N5 is turned off.

In this embodiment, the first signal terminal 04 and the second signal terminal 05 may be specifically the same signal terminal. And the first switching transistor N3 and the second switching transistor N5 have the same polarity, for example, both may be NMOS transistors.

In addition, in this embodiment, the first signal terminal 04 and the second signal terminal 05 may implement the functions thereof by directly connecting VG signals or digital circuits externally, which is not specifically limited herein.

Based on the above, the principles of the level shift circuit in this embodiment will be described by taking the first pull-up transistor P1 and the second pull-up transistor P2 as PMOS transistors, and taking the first pull-down transistor N1, the first pull-down transistor N2, the first switch transistor N3, the first adjustment transistor N4, the second switch transistor N5, and the second adjustment transistor N6 as NMOS transistors as examples:

The description is first directed to the case where the power supply voltage VDDIO is larger.

Specifically, when the voltage VDDIO of the power supply terminal is greater than or equal to the predetermined voltage, if the input voltage of the input terminal In is a low level signal, the gates of the first pull-down transistor N1 and the first adjusting transistor N4 receive the low level signal, and the first pull-down transistor N1 and the first adjusting transistor N4 are turned off, so that the first adjusting circuit 02 is turned off. And the low level signal is inverted to a high level signal via the inverter 01 and is input to gates of the second pull-down transistor N2 and the second adjustment transistor N6, and the second pull-down transistor N2 and the second adjustment transistor N6 are turned on.

And, when the voltage of the power supply terminal VDDIO is greater than or equal to the predetermined voltage, the first signal terminal 04 outputs an on voltage to the gate of the second switching transistor N5, so that the second switching transistor N5 is turned on. The second regulating transistor N6, the second switching transistor N5 and the second pull-down transistor N2 are thereby all turned on. Then both the second regulating circuit 03 and the second pull-down transistor N2 are turned on at the same time and both pull down the charge at the second node B to a low signal at the same time. The first pull-up transistor P1 is turned on, the charge at the first node a is pulled up to a high level signal, the second pull-up transistor P2 is turned off, and the output terminal Out outputs a low level signal.

And when the voltage VDDIO of the power supply terminal is greater than or equal to a predetermined voltage, if the input voltage of the input terminal In is the high level signal VDDC, the gates of the first pull-down transistor N1 and the first adjusting transistor N4 receive the high level signal, and the first pull-down transistor N1 and the first adjusting transistor N4 are turned on. The gates of the second pull-down transistor N2 and the second adjusting transistor N6 receive a low level signal, and the second pull-down transistor N2 and the second adjusting transistor N6 are turned off, so that the second adjusting circuit 03 is turned off. And, since the first signal terminal 04 outputs the turn-on voltage to the gate of the first switching transistor N3 when the voltage of the power terminal is equal to or greater than the predetermined voltage, the first switching transistor N3 is turned on. Thus, the first adjusting NMOS transistor N4, the first switching transistor N3, and the first pull-down transistor N1 are all turned on, that is, both the first adjusting circuit 02 and the first pull-down transistor N1 are turned on at the same time, and both pull-down the charge at the first node a to the low level signal at the same time. The second pull-up transistor P2 is turned on, pulls up the charge at the second node B to a high signal and outputs it, and the first pull-up transistor P1 is turned off.

It should be noted that, before the signal of the second node B toggles to the low level signal, the second pull-up transistor P2 and the second pull-down transistor N2 are turned on simultaneously due to signal delay. At this time, when the voltage at the power supply terminal is larger, the speed of the charge at the power supply terminal VDDIO flowing to the second node B is also larger, so that the pull-up capability of the level shifter circuit to the charge at the second node B is stronger. Based on this, in the present embodiment, when the voltage of the power supply terminal is larger, the second adjusting circuit 03 is turned on simultaneously with the second pull-down transistor N2, so that the potential at the second node B is pulled down by both the second pull-down transistor N2 and the second adjusting circuit 03, the pull-down capability is also stronger, and the pull-down capability and the pull-up capability are matched with each other. Based on this, when the second pull-up transistor P2 and the second pull-down transistor N2 are turned on at the same time, the situation that the pull-down capability of the charge at the second node B is far smaller than the pull-up capability can be avoided, so that the charge at the second node B is quickly pulled down to the low level signal, and the output terminal Out (i.e., the second node B) can realize quick inversion of the low level signal of the output terminal.

And, similarly, before the signal of the first node a is inverted to a low level signal, the first pull-up transistor P1 and the first pull-down transistor N1 are simultaneously turned on due to signal delay. At this time, when the voltage of the power supply terminal is large, the level shifter circuit has a strong pull-up capability on the charge at the first node a. In this embodiment, when the voltage at the power supply terminal is large, the first regulator circuit 02 is enabled to pull down the charge at the first node a along with the simultaneous turn-on of the first pull-down transistor N1, so as to improve the pull-down capability of the level shifter circuit for the charge at the first node a, and enable the pull-down capability and the pull-up capability to match each other. Thus, when the first pull-up transistor P1 and the first pull-down transistor N1 are turned on at the same time, the situation that the pull-down capability of the charge at the first node a is far smaller than the pull-up capability can be avoided, so that the charge at the first node a is quickly pulled down to a low-level signal, and further, the second pull-up transistor P2 can be turned on faster, so that the charge at the second node B can be quickly pulled up to a high-level signal VDDIO to be output, and the quick turn-over of the high-level signal at the output end is realized.

As can be seen from the foregoing, in the level shifter circuit of this embodiment, when the power supply terminal VDDIO is greater than or equal to the predetermined voltage, and the pull-up capability of the level shifter circuit is stronger, by making the first regulator circuit 02 and the second regulator circuit 03 conductive, the pull-down capability of the level shifter circuit to the charges at the first node a and the second node B can be flexibly adjusted, so that the pull-down capability of the level shifter circuit to the charges at the first node a and the second node B is correspondingly stronger, and the phenomenon that the pull-down capability is far smaller than the pull-up capability is avoided, so that the charges at the first node a and the second node B can be successfully turned to the low-level signal in a short time, and the output terminal Out can be quickly turned to high-low level. Therefore, even if the signal turning speed of the input signal is high, the output end Out can still successfully realize the turning of the high-low level signal, so that the correct signal is output, and the operation of a subsequent circuit is ensured.

Further, the following description is made with respect to the case where the power supply terminal voltage VDDIO is smaller.

Specifically, when the power supply terminal VDDIO is smaller and smaller than the predetermined voltage, or when the voltage of VDDIO is smaller than (normal operating voltage-normal operating voltage×a preset percentage), the preset percentage may be between 8% and 12%, for example, may be 10%, and the normal operating voltage may be the normal operating voltage of the integrated circuit chip. If the input signal at the input terminal In is a high level signal, the second pull-down transistor N2 and the second adjusting transistor N6 are turned off, and the second adjusting circuit 03 is turned off. The first pull-down transistor N1 and the first adjustment transistor N4 are turned on. Meanwhile, since the first signal terminal 04 outputs the off voltage to the gate of the first switching transistor N3 when the voltage of the power supply terminal is less than the predetermined voltage, the first switching transistor N3 is turned off, so that the first adjusting circuit 02 is turned off. At this time, only the first pull-down transistor N1 pulls down the charge at the first node a to a low level signal, the second pull-up transistor P2 is turned on, the charge at the second node B is pulled up to a high level signal and output from the output terminal Out, and the first pull-up transistor P2 is turned off.

And when the power supply terminal VDDIO is smaller than a predetermined voltage, or when the voltage of VDDIO is smaller than (normal operation voltage-normal operation voltage×preset percentage). If the signal In is a low level signal, the first pull-down transistor N1 and the first adjusting transistor N4 are turned off, the first adjusting circuit 02 is turned off, and the second pull-down transistor N2 and the second adjusting transistor N6 are turned on. Meanwhile, since the second signal terminal 05 outputs the off voltage to the gate of the second switching transistor N5 when the voltage of the power terminal is less than the predetermined voltage, the second switching transistor N5 is turned off, so that the second adjusting circuit 03 is turned off. At this time, only the second pull-down transistor N2 pulls down the charge at the second node B to a low level signal, the first pull-up transistor P1 is turned on, the charge at the first node a is pulled up to a high level signal, the second pull-up transistor P2 is turned off, and the second node B outputs a low level signal.

In this embodiment, before the signal at the second node B is pulled up to the high level signal, the second pull-up transistor P2 and the second pull-down transistor N2 are turned on simultaneously due to the signal delay. At this time, if the voltage of the power supply terminal is smaller, the speed of the charge at the power supply terminal VDDIO flowing to the second node B is smaller, so that the pull-up capability of the level conversion circuit for the charge at the second node B is smaller. At this time, in the present embodiment, the second adjusting circuit 03 is turned off, and the level shifter circuit only pulls down the charge at the second node B by the second pull-down transistor N2, so that the pull-down capability is correspondingly smaller, and the pull-down capability and the pull-up capability are matched with each other. Therefore, when the second pull-up transistor P2 and the second pull-down transistor N2 are simultaneously turned on, the phenomenon that the charge pull-down capability of the second node B is far greater than the pull-up capability can be avoided, so that the signal of the second node B can be quickly turned over to the high-level signal VDDIO to be output, and the quick turning over of the high-level signal of the output end is realized.

And, similarly, before the signal at the first node a is pulled up to the high level signal, a phenomenon that the first pull-up transistor P1 and the first pull-down transistor N1 are simultaneously turned on occurs due to a signal delay. At this time, if the voltage VDDIO of the power supply terminal is smaller, the level shifter circuit will have smaller pull-up capability on the charge at the first node a. At this time, in the present embodiment, the first adjusting circuit 02 is turned off, and the charge at the first node a is pulled down only by the first pull-down transistor N1 in the level shifter circuit, and the pull-down capability thereof is correspondingly smaller, so that the pull-down capability and the pull-up capability are matched with each other. So when first pull-up transistor P1 and first pull-down transistor N1 switch on simultaneously, can avoid appearing the phenomenon that the electric charge pull-down ability of first node A department is greater than electric charge pull-up ability far away for first node A's signal can overturn fast to high level signal VDDIO, thereby make second pull-up transistor P2 can cut off at sooner, make the signal of second node department overturn fast to low level signal and output, realize the quick upset of the low level signal of output.

As can be seen from the above description, in the level shifter circuit of the present invention, when the power supply terminal VDDIO is smaller and the pull-up capability of the level shifter circuit is weaker, the first adjusting circuit and the second adjusting circuit can be disconnected to flexibly adjust the pull-down capability of the level shifter circuit, so that the pull-down capability of the level shifter circuit is correspondingly weaker, and the situation that the pull-up capability of the level shifter circuit is far smaller than the pull-down capability can be avoided, so that the output terminal Out can quickly realize the high-low level flip. Therefore, even if the signal turning speed of the input signal is high, the output end Out can successfully realize the turning of the high-low level signal, so that the correct signal is output, and the operation of a subsequent circuit is ensured.

In addition, it should be noted that in this embodiment, the first adjusting circuit may include only the first switching transistor, and the second adjusting circuit may include only the second switching transistor, where the first signal terminal and the second signal terminal are not the same signal terminal. And when the voltage VDDIO of the power supply end is larger than or equal to a preset voltage and the first pull-down transistor N1 is turned on, the first signal end is used for inputting an on voltage to the first switch transistor so as to enable the first switch transistor to be turned on, and otherwise, the first signal end is used for outputting an off voltage to the first switch transistor so as to enable the first switch transistor to be turned off. And when the voltage VDDIO of the power supply terminal is greater than or equal to a predetermined voltage, and when the second pull-down transistor N2 is turned on, the second signal terminal is configured to input an on voltage to the second switching transistor to turn on the second switching transistor, and otherwise, the second signal terminal is configured to output an off voltage to the second switching transistor to turn off the second switching transistor. And when the voltage VDDIO of the power supply terminal is smaller than a preset voltage, the first signal terminal is used for inputting a cut-off voltage to the first switching transistor, and the second signal terminal is used for inputting the cut-off voltage to the second switching transistor.

Optionally, in this embodiment, the first adjusting transistor and the second adjusting transistor have the same size, and the first switching transistor and the second switching transistor have the same size; the first pull-down transistor and the second pull-down transistor are the same size; the first pull-up transistor and the second pull-up transistor are the same size; the substrate end of the first pull-up transistor is connected with the source electrode of the first pull-up transistor; the substrate end of the second pull-up transistor is connected with the source electrode of the second pull-up transistor; the substrate end of the first pull-down transistor is connected with the source electrode of the first pull-down transistor and grounded; the substrate end of the second pull-down transistor is connected with the source electrode of the second pull-down transistor and grounded.

Therefore, for the level conversion circuit, when the voltage change amplitude of the power supply end is large so that the pull-up capacity of the level conversion circuit is greatly reduced or improved, the pull-down capacity of the level conversion circuit can be flexibly adjusted correspondingly by controlling the connection or disconnection of the first regulating circuit and the second regulating circuit, so that the situation that the pull-up capacity and the pull-down capacity of the level conversion circuit are far apart is avoided, and the output end can be ensured to rapidly output a high-level signal or a low-level signal in a short time. Even if the signal turning speed of the input signal is high, the output end can be ensured to successfully realize the turning of the high level and the low level, so that the level conversion circuit can adapt to the diversified requirements of the current chip products.

In addition, the level conversion circuit has a simpler structure.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A level shifter circuit, the circuit comprising: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first regulation circuit, at least one second pull-down transistor, at least one second regulation circuit;

When the voltage of the power supply end is larger than or equal to a preset voltage and the input voltage of the input end is a high-level signal, the second regulating circuit is disconnected, and the first signal end is used for providing an opening voltage for the first regulating circuit so as to enable the first regulating circuit to be conducted, so that the output signal of the first node can be turned to a low-level signal; when the voltage of the power supply end is larger than or equal to a preset voltage and the input voltage of the input end is a low-level signal, the first regulating circuit is disconnected, and the second signal end is used for providing an opening voltage for the second regulating circuit so as to enable the second regulating circuit to be conducted, so that the output signal of the second node can be turned to the low-level signal;

2. The level shifter circuit of claim 1, wherein the first regulator circuit includes a first switching transistor and a first regulator transistor in series with each other, and the second regulator circuit includes a second switching transistor and a second regulator transistor in series with each other;

When the voltage of the power supply end is larger than or equal to the preset voltage, the first signal end is used for inputting an opening voltage to the grid electrode of the first switching transistor so as to enable the first switching transistor to be opened; the second signal end is used for inputting an opening voltage to the grid electrode of the second switching transistor so as to enable the second switching transistor to be opened;

3. The level shifting circuit of claim 2, wherein the first pull-down transistor is of the same polarity as the second pull-down transistor, the first pull-up transistor is of the same polarity as the second pull-up transistor, and the first pull-down transistor and the first pull-up transistor are of opposite polarity.

4. The level shifter circuit of claim 3, wherein the first adjustment transistor and the first pull-down transistor are of the same polarity and the second adjustment transistor and the second pull-down transistor are of the same polarity.

5. The level shifter circuit of claim 4, wherein the first pull-down transistor and the second pull-down transistor are NMOS transistors, wherein the first pull-up transistor and the second pull-up transistor are PMOS transistors, and wherein the first adjustment transistor and the second adjustment transistor are NMOS transistors.

6. The level shifter circuit of claim 2, wherein the first signal terminal and the second signal terminal are the same signal terminal.

7. The level shifter circuit of claim 2, wherein the first switching transistor and the second switching transistor are of the same polarity.

8. The level shifter circuit of claim 7, wherein the first switching transistor and the second switching transistor are NMOS transistors.

9. The level shifter circuit of claim 2, wherein the first signal terminal and the second signal terminal each include a comparison circuit, and wherein the first signal terminal and the second signal terminal are each connected to the power terminal for receiving a voltage value of the power terminal and comparing the voltage value with a predetermined voltage.

10. The level shifter circuit of claim 1, wherein the first pull-down transistor and the second pull-down transistor are the same size; the first pull-up transistor and the second pull-up transistor are the same size.