WO2021189282A1 - Circuit d'attaque et puce associée - Google Patents

Circuit d'attaque et puce associée Download PDF

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Publication number
WO2021189282A1
WO2021189282A1 PCT/CN2020/081033 CN2020081033W WO2021189282A1 WO 2021189282 A1 WO2021189282 A1 WO 2021189282A1 CN 2020081033 W CN2020081033 W CN 2020081033W WO 2021189282 A1 WO2021189282 A1 WO 2021189282A1
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WO
WIPO (PCT)
Prior art keywords
transistor
current
gate
driving circuit
circuit
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PCT/CN2020/081033
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English (en)
Chinese (zh)
Inventor
李宗隆
范铨奇
徐建昌
Original Assignee
深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN202080001681.7A priority Critical patent/CN111936949A/zh
Priority to PCT/CN2020/081033 priority patent/WO2021189282A1/fr
Publication of WO2021189282A1 publication Critical patent/WO2021189282A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • This application relates to a circuit, in particular to a driving circuit and related chips.
  • the interface of the integrated circuit usually needs to comply with some design specifications of electronic components.
  • a general-purpose input/output interface (general-purpose input/output) needs to comply with the design specifications of electromagnetic interference (EMI). Therefore, an innovative design is needed to reduce the EMI of the existing interface.
  • EMI electromagnetic interference
  • One of the objectives of the present application is to disclose a circuit, especially a driving circuit and related chips, to solve the above-mentioned problems.
  • An embodiment of the present application discloses a driving circuit: including a logic circuit, a push-pull circuit, and a control circuit, wherein the logic circuit is used to generate a data signal;
  • the push-pull circuit includes: a first transistor for When the data signal transitions from the first logic state to the second logic state, the potential of the output terminal of the driving circuit is transitioned from the first potential corresponding to the first logic state to the corresponding state during the first transition period.
  • the second potential of the second logic state the control circuit, coupled to the push-pull circuit, is used during the first transition period, before the potential of the output terminal reaches the second potential,
  • the current flowing through the first transistor is controlled to be a first constant current.
  • An embodiment of the present application discloses a chip including the aforementioned driving circuit.
  • the driving circuit disclosed in the present application can control the current flowing through the turned-on pull-up transistor or the turned-on pull-down transistor to a constant current. Accordingly, during each on period, the slew rate of the pull-up transistor and the pull-down transistor can be controlled to improve the EMI problem.
  • the circuit diagram of FIG. 1A illustrates the charging operation of the driving circuit.
  • the voltage waveform diagram of FIG. 1B illustrates the relationship between the voltage at the output terminal of the driving circuit and the time during the operation of charging the equivalent capacitor.
  • the circuit diagram of FIG. 1C illustrates the discharging operation of the driving circuit.
  • the voltage waveform diagram of FIG. 1D illustrates the relationship between the voltage at the output terminal of the driving circuit in the operation of discharging the equivalent capacitance with respect to time.
  • FIG. 2A illustrates the charging operation of the driving circuit of the present application.
  • the voltage waveform diagram of FIG. 2B illustrates the relationship between the voltage at the output terminal of the driving circuit of FIG. 2A during the operation of charging the equivalent capacitor with respect to time.
  • FIG. 2C illustrates the discharging operation of the driving circuit of the present application.
  • the voltage waveform diagram of FIG. 2D illustrates the relationship between the voltage at the output terminal of the driving circuit of FIG. 2C in the operation of discharging the equivalent capacitance with respect to time.
  • FIG. 3 is a circuit diagram of yet another embodiment of the driving circuit of the application.
  • FIG. 4 is a circuit diagram of still another embodiment of the driving circuit of the application.
  • FIG. 5 is a circuit diagram of another embodiment of the driving circuit of the application.
  • first and second features are in direct contact with each other; and may also include
  • additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • present disclosure may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing in the figure
  • the relationship between one component or feature relative to another component or feature is shown.
  • the original meaning of these spatially-relative vocabulary covers not only the orientation shown in the figure, but also the various orientations of the device in use or operation.
  • the device may be placed in other orientations (for example, rotated 90 degrees or in other orientations), and these spatially-relative description vocabulary should be explained accordingly.
  • input/output interfaces such as general-purpose input/output (GPIO)
  • GPIO general-purpose input/output
  • the equivalent capacitance seen at the output terminal of the input/output interface is charged or discharged through the transistor, so that the input/output interface outputs a high potential or a low potential.
  • FIGS. 1A and 1C illustrate the charging operation and the discharging operation of the driving circuit 100, respectively.
  • the driving circuit 100 includes a logic circuit 110 and a push-pull circuit 120.
  • the push-pull circuit 120 includes a P-type transistor M1 and an N-type transistor M2, which are connected in series between a specific voltage VDD and VSS.
  • the source and drain of the transistor M1 are respectively coupled to a specific voltage VDD and the drain of the transistor M2, and the source of the transistor M2 is coupled to a specific voltage VSS.
  • the specific voltages VDD and VSS have the same magnitude and opposite polarities.
  • the specific voltage VSS is the reference ground.
  • the logic circuit 110 is coupled to the transistors M1 and M2, and is used to turn on only one of the transistors M1 and M2 at any time according to the enable signal EN and the data signal D (ie, the transistors M1 and M2 are not turned on at the same time).
  • the logic circuit 110 includes a NOT gate 112, a NAND gate 114, and a NOR gate 116.
  • the data signal D is transmitted to the gates of the transistors M1 and M2 via the NAND gate 114 and the NOR gate 116, respectively.
  • the NAND gate 114 based on the enable signal EN of logic 1, the NAND gate 114 reverses the logic state of the received data signal D, and then outputs the reversed data signal D to the gate of the transistor M1.
  • the NOR gate 116 inverts the logic state of the received data signal D, and then outputs the inverted data signal D to the gate of the transistor M2.
  • the drains of the transistor M1 and M2 form the output terminal OUT.
  • the transistor M2 is not conducting and the transistor M1 is conducting.
  • the transistor M1 uses a specific voltage VDD to charge the equivalent capacitance CL seen at the output terminal OUT to charge the output
  • the potential of the terminal OUT changes from the first potential (approximately VSS, corresponding to logic 0) to the second potential (approximately VDD, corresponding to logic 1) during the rising transition period.
  • the rising transition period refers to a period in which the potential continues to rise, and does not include a period in which the potential remains at the second potential after reaching the second potential without further rising.
  • the transistor M2 when the transistor M1 is not conducting and the transistor M2 is conducting, the transistor M2 uses a specific voltage VSS to discharge the equivalent capacitor CL to change the potential of the output terminal OUT from the second potential (approximately VDD) during the falling transition period. ) Transition to the first potential (approximately VSS).
  • the falling transition period refers to a period in which the potential continues to fall, and does not include a period in which the potential remains at the first potential after reaching the first potential and does not continue to fall.
  • FIG. 1B and FIG. 1D respectively illustrate the relationship between the voltage of the output terminal OUT of the driving circuit 100 during the charging operation and the discharging operation of the equivalent capacitor CL with respect to time.
  • the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 100
  • the horizontal axis represents time.
  • FIGS. 2A and 2C illustrate the charging operation and the discharging operation of the driving circuit 200, respectively.
  • the driving circuit 200 is similar to the driving circuit 100 of FIG. 1A, except that the driving circuit 200 further includes a control circuit 210, which is coupled to the push-pull circuit 120.
  • the control circuit 210 includes a current source Ir and a current tank Ik.
  • the current source Ir receives a specific voltage VDD and is coupled to the source of the transistor M1.
  • the transistor M2 is not turned on and the transistor M1 is turned on.
  • the current source Ir is used to continuously provide a constant current ics1 through the transistor M1 to the output terminal OUT during the on period of the transistor M1 to charge the equivalent capacitor CL.
  • the current source Ir controls the current flowing through the transistor M1 to a constant current ics1.
  • the constant current means that the magnitude of the current does not change with time.
  • the current source Ir can be implemented by a single P-type transistor, wherein the source of the P-type transistor receives a specific voltage VDD, the gate is controlled by the control voltage, and the drain is coupled to the source of the transistor M1 pole.
  • the current tank Ik receives a specific voltage VSS and is coupled to the source of the transistor M2.
  • the transistor M1 is not turned on and the transistor M2 is turned on, and the current tank Ik is used to continuously draw a constant current ics2 from the output terminal OUT through the transistor M2 during the on period of the transistor M2 to discharge the equivalent capacitor CL.
  • the current tank Ik controls the current flowing through the transistor M2 to be a constant current ics2.
  • the current tank Ik can be implemented by a single N-type transistor, wherein the source of the N-type transistor receives a specific voltage VSS, the gate is controlled by another control voltage, and the drain is coupled to the transistor M2 Of the source.
  • FIGS. 2B and 2D respectively illustrate the relationship between the voltage at the output terminal OUT of the driving circuit 200 during the charging operation and the discharging operation of the equivalent capacitor CL with respect to time.
  • the voltage on the vertical axis represents the potential of the output terminal OUT of the driving circuit 200
  • the horizontal axis represents time.
  • FIG. 2B the waveform 130 of FIG. 1B is drawn. Comparing the waveforms 230 and 130, it can be observed that the potential of the output terminal OUT indicated by the waveform 230 climbs to Vr at a relatively small absolute value and a substantially fixed slope in the initial charging stage (period dTr) compared to the waveform 130 of FIG. 1B. This means that in the early stage of charging, the drain-source voltage slew rate of the transistor M1 of FIG. 2A is lower than that of the transistor M1 of FIG. 1A.
  • FIG. 2D the waveform 135 in FIG. 1D is drawn. Comparing the waveforms 235 and 135, it can be observed that the potential of the output terminal OUT indicated by the waveform 235 decreases to Vr at a relatively small absolute value and a substantially constant slope compared to the waveform C135 of FIG. 1D at the initial stage of discharge (period dTf). This means that in the early stage of discharge, the drain-source voltage slew rate of the transistor M2 of FIG. 2C is lower than that of the transistor M2 of FIG. 1C.
  • the EMI problems in the initial stage of discharge and the initial stage of charging can be improved, and the EMI can meet the specifications.
  • FIG. 3 is a circuit diagram of an embodiment of the driving circuit 300 of the application. 3, the driving circuit 300 is similar to the driving circuit 200 of FIG. 2A. The difference is that compared with the control circuit 210 of FIG. 2A, the control circuit 310 of the driving circuit 300 further includes: a reference current source Iref and transistors M3, M4, M5, M6 and M7.
  • a reference current source Iref and transistors M3, M4, M5, M6 and M7.
  • Transistors M3 and M4 form a current mirror. Since this current mirror receives a constant current iref from a reference current source Iref (which may be referred to as a reference constant current where appropriate), this current mirror may be referred to as a source current mirror where appropriate, and transistors M3 and M4 may be referred to as reference where appropriate Transistor.
  • the gate and drain of the transistor M3 are short-circuited and connected to the gate of the transistor M4.
  • the source current mirror replicates the constant current iref received by the transistor M3, and outputs a constant current icof through the transistor M4 (which may be referred to as a replicated constant current where appropriate).
  • the driving circuit 300 also includes other current mirrors, which are described in detail as follows.
  • Transistor M3 and transistor M7 also form a current mirror, which can be called a first current mirror where appropriate.
  • the gate of the transistor M3 is further short-circuited with the gate of the transistor M7.
  • the first current mirror replicates the constant current iref received by the transistor M3, and outputs the constant current ic1 through the transistor M7. Since the transistor M7 provides the function of a current sink, it can also be referred to as a current sink transistor where appropriate.
  • the transistors M5 and M6 constitute a current mirror, which can be called a second current mirror where appropriate.
  • the gate and drain of the transistor M5 are short-circuited and connected to the gate of the transistor M6.
  • the second current mirror copies the constant current icof received by the transistor M5, and outputs the constant current ic2 through the transistor M6. Since the transistor M6 provides the function of a current source, it can also be referred to as a current source transistor where appropriate.
  • the transistor M6 continues to provide a constant current ic2 to the output terminal OUT via the transistor M1.
  • the driving circuit 300 of the present application can improve the problem of EMI in the initial stage of discharge and the initial stage of charging, and make EMI meet the specifications.
  • FIG. 4 is a circuit diagram of an embodiment of the driving circuit 400 of this application.
  • the driving circuit 400 is similar to the driving circuit 300 of FIG. 3, the difference is that compared with the control circuit 310 of FIG. 3, the control circuit 410 of the driving circuit 400 further includes: transistors M8, M9, and M10, and transistors M3 and M5
  • the respective connection modes are different from the respective connection modes of the transistors M3 and M5 of the control circuit 310.
  • each of the transistors M8, M9, and M10 can be used as a resistor, which is described in detail as follows.
  • the circuit operator can change the current gear of the reference current source Iref as needed to adjust the size of the constant current iref, so that the charging and discharging time of the parasitic capacitor CL can meet the specification requirements.
  • the constant currents ic1 and ic2 In order to accurately adjust the charge and discharge time of the parasitic capacitor CL, it is necessary to accurately adjust the constant currents ic1 and ic2.
  • One possible way to achieve this goal is to (1) make the equivalent circuits of constant current iref and ic1 flow as equal as possible to each other; and (2) make the equivalent circuits of constant current iref, icof and ic2 flow as equal to each other as possible .
  • the equivalent circuit through which the constant current ic1 flows is composed of transistors M2 and M7 connected in series, and the transistor M2 receives a voltage equal to the specific voltage VDD. Accordingly, the transistor M8 is added, and the transistor M8 and M3 are connected in series. In addition, in order for the transistor M8 to follow the behavior of the transistor M2 when it is turned on, the gate of the transistor M8 receives a specific voltage VDD. In this way, the equivalent circuits through which the constant currents ic1 and iref flow are as equal as possible to each other.
  • the equivalent circuit through which the constant current ic2 flows is composed of transistors M1 and M6 connected in series, and the transistor M1 receives a voltage equivalent to the specific voltage VSS. Accordingly, the transistor M10 is added, and the transistor M10 and M5 are connected in series. In addition, in order for the transistor M10 to follow the behavior of the transistor M1 when it is turned on, the gate of the transistor M10 receives a specific voltage VSS. In this way, the equivalent circuits through which the constant currents ic2 and icof flow are as equal as possible to each other. In addition, the equivalent circuit through which the constant current iref flows is composed of transistors M3 and M8 connected in series, and the transistor M8 receives a specific voltage VDD.
  • the transistor M9 is added, and the transistor M9 and M4 are connected in series.
  • the gate of the transistor M9 also receives a specific voltage VDD.
  • the equivalent circuits through which the constant current icof and iref flow are as equal as possible to each other.
  • the equivalent circuits through which constant currents iref, icof, and ic2 flow are as equal as possible to each other.
  • the transistor M8 can be referred to as a stacked transistor where appropriate.
  • the impedance value relative to the drain of the transistor M3 is related to the on-resistance of the transistor M8, and the impedance value relative to the drain of the transistor M7 is related to the on-resistance of the transistor M2.
  • the transistor M8 can be used as a resistor.
  • the transistor M10 is added to be stacked in series with the transistor M5. Accordingly, the transistor M10 can be referred to as a stacked transistor where appropriate. Furthermore, the impedance value relative to the drain of the transistor M5 is related to the on-resistance of the transistor M10, and the impedance value relative to the drain of the transistor M6 is related to the on-resistance of the transistor M1. In other words, the transistor M10 can be used as a resistor.
  • the resistance value with respect to the drain of the transistor M4 is made to be the same as the resistance value with respect to the drain of the transistor M3 as much as possible. Therefore, a transistor M9 is added to be stacked in series with the transistor M4. Accordingly, the transistor M9 can be referred to as a stacked transistor where appropriate. Furthermore, the impedance value relative to the drain of the transistor M4 is related to the on-resistance of the transistor M9, and the impedance value relative to the drain of the transistor M3 is related to the on-resistance of the transistor M8. In other words, the transistor M9 can be used as a resistor.
  • the driving circuit 400 of the present application can not only improve the EMI problems in the initial stage of discharge and the initial stage of charging, but also can accurately adjust the constant currents ic1 and ic2.
  • FIG. 5 is a circuit diagram of an embodiment of the driving circuit 500 of the application. 5, the driving circuit 500 is similar to the driving circuit 400 of FIG. 4, the main difference is that the stacking method of the transistor M1 of the push-pull circuit 120 and the transistor M6 of the control circuit 510 is opposite to the stacking method of FIG. The transistor M2 of the pull circuit 120 and the transistor M7 of the control circuit 510 are opposite to the stacking manner of FIG. 4 in the vertical direction.
  • the transistor M1 becomes stacked above the transistor M6, that is, the transistor M1 is coupled between the source of the transistor M6 and the specific voltage VDD.
  • the transistor M2 becomes stacked under the transistor M7, that is, coupled between the source of the transistor M7 and the specific voltage VSS.
  • the transistor M10 in response to the stacking changes of the transistors M1 and M6, the transistor M10 becomes stacked on the transistor M5 and is coupled to the transistor M5. Between the source and a specific voltage VDD. In addition, in order for the transistor M10 to follow the behavior of the transistor M1 when it is turned on, the gate of the transistor M10 receives a specific voltage VSS. In addition, in order to form a current mirror, the drain and gate of the transistor M5 are short-circuited to each other, and the drain of the transistor M5 is also short-circuited to the gate of the transistor M6. Overall, the transistors M5, M6, and M10 form the aforementioned second current mirror.
  • the transistor M3 in response to the stacking changes of the transistors M2 and M7, the transistor M3 becomes stacked above the transistor M8 and is coupled between the reference current source Iref and the drain of the transistor M8.
  • the gate of the transistor M8 receives a specific voltage VDD.
  • the drain and gate of the transistor M3 are short-circuited to each other, and the drain of the transistor M3 is also short-circuited to the gate of the transistor M7.
  • the transistors M3, M7, and M8 form the aforementioned first current mirror.
  • the transistor M4 in response to the stacking changes of the transistors M3 and M8, the transistor M4 becomes stacked above the transistor M9 and coupled between the drain of the transistor M9 and the drain of the transistor M5.
  • the gate of the transistor M9 receives a specific voltage VDD.
  • the gate of the transistor M4 is coupled to the gate of the transistor M3.
  • the transistors M3, M4, M8, and M9 form the aforementioned source current mirror.
  • the driving circuit 500 of the present application can not only improve the EMI problems in the initial stage of discharge and the initial stage of charging, but also can accurately adjust the constant currents ic1 and ic2.
  • the present application also provides a chip, which includes a driving circuit 200, 300, 400, or 500.
  • the chip may be a semiconductor chip realized by a different process.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

La présente invention concerne un circuit d'attaque (200) et une puce associée. Le circuit d'attaque comprend un circuit logique (110), un circuit push-pull (120) et un circuit de commande (210). Le circuit logique est utilisé pour générer un signal de données Le circuit push-pull comprend un premier transistor (M1). Lorsque le signal de données passe d'un premier état logique à un second état logique, le premier transistor est utilisé pour changer, pendant une première période de transition, le potentiel au niveau d'une borne de sortie du circuit d'attaque d'un premier potentiel correspondant au premier état logique en un second potentiel correspondant au second état logique. Le circuit de commande est couplé au circuit push-pull, et commande, pendant la première période de transition et avant que le potentiel au niveau de la borne de sortie atteigne le second potentiel, un courant circulant à travers le premier transistor pour être un premier courant constant (ics1).
PCT/CN2020/081033 2020-03-25 2020-03-25 Circuit d'attaque et puce associée WO2021189282A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080001681.7A CN111936949A (zh) 2020-03-25 2020-03-25 驱动电路以及相关芯片
PCT/CN2020/081033 WO2021189282A1 (fr) 2020-03-25 2020-03-25 Circuit d'attaque et puce associée

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Application Number Priority Date Filing Date Title
PCT/CN2020/081033 WO2021189282A1 (fr) 2020-03-25 2020-03-25 Circuit d'attaque et puce associée

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WO2021189282A1 true WO2021189282A1 (fr) 2021-09-30

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CN101114421A (zh) * 2006-07-26 2008-01-30 松下电器产业株式会社 输出驱动装置及显示装置
CN102186130A (zh) * 2011-02-23 2011-09-14 启攀微电子（上海）有限公司 一种摆率控制驱动电路
CN103066988A (zh) * 2012-12-18 2013-04-24 深圳国微技术有限公司 一种限制输出端电压摆率的接口电路及其实现方法
CN104104380A (zh) * 2013-04-08 2014-10-15 上海山景集成电路股份有限公司 一种低电磁干扰高速率功率开关驱动装置及方法
CN103346774A (zh) * 2013-07-16 2013-10-09 中国科学院上海微系统与信息技术研究所 一种电流模驱动型的抗电磁干扰lin驱动器
CN106774239A (zh) * 2016-11-24 2017-05-31 中国船舶重工集团公司第七六研究所 一种便携式工程车辆车载ecu检测装置

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