JP2008263349A - Output buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of compensating the slew rate of an output signal to stabilize the slew rate against variations in source voltage and temperature and manufacture variance. <P>SOLUTION: The output buffer circuit comprises a buffer, a first voltage detecting circuit which outputs a first detection signal on detecting the voltage of the output signal of the buffer reaching a first voltage during transition of the output signal, a second voltage detecting circuit which outputs a second detection signal on detecting the voltage of the output signal reaching a second voltage, a delay circuit which delays the first detection signal by a predetermined time corresponding to an assumed value of the slew rate of the output signal and outputs the delayed signal, a phase difference detector which detects the phase difference between the second detection signal and delayed signal and outputs a phase difference signal, and a current source which controls current driving power of the buffer according to the phase difference signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an output buffer circuit that controls a slew rate of an output signal (slope when a signal transitions (transition time)) to be constant.

  The transition (rise or fall) of the voltage signal is used for information transmission of the circuit. However, they are not necessarily intended values at the time of design due to variations in power supply voltage, temperature, and manufacturing variations, and there is a problem from the viewpoint of signal quality.

  In a circuit that outputs a signal, if the slew rate of the output signal changes due to manufacturing variations, power supply voltage, or temperature fluctuations, the circuit that receives the signal shifts the timing of the signal and malfunctions or outputs When the rise and fall of the signal become steep, the current change also becomes faster. As a result, there is a problem that not only electromagnetic noise is generated but also EMI (electromagnetic interference) is caused.

  Conventionally, for example, Patent Document 1 proposes an output buffer circuit that controls the slew rate constant regardless of the output load of the buffer. However, there has been no circuit that compensates for the slew rate of the output signal with respect to fluctuations in power supply voltage, temperature, and manufacturing.

JP 2001-285050 A

  An object of the present invention is to provide an output buffer circuit that can solve the problems based on the above-described conventional technology and can uniformly compensate the slew rate of an output signal against fluctuations in power supply voltage, temperature, and manufacturing variations. is there.

  In order to achieve the above object, the present invention outputs a first detection signal by detecting that the voltage of the output signal has reached the first voltage during transition of the buffer and the output signal of the buffer. A first voltage detection circuit that detects that the voltage of the output signal has reached a second voltage, and outputs a second detection signal; and the first detection signal A delay circuit that outputs a delayed signal delayed by a predetermined time corresponding to an assumed value of the slew rate of the output signal; and a phase difference signal between the second detection signal and the delayed signal by detecting a phase difference signal An output buffer circuit comprising an output phase difference detector and a current source that adjusts a current driving force of the buffer according to the phase difference signal is provided.

  Here, as a first form, the output buffer circuit detects the first voltage and the second voltage higher than the first voltage during a rising period of the output signal, and the buffer It is preferable to control the current driving force on the power source side.

  Further, as a second form, the output buffer circuit detects the first voltage and the second voltage lower than the first voltage during a falling period of the output signal, and the buffer It is preferable to control the current driving force on the ground side.

  The output buffer circuit preferably includes the output buffer circuit of the first form and the output buffer circuit of the second form.

The present invention also provides a dummy buffer and a first detection signal that outputs a first detection signal by detecting that the voltage of the output signal has reached the first voltage during transition of the output signal of the dummy buffer. A voltage detection circuit; a second voltage detection circuit for detecting that the voltage of the output signal has reached a second voltage; and outputting a second detection signal; and the first detection signal as the output signal. A delay circuit that outputs a delayed signal delayed by a predetermined time corresponding to an assumed value of the slew rate, and a phase difference that detects a phase difference between the second detection signal and the delayed signal and outputs a phase difference signal A detector and a dummy current source for adjusting a current driving force of the dummy buffer according to the phase difference signal;
The output further comprising: a plurality of buffers; and a plurality of current sources provided in each of the plurality of buffers according to the phase difference signal and respectively adjusting a current driving force of the plurality of buffers. A buffer circuit is provided.

  According to the present invention, the slew rate of the output signal can be uniformly compensated for fluctuations in power supply voltage, temperature, and manufacturing variations, and a malfunction occurs in the circuit that receives the signal due to the timing deviation of the output signal. Can be prevented. In addition, by suppressing the steep rise or fall of the output signal, unnecessary fluctuation of the output voltage can be prevented, generation of electromagnetic noise can be suppressed, and EMI can be reduced.

  Hereinafter, an output buffer circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a schematic diagram of the first embodiment showing the configuration of the output buffer circuit of the present invention. The output buffer circuit 10 shown in the figure includes an IO (input / output) buffer 12, first and second voltage detection circuits 14a and 14b, a delay circuit 16, a phase difference detector 18, a low-pass filter 20, And a current source 22. The output buffer circuit 10 detects the rising slew rate of the output signal OUT of the buffer 12, and controls the current driving power on the power source side of the buffer 12 so that the slew rate becomes constant.

  Here, the signal IN is input to the buffer 12. The input signal IN is buffered by the buffer 12 and output as a signal OUT. The output signal OUT of the buffer 12 is input to the first and second voltage detection circuits 14a and 14b.

  The first voltage detection circuit 14a detects that the voltage has reached the first voltage (1) shown in the graph within the dotted line in FIG. A detection signal is output. When the first voltage detection circuit 14a detects that the voltage of the output signal OUT has reached the preset first voltage (1), the first detection signal becomes 'H (high level)'. . The first detection signal is input to the delay circuit 16.

  Further, the voltage detection circuit 14b detects that the voltage has reached the second voltage (2) higher than the first voltage (1) shown in the graph of FIG. 1 during the rising period of the output signal OUT. Then, the second detection signal is output. When the second voltage detection circuit 14b detects that the voltage of the output signal OUT has reached the preset second voltage (2), the second detection signal becomes 'H'. The second detection signal is input to the phase difference detector 18.

  The delay circuit 16 changes the first detection signal from the first voltage (1) to the second voltage (2) for a predetermined time corresponding to the assumed value (ideal value) + ΔT of the slew rate of the output signal OUT. Delayed by the time to reach + ΔT), and outputs a delayed signal. The delayed signal is input to the phase difference detector 18. ΔT is 0 to an arbitrary value, and the expected value of the slew rate of the output signal OUT can be appropriately adjusted by appropriately changing this value.

  Here, the slew rate of the output signal OUT is the time until the signal changes from “L (low level)” to “H” or from “H” to “L”. The delay time by the delay circuit 16 is set to the time + ΔT until the output signal OUT reaches the second voltage (2) from the first voltage (1), and the value is the first voltage ( It is calculated from the assumed value of the slew rate in consideration of 1) and the second voltage (2).

  Subsequently, the phase difference detector 18 detects a phase difference between the second detection signal and the delay signal and outputs a phase difference signal. The phase difference detected by the phase difference detector 18 is the time difference + ΔT between the assumed value of the slew rate and the current slew rate of the output signal OUT. The phase difference detection signal is an analog signal having a voltage value corresponding to the phase difference between the second detection signal and the delay signal, and is input to the low-pass filter 20.

  Here, when the phase of the second detection signal is delayed from the phase of the delayed signal, that is, when the current slew rate of the output signal OUT is larger than the assumed value, the voltage of the phase difference detection signal is It becomes low according to the phase difference between the two. On the other hand, when the phase of the second detection signal is ahead of the phase of the delay signal, that is, when the current slew rate of the output signal OUT is smaller than its assumed value, the voltage of the phase difference detection signal is It becomes higher according to the phase difference.

  The low pass filter 20 filters the phase difference detection signal to remove high frequency noise. The phase difference detection signal (DC voltage) filtered by the low-pass filter 20 is input to the current source 22.

  The current source 22 is configured by a P-type MOS transistor (PMOS) 24. The PMOS 24 is connected between the power supply and the buffer 12. The phase difference detection signal is input to the gate of the PMOS 24. When the voltage of the phase difference detection signal is increased, the on state of the PMOS 24 is weakened, and the current driving capability of the buffer 12 is also weakened. On the other hand, when the voltage of the phase difference detection signal is lowered, the PMOS 24 is turned on, and the current driving capability of the buffer 12 is also enhanced.

  Next, the voltage detection circuits 14a and 14b will be described with specific examples.

  FIG. 2 is a circuit diagram showing the configuration of the voltage detection circuit. The voltage detection circuit 14 ′ shown in FIG. 1 includes an N-type MOS transistor (NMOS) 30 and a resistance element 32. Both are connected in series between the power source and the ground. The gate of the NMOS 30 is an input terminal of the voltage detection circuit 14 ′, and the connection point A between the NMOS 30 and the resistance element 32 is an output terminal of the voltage detection circuit 14 ′.

  In the voltage detection circuit 14 ′, when the input signal reaches the gate threshold voltage of the NMOS 30, the NMOS 30 is turned on, and the output signal becomes ‘H’. The configuration of the first and second voltage detection circuits 14a and 14b is as shown in FIG. 2, but the gate threshold voltage of the NMOS 30 of the first voltage detection circuit 14a is the first voltage (1 in the graph shown in FIG. ) And the gate threshold voltage of the NMOS 30 of the second voltage detection circuit 14b is set to the second voltage (2).

  Therefore, when the first voltage detection circuit 14a detects that the output signal OUT has reached the first voltage (1) during the rising period of the output signal OUT, the NMOS 30 is turned on, and the first detection is performed. The signal becomes “H”. Subsequently, when the second voltage detection circuit 14b detects that the output signal OUT has reached the second voltage (2), the NMOS 30 is turned on, and the second detection signal becomes 'H'.

  FIG. 3 is a circuit diagram showing another configuration of the voltage detection circuit. The voltage detection circuit 14 ″ shown in the figure is configured by two inverters 34 and 36 connected in series. The configuration of the inverters 34 and 36 is known and is as shown in FIG.

  In the voltage detection circuit 14 ″, the input signal is inverted twice by the two inverters 34 and 36 and output. The configuration of the first and second voltage detection circuits 14a and 14b is as shown in FIG. 3, but the first voltage detection circuit 14a is configured so that the driving capability of the NMOS 40 is stronger than the PMOS 38, and is shown in FIG. The output is inverted at the first voltage (1) in the graph (the logic threshold is low). On the other hand, in the second voltage detection circuit 14b, the driving capability of the PMOS 38 is stronger than that of the NMOS 40, and the output is inverted at the second voltage (2) (logical threshold is high).

  Therefore, when the first voltage detection circuit 14a detects that the output signal OUT has reached the first voltage (1) during the rising period of the output signal OUT, the inverters 34 and 36 are inverted, and the first The detection signal becomes “H”. Subsequently, when the second voltage detection circuit 14b detects that the output signal OUT has reached the second voltage (2), the inverters 34 and 36 are inverted, and the second detection signal becomes “H”. .

  Hereinafter, the operation of the output buffer circuit 10 will be described.

  The input signal IN is buffered by the buffer 12 and output as a signal OUT.

  When the output signal OUT rises, the first voltage detection circuit 14a detects that the voltage has reached the first voltage (1) shown in the graph of FIG. H '. Subsequently, when the voltage of the output signal OUT further rises and the voltage detection circuit 14b detects that the voltage of the output signal OUT has reached the second voltage (2), the second detection signal also becomes' H '.

  The first detection signal is delayed by the delay circuit 16 by a predetermined time corresponding to the assumed value + ΔT of the slew rate of the output signal OUT. The phase difference between the delayed signal and the second detection signal is detected by the phase difference detector 18, and a voltage phase difference signal corresponding to the phase difference is output. The phase difference signal is filtered by the low pass filter 20 to remove high frequency noise.

  The current amount of the PMOS 24 of the current source 22 increases as the voltage of the phase difference detection signal decreases. Therefore, the current driving capability of the buffer 12 is increased, and the slew rate of the output signal OUT is decreased. On the other hand, when the voltage of the phase difference detection signal increases, the amount of current decreases. For this reason, the current driving capability of the buffer 12 is reduced, and the slew rate of the output signal OUT is increased.

  ΔT is added to the delay time by the delay circuit 16. Therefore, if the output buffer circuit 10 is made under ideal conditions, even if the phases of the second detection signal and the delay signal match, the phase difference between them is detected as ΔT. In actual use, the DC voltage output from the low-pass filter 20 transitions with a voltage V (ΔT) corresponding to the ΔT as a base point.

  As described above, the output buffer circuit 10 detects the current slew rate of the output signal of the buffer 12 and feeds back the current source 22 so that the slew rate of the buffer 12 becomes constant (assumed value). The current driving force on the power source side of the buffer 12 is controlled.

  As a result, the slew rate of the output signal OUT can be uniformly compensated for fluctuations in power supply voltage, temperature, and manufacturing variations, and a malfunction occurs in a circuit that receives the signal OUT due to a timing shift of the output signal OUT. Can be prevented. Further, by suppressing the steep rising or falling of the output signal OUT, unnecessary fluctuation of the output voltage can be prevented, generation of electromagnetic wave noise can be suppressed, and EMI can be reduced.

  Next, an output buffer circuit according to a second embodiment of the present invention will be described.

  FIG. 4 is a schematic diagram of the second embodiment showing the configuration of the output buffer circuit of the present invention. The output buffer circuit 50 shown in the figure includes an IO buffer 52, first and second voltage detection circuits 54a and 54b, a delay circuit 56, a phase difference detector 58, a low-pass filter 60, and a current source 62. It is constituted by. The output buffer circuit 50 detects the falling slew rate of the output signal OUT of the buffer 52, and controls the current driving force on the ground side of the buffer 52 so that the slew rate becomes constant.

  In the output buffer circuit 50, the buffer 52, the first and second voltage detection circuits 54a and 54b, the delay circuit 56, the phase difference detector 58, the low-pass filter 60, and the current source 62 are respectively output buffer circuits shown in FIG. 10 corresponds to the buffer 12, the first and second voltage detection circuits 14a and 14b, the delay circuit 16, the phase difference detector 18, the low-pass filter 20, and the current source 22.

  The difference between the two is the voltage detection circuits 54 a and 54 b and the current source 62. Hereinafter, the repeated description of the same components between them will be omitted, and only the voltage detection circuits 54a and 54b and the current source 62 will be described.

  The first voltage detection circuit 54a detects that the voltage has reached the first voltage (1) shown in the graph in the dotted line square of FIG. The detection signal is output. In the first voltage detection circuit 54a, when it is detected that the voltage of the output signal OUT has reached the preset first voltage (1), the first detection signal becomes “H (high level)”. .

  Further, the voltage detection circuit 54b indicates that the voltage has reached the second voltage (2) lower than the first voltage (1) shown in the graph of FIG. 4 during the falling period of the output signal OUT. It detects and outputs a 2nd detection signal. When the second voltage detection circuit 54b detects that the voltage of the output signal OUT has reached the preset second voltage (2), the second detection signal becomes ‘H’.

  The current source 62 is configured by an NMOS 64. The NMOS 64 is connected between the buffer 52 and the ground. The phase difference detection signal is input to the gate of the NMOS 64. When the voltage of the phase difference detection signal is lowered, the on state of the NMOS 24 is weakened, and the current driving capability of the buffer 52 is also weakened. On the other hand, when the voltage of the phase difference detection signal increases, the on state of the NMOS 64 increases and the current driving capability of the buffer 52 also increases.

  Next, the voltage detection circuits 54a and 54b will be described.

  FIG. 4 is a circuit diagram showing the configuration of the voltage detection circuit. The voltage detection circuit 54 ′ shown in the same figure is composed of a PMOS 70 and a resistance element 72. Both are connected in series between the power source and the ground. The gate of the PMOS 70 is an input terminal of the voltage detection circuit 54 ′, and the connection point B between the PMOS 70 and the resistance element 72 is an output terminal of the voltage detection circuit 54 ′.

  In the voltage detection circuit 54 ′, when the input signal reaches the gate threshold voltage of the PMOS 70, the PMOS 70 is turned on, and the output signal becomes ‘H’. The configuration of the first and second voltage detection circuits 54a and 54b is as shown in FIG. 5, but the gate threshold voltage of the PMOS 70 of the first voltage detection circuit 54a is the first voltage (1) in the graph shown in FIG. ), And the gate threshold voltage of the PMOS 70 of the second voltage detection circuit 54b is set to the second voltage (2).

  Therefore, when the first voltage detection circuit 54a detects that the output signal OUT has reached the first voltage (1) during the falling period of the output signal OUT, the PMOS 70 is turned on, and the first The detection signal becomes “H”. Subsequently, when the second voltage detection circuit 54b detects that the output signal OUT has reached the second voltage (2), the PMOS 70 is turned on, and the second detection signal becomes 'H'.

  FIG. 6 is a circuit diagram showing another configuration of the voltage detection circuit. The voltage detection circuit 54 ″ shown in FIG. The configuration of the inverter 74 is well known and is as shown in FIG.

  In the voltage detection circuit 54 ″, the input signal is inverted and output by the inverter 74. The configuration of the first and second voltage detection circuits 54a and 54b is as shown in FIG. 6, but the first voltage detection circuit 54a is configured so that the driving capability of the PMOS 78 is stronger than the NMOS 80, as shown in FIG. The output is inverted at the first voltage (1) in the graph. On the other hand, in the second voltage detection circuit 54b, the driving capability of the NMOS 80 is stronger than that of the PMOS 78, and the output is inverted at the second voltage (2).

  Therefore, when the first voltage detection circuit 54a detects that the output signal OUT has reached the first voltage (1) during the falling period of the output signal OUT, the inverter 74 is inverted and the first detection is performed. The signal becomes “H”. Subsequently, when the second voltage detection circuit 54b detects that the output signal OUT has reached the second voltage (2), the inverter 74 is inverted, and the second detection signal becomes 'H'.

  Hereinafter, the operation of the output buffer circuit 50 will be described.

  When the output signal OUT of the buffer 52 falls, the first voltage detection circuit 54a detects that the voltage has reached the first voltage (1) shown in the graph of FIG. The detection signal becomes “H”. Subsequently, when the voltage of the output signal OUT further decreases and the voltage detection circuit 54b detects that the voltage of the output signal OUT has reached the second voltage (2), the second detection signal is also ' H '.

  The first detection signal is delayed by the delay circuit 56 for a predetermined time corresponding to the assumed value + ΔT of the slew rate of the output signal OUT. The phase difference between the delayed signal and the second detection signal is detected by the phase difference detector 58, and a phase difference signal having a voltage corresponding to the phase difference is output. The phase difference signal is filtered by the low pass filter 60 to remove high frequency noise.

  The current amount of the NMOS 64 of the current source 62 increases as the voltage of the phase difference detection signal increases. As a result, the current driving capability of the buffer 52 increases and the slew rate of the output signal OUT decreases. On the other hand, when the voltage of the phase difference detection signal decreases, the amount of current decreases. For this reason, the current driving capability of the buffer 52 is reduced, and the slew rate of the output signal OUT is increased.

  The DC voltage output from the low-pass filter 60 is the same as that of the output buffer circuit 10 in that it transitions with the voltage V (ΔT) corresponding to ΔT as a base point. The operation and effect of the output buffer circuit 50 are the same as those of the output buffer circuit 10.

  Note that the output buffer circuit of the first embodiment and the output buffer circuit of the second embodiment can be used in combination. The specific configurations of the buffer, the voltage detection circuit, the delay circuit, the phase difference detector, the low-pass filter, and the current source are not limited at all, and various configurations of circuits that realize the same function can be employed. Further, the low-pass filter is not an essential component.

  Further, the present invention is applied to the dummy buffer, a current source is provided in each of the plurality of buffers, and phase difference signals output from the phase difference detector provided in the dummy buffer are provided in the plurality of output buffers. The current driving force of each of the plurality of buffers may be adjusted by supplying the supplied current source. In this case, one set of the first and second voltage detection circuits, the delay circuit, the phase difference detection circuit, and the low-pass filter is sufficient, and the circuit scale can be greatly reduced as compared with the case where the present invention is applied to each buffer.

The present invention is basically as described above.
The output buffer circuit of the present invention has been described in detail above. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the spirit of the present invention. is there.

1 is a schematic diagram of a first embodiment illustrating a configuration of an output buffer circuit of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of an output buffer circuit illustrated in FIG. 1. FIG. 4 is a circuit diagram illustrating another configuration of the output buffer circuit illustrated in FIG. 1. It is the schematic of 2nd Embodiment showing the structure of the output buffer circuit of this invention. FIG. 5 is a circuit diagram illustrating a configuration of an output buffer circuit illustrated in FIG. 4. FIG. 5 is a circuit diagram illustrating another configuration of the output buffer circuit illustrated in FIG. 4.

Explanation of symbols

10, 50 Output buffer circuit 12, 52 IO buffer 14a, 14b, 14 ', 14 ", 54a, 54b, 54', 54" Voltage detection circuit 16, 56 Delay circuit 18, 58 Phase difference detector 20, 60 Low-pass filter 22, 62 Current source 30, 40, 64, 80 N-type MOS transistor (NMOS)
32, 72 Resistive element 34, 36, 74 Inverter 38, 70, 78 P-type MOS transistor (PMOS)
IN input signal OUT output signal A, B Connection point

Claims (5)

  A buffer, a first voltage detection circuit for detecting that the voltage of the output signal has reached the first voltage during the transition of the output signal of the buffer, and outputting a first detection signal; and the output signal A second voltage detection circuit that detects that the first voltage has reached the second voltage and outputs a second detection signal, and the first detection signal corresponds to an assumed value of the slew rate of the output signal A delay circuit that outputs a delayed signal after being delayed by a predetermined time, a phase difference detector that detects a phase difference between the second detection signal and the delayed signal and outputs a phase difference signal, and the phase difference signal An output buffer circuit comprising: a current source for adjusting a current driving force of the buffer according to   The output buffer circuit detects the first voltage and the second voltage higher than the first voltage during a rising period of the output signal, and controls a current driving force on the power source side of the buffer The output buffer circuit according to claim 1, wherein:   The output buffer circuit detects the first voltage and the second voltage lower than the first voltage during a fall period of the output signal, and increases the current driving force on the ground side of the buffer. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is controlled.   An output buffer circuit comprising: the output buffer circuit according to claim 2; and the output buffer circuit according to claim 3. A dummy buffer, a first voltage detection circuit for detecting that the voltage of the output signal has reached the first voltage during the transition of the output signal of the dummy buffer, and outputting a first detection signal; A second voltage detection circuit that detects that the voltage of the output signal has reached the second voltage and outputs a second detection signal; and the first detection signal is assumed to be a slew rate of the output signal. A delay circuit that outputs a delayed signal after being delayed by a predetermined time, a phase difference detector that detects a phase difference between the second detection signal and the delayed signal, and outputs a phase difference signal; A dummy current source for adjusting a current driving force of the dummy buffer according to a phase difference signal;
The output further comprising: a plurality of buffers; and a plurality of current sources provided in each of the plurality of buffers according to the phase difference signal and respectively adjusting a current driving force of the plurality of buffers. Buffer circuit.

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