JP5689781B2 - Gated VCO circuit - Google Patents

Description

  The present invention relates to a data communication technique, and more particularly to a clock extraction technique that extracts and outputs a clock component from an input data signal.

  In general, when a clock component is extracted from an input data signal, a gated VCO circuit is used. For example, in a PON (Passive Optica 1 Network) system that realizes FTTH (Fiber To The Home), phase synchronization is instantaneously established for burst data received asynchronously, and a clock is extracted, and data is synchronized with this clock. A circuit configuration for retiming and sending out is essential.

A gated VCO circuit is a circuit that generates a clock signal having a frequency corresponding to the bit rate of an input data signal by free-running oscillation, adjusts the oscillation phase of the clock signal to the transition timing of the input data signal, and outputs it. .
FIG. 7 is a circuit diagram showing a configuration of a conventional gated VCO circuit. Conventionally, a configuration including a gating circuit 50 and a ring oscillator 60 has been proposed as the gated VCO circuit 200 (see, for example, Non-Patent Document 1: Figure 12).

  The gating circuit 50 includes a delay circuit 51 and a 2-input NAND circuit 52. An input data signal INPUTDATA is input to the NAND circuit 52 as a first input, and INPUTDATA is input as a second input via the delay circuit 51.

The delay circuit 51 is a delay circuit that outputs a positive phase delay signal DERAYP indicating the positive logic of INPUTDATA delayed by a delay time corresponding to ½ of the reference pulse period (minimum pulse time width) of INPUTDATA.
The NAND circuit 52 takes an inversion logic of the logical product of the inverse phase delayed signal DERAYN (internal signal) of INPUTDATA and DELETEP, and at every rising edge of INPUTDATA, 1 / of the reference pulse cycle of the input data signal. A pulse having a time length corresponding to 2 is output as a gating signal GOUT (differential signal).

The ring oscillator 60 is composed of a phase adjustment circuit 61 and a gate circuit group 62 connected in a ring shape, and the phase adjustment circuit 61 and the gate circuit group 62 generate free-running oscillations, so that a bit of INPUTDATA is obtained. A free-running clock signal CLKIN having a frequency corresponding to the rate is generated.
The gate circuit group 62 is a circuit in which a plurality of general gate circuits such as inverter circuits are connected in series. The number of connection stages between the gate circuit and the phase adjustment circuit 61 is determined in advance so that the free-running oscillation frequency matches the INPUTDATA bit rate with high accuracy.

  The phase adjustment circuit 61 uses the free-running clock signal CLKIN (differential signal) from the gate circuit group 22 as a first input, and GOUT (differential signal) from the gating circuit 10 as a second input. By controlling the oscillation phase of the free-running clock signal CLKIN according to GOUT, the clock output signal CLKOUT indicating the clock component of INPUTDATA is generated.

As shown in FIG. 7, the phase adjustment circuit 61 includes MOS transistors Q61 to Q65, resistance elements R61 and R62, and a current source IS.
In this phase adjustment circuit 61, the MOS transistors Q61 and Q62 constituting one differential pair and the MOS transistors Q63 and Q64 constituting another differential pair are placed between the power supply potential VDD and the ground potential VSS. Connected in a column column.

Among these MOS transistors, a negative phase free-running clock signal CLKINN of the free-running clock signal CLKIN from the gate circuit group 62 is input to the gate terminal of Q61, and the gate terminal of Q62 includes The positive-phase free-running clock signal CLKINP is input.
Further, the positive phase gating signal GOUTP of the gating signal GOUT of the gating circuit 50 is inputted to the gate terminal of Q63, and the negative phase gating signal GOUTN of GOUT is inputted to the gate terminal of Q64. Is entered.

  As a result, a signal indicating the inverted logic of the logical product of CLKINN and GOUTP is output as the positive-phase clock output signal CLKOUTP from the drain terminal of Q61 that is pulled up to VDD by the resistor element R61. Further, a signal indicating the inverted logic of the logical product of CLKINP and GOUTP, that is, a reverse phase clock output signal CLKOUTN indicating the inverted logic of CLKOUTP is output from the drain terminal of Q62 pulled up to VDD by the resistance element R62.

  Therefore, when there is no pulse in INPUTDATA and GOUTP, which is one of the second inputs, indicates a high level, Q63 is turned on and Q61 and Q62 can be operated. Therefore, the phase adjustment circuit 61 includes the ring oscillator 60. CLKIN which is the first input generated by self-running is output as CLKOUT.

  Further, when there is a pulse in INPUTDATA and GOUTP becomes low level in synchronization with the rising edge of INPUTDATA, Q63 is turned off and QOUT is turned on because GOUTN is at high level. For this reason, Q61 becomes inoperable, and CLKOUTN becomes high level for a length of ½ of the cycle of INPUTDATA regardless of the state of CLKIN which is the first input.

  Similarly to Q61, Q62 also becomes inoperable, but since Q64 is on, CLKOUTP goes low via Q65. As a result, the ring oscillator 60 starts ring oscillation starting from the low level pulse of CLKOUTP. By this operation, the ring oscillator 60 provides a function of instantaneously synchronizing the phase of CLKIN with the rising edge of INPUTDATA.

  FIG. 8 is a signal waveform diagram showing the operation of the conventional gated VCO circuit. When INPUTDATA is input to the gating circuit 50, for each rising edge of the INPUTDATA, a pulse having a half of the signal period is output from the gating circuit 50 as GOUT (GOUTP, GOUTN). In the ring oscillator 60, CLKIN (CLKINP, CLKINN) from the gate circuit group 62 is input to the phase adjustment circuit 61. As a result, a signal indicating the inverted logic of the logical product of GOUTP and CLKINN is output from the phase adjustment circuit 61 as CLKOUTP. In addition, a signal indicating the inverted logic of the logical product of GOUTP and CLKINP is output from the phase adjustment circuit 61 as CLKOUTP.

  With this configuration, when the input data signal INPUTDATA has a rising edge, a half pulse of the signal cycle, which is phase-synchronized with the edge of INPUTDATA, is output from the phase adjustment circuit 61 as the clock output signal CLKOUT. . If INPUTDATA has no rising edge, the free-running clock signal CLKIN generated by the ring oscillator 60 is output from the phase adjustment circuit 61 as CLKOUT. As a result, the clock component of INPUTDATA can be output as the clock output signal CLKOUT.

M. Nogawa, et al. “A 10Gb / s Burst-Mode CDR IC in 0.13um CMOS” ISSCC Dig. Tech. Papers, pp. 228-229, Feb., 2005.

  However, such a conventional technique has a problem that the clock output signal CLKOUT output from the phase adjustment circuit 61 includes jitter and a shift in the clock duty ratio, so that a good clock component cannot be extracted.

  That is, according to the conventional gated VCO circuit 200 shown in FIG. 7 described above, the propagation delay time until the clock output signal CLKOUT changes according to the change of the free-running clock signal CLKIN that is the first input is The propagation delay time until CLKOUT changes according to the change of the gating signal GOUT as the second input is greatly different.

  Specifically, as shown in FIG. 8, when GOUTP transitions to a low level, the delay time, that is, the rise time when CLKOUTN transitions from a low level to a high level is short. However, when CLKINP transitions to a low level, the delay time when CLKOUTN transitions from a low level to a high level, that is, the rise time is long. Similarly, when CLKINP transitions to a high level, the delay time, that is, the fall time, when CLKOUTN transitions from a high level to a low level is long.

  In general, circuits using MOS transistors tend to operate with low operating power for the purpose of reducing power consumption. When MOS transistors are connected in series to the operating power supply under such severe conditions, the operating voltage that can be used in each MOS transistor is greatly reduced. In particular, in the circuit configuration shown in FIG. 7, since there is a voltage drop even in the drain resistors R61 and R62 and the current source IS, the operating voltage (drain-source voltage) that can be used in the MOS transistors Q61 and Q62 and the MOS transistor Q63 is further increased. descend. For example, when an operating voltage of 1.2 V is supplied between VDD and VSS, operating voltages that can be used in Q61, Q62, and Q63 are about 0.2 to 0.3 V, respectively.

Further, when signals having the same potential are used as CLKIN and GOUT that control these Q61, Q62, and Q63, the drain potential of Q63 tends to increase, and the operating voltage that can be used in Q61 and Q62 tends to further decrease. On the other hand, the response of MOS transistors tends to decrease as the operating voltage decreases.
For this reason, the operating voltage of Q61 and Q62 is further lowered under the severe condition that originally a sufficient operating voltage cannot be obtained. As a result, Q61 and Q62 responsiveness is deteriorated as compared with Q63.

  Therefore, the rise / fall time of the clock output signal CLKOUT depends on whether the gating signal GOUT or the free-running clock signal CLKIN is used as the clock output signal CLKOUT output from the conventional gated VCO circuit 200. Will change. For this reason, jitter corresponding to fluctuations in the rising / falling time of CLKOUT and a deviation from 50% of the clock duty ratio (the ratio of the high level time to one period) occur.

  An object of the present invention is to solve such a problem, and an object of the present invention is to provide a clock extraction technique capable of extracting a good clock component with suppressed jitter and clock duty ratio shift.

  In order to achieve such an object, a gated VCO circuit according to the present invention detects a rising or falling edge of each pulse included in an input data signal and generates a gating signal composed of a pulse signal having a certain time width. A gating circuit that outputs in phase with the edge, a gate circuit group composed of a plurality of gate circuits connected in series, and a phase adjustment circuit are connected in a ring shape, and the gate circuit group and the phase adjustment circuit To generate a free-running clock signal having a frequency corresponding to the bit rate of the input data signal, and the phase adjustment circuit changes the oscillation phase of the free-running clock signal according to the gating signal. A ring oscillator that generates a clock output signal indicating a clock component of the input data signal by controlling, In the phase adjustment circuit, a parallel connection circuit of a first MOS transistor that receives a free-running clock signal output from the gate circuit group and a second MOS transistor that receives a gating signal, and a reference voltage as a reference A CML circuit that forms a differential pair with a third MOS transistor as an input, and outputs a logical sum of the free-running clock signal obtained by the CML circuit and a gating signal or its inverted logic as a clock output signal. It is what I did.

  At this time, the phase adjustment circuit has a gate terminal connected to the free-running clock signal, a drain terminal connected to the first power supply potential via the first resistance element, and a source terminal connected to the second current via the constant current source. A first MOS transistor connected to the power supply potential, a gate terminal connected to the gating signal, a drain terminal connected to the drain terminal of the first MOS transistor, and a source terminal connected to the source terminal of the first MOS transistor A second MOS transistor connected to the first MOS transistor, a gate terminal connected to the reference voltage, a drain terminal connected to the first power supply potential via the second resistance element, and a source terminal connected to the source of the first MOS transistor You may comprise from the terminal and the 3rd MOS transistor connected in common with the source terminal of the 2nd transistor.

  Also, a DC level that detects and outputs a differential voltage between the DC level of the positive phase signal of the clock output signal output from the phase adjustment circuit and the DC level of the negative phase signal of the clock output signal output from the phase adjustment circuit. A difference detection circuit and a reference voltage generation circuit that generates a reference voltage by comparing the difference voltage with an offset voltage having a constant potential may be further provided.

  According to the present invention, in the phase adjustment circuit of the ring oscillator, the rising / falling time of the clock output signal does not change when either the gating signal or the free-running clock signal is selected as the clock output signal. Therefore, it is possible to extract a good clock component with very little jitter and a clock duty ratio of about 50%.

1 is a circuit diagram showing a configuration of a gated VCO circuit according to a first embodiment. FIG. FIG. 6 is a signal waveform diagram showing an operation of the gated VCO circuit according to the first embodiment. It is a circuit diagram which shows the structure of the gated VCO circuit concerning 2nd Embodiment. FIG. 6 is a signal waveform diagram showing an operation of a gated VCO circuit according to a second embodiment. It is a circuit diagram which shows the structure of a direct current | flow level difference detection circuit. It is a circuit diagram which shows the structure of a reference voltage generation circuit. It is a circuit diagram which shows the structure of the conventional gated VCO circuit. It is a signal waveform diagram which shows the operation | movement of the conventional gated VCO circuit.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a gated VCO circuit 100 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of a gated VCO circuit according to the first embodiment.

  The gated VCO circuit 100 shown in FIG. 1 generates a clock signal having a frequency corresponding to the bit rate of the input data signal by free-running oscillation, and outputs the clock signal with its oscillation phase synchronized with the transition timing of the input data signal. It has a function to do. This gated VCO circuit 100, for example, in a PON (Passive Optica1 Network) system that realizes FTTH (Fiber To The Home), when establishing a phase synchronization instantaneously and extracting a clock for burst data received asynchronously. Used.

[Configuration of First Embodiment]
The configuration of the gated VCO circuit 100 will be described in detail with reference to FIG.
The gated VCO circuit 100 includes a gating circuit 10 and a ring oscillator 20.
The gating circuit 10 detects a rising edge of each pulse included in the input data signal, and phase-synchronizes the gating signal including a pulse signal having a time width corresponding to 1/2 of the reference pulse period of INPUTDATA to the edge. Output function.

The gating circuit 10 includes a delay circuit 11 and a NAND circuit 12.
The delay circuit 11 is a delay circuit that outputs a positive-phase delay signal DERAYP indicating the positive logic of INPUTDATA delayed by a delay time corresponding to ½ of the reference pulse period (minimum pulse time width) of the input data signal INPUTDATA. .
The NAND circuit 12 takes an inversion logic of the logical product of the inverse phase delayed signal DERAYN (internal signal) of INPUTDATA and DELETEP, and at every rising edge of INPUTDATA, 1 / of the reference pulse cycle of the input data signal. A pulse having a time length corresponding to 2 is output as a gating signal GOUT (differential signal). In the example of FIG. 1, only the anti-phase gating signal GOUTN in which GOUT is represented by inverted logic is output from the NAND circuit 12 to the phase adjustment circuit 21.

The ring oscillator 20 includes a phase adjustment circuit 21 and a gate circuit group 22 connected in a ring shape, and the phase adjustment circuit 21 and the gate circuit group 22 generate free-running oscillations, so that a bit of INPUTDATA is obtained. A free-running clock signal CLKIN having a frequency corresponding to the rate is generated.
The gate circuit group 22 is a circuit in which a plurality of general gate circuits such as inverter circuits are connected in series. The number of connection stages between the gate circuit and the phase adjustment circuit 21 is determined in advance so that the free-running oscillation frequency coincides with the INPUTDATA bit rate with high accuracy.

  The phase adjustment circuit 21 uses a negative-phase free-running clock signal CLKINN obtained by inverting logic of CLKIN from the gate circuit group 22 as a first input, and uses GOUTN from the gating circuit 10 as a second input. In response to this, by controlling the oscillation phase of the free-running clock signal CLKINN, a clock output signal CLKOUT (differential signal) indicating the clock component of INPUTDATA is generated.

As shown in FIG. 1, the phase adjustment circuit 21 is provided with MOS transistors Q1 to Q3, resistance elements R1 and R2, and a current source IS1.
Q1 (first MOS transistor) is an N-type MOS transistor, and has a gate terminal connected to the anti-phase free-running clock signal CLKINN and a drain terminal connected to the power supply potential VDD (first resistor) via R1 (first resistance element). 1 is connected to the ground potential VSS (second power supply potential) via IS1.

Q2 (second MOS transistor) is an N-type MOS transistor, and has a gate terminal connected to GOUTN, a drain terminal connected to the drain terminal of Q1, and a source terminal connected to the source terminal of Q1.
Q3 (third MOS transistor) is composed of an N-type MOS transistor, the gate terminal is connected to the reference voltage VREF, the drain terminal is connected to VDD via R2 (second resistance element), and the source terminal is Q1. And the source terminal of Q2 are commonly connected. The potential of VREF is set to a constant potential located between VDD and VSS.

  Therefore, the phase adjustment circuit 21 as a whole is composed of a CML (Current Mode Logic) circuit in which a parallel connection circuit of Q1 and Q2 and Q3 form a differential pair. As a result, the potentials of the drain terminals of Q1 and Q2 are output as the positive phase clock output signal CLKOUTP of the clock output signal CLKOUT, and the potential of the drain terminal of Q3 is output as the negative phase clock output signal CLKOUTN of the clock output signal CLKOUT. The That is, the phase adjustment circuit 21 operates as a gate circuit that outputs the NOR logic of GOUTN and CLKINN as CLKOUTP.

[Operation of First Embodiment]
Next, the operation of the gated VCO circuit 100 according to the present embodiment will be described with reference to FIG. FIG. 2 is a signal waveform diagram showing an operation of the gated VCO circuit according to the first embodiment.

  When the input data signal INPUTDATA is input to the gating circuit 10, the NAND circuit 12 takes the inverted logic of the logical product of the INPUTDATA and the reverse logic DERAYN of the normal phase delay signal DERAYP from the delay circuit 11. As a result, the anti-phase gating signal GOUTN including a pulse signal having a time width corresponding to ½ of the reference pulse period of INPUTDATA is output from the NAND circuit 12 in phase synchronization with the rising edge of INPUTDATA.

  In the phase adjustment circuit 21 of the ring oscillator 20, when one or both of GOUTN and CLKINN are at a high level, either one or both of Q1 and Q2 are turned on and the current defined by the constant current source IS1 Flows, so that no current flows through Q3 and the switch is turned off. Therefore, CLKOUTN indicates a high level and CLKOUTP indicates a low level.

On the other hand, when both GOUTN and CLKINN are at the low level, both Q1 and Q2 are turned off and the current defined by the constant current source IS1 does not flow, so that the current flows only to Q3 and is turned on. Therefore, CLKOUTN indicates a low level and CLKOUTP indicates a high level.
Therefore, the phase adjustment circuit 21 outputs the logical sum of GOUTN and CLKINN as CLKOUTP. This is because the inversion logic of the logical product of CLKINP and GOUTP in the phase adjustment circuit 61 of FIG. The output is the same as the logic circuit.

  Therefore, when the input data signal INPUTDATA has a rising edge, that is, when GOUTP is at a high level, a pulse having a half of the signal cycle phase-synchronized with the edge of INPUTDATA is phase-shifted as the clock output signal CLKOUT. Output from the adjustment circuit 21. When INPUTDATA has no rising edge, that is, when GPUP is at a low level, the free-running clock signal CLKIN generated by the ring oscillator 20 and having a bit rate corresponding to INPUTDATA is output from the phase adjustment circuit 21 as CLKOUT. Is done.

At this time, the phase adjustment circuit 21 takes the form of OR logic in which Q1 and Q2 are connected in parallel in the CML circuit. For this reason, the propagation delay time until CLKOUTN changes due to a change in CLKINN substantially matches the propagation delay time until CLKOUTN changes due to a change in GOUTN.
In addition, since Q1 and Q2 are not connected in series with other MOS transistors in the CML circuit, the operating voltage that can be used for Q1 and Q2 at the time of CLKOUT output is sufficiently secured within the operating voltage between VDD and VSS. And good responsiveness can be obtained.

  Therefore, regardless of whether the gating signal GOUT or the free-running clock signal CLKIN is used as the clock output signal CLKOUT, the rise / fall time of the clock output signal CLKOUT does not change, the jitter is extremely small, and the clock duty ratio is A good clock component, approximately 50%, is extracted.

[Effect of the first embodiment]
As described above, according to the present embodiment, the phase adjustment circuit 21 of the ring oscillator 20 includes the MOS transistor Q1 that receives the free-running clock signal CLKIN (CLKINN) output from the gate circuit group 22 and the gating circuit 10. The CML circuit in which the parallel connection circuit of the MOS transistor Q2 that receives the gating signal GOUT (GOUTN) and the MOS transistor Q3 that receives the reference voltage VREF as a reference forms a differential pair. The logical sum of the free-running clock signal CLKINN and the gating signal GOUTN obtained in the above or the inverted logic thereof is output as the clock output signal CLKOUT (CLKPUTP, CLKOUTN).

  More specifically, the gate terminal is connected to the free-running clock signal CLKINN, the drain terminal is connected to the power supply potential VDD via the resistance element R1, and the source terminal is connected to the ground potential VSS via the constant current source IS1. The MOS transistor Q1, the gate terminal is connected to the gating signal GOUTN, the drain terminal is connected to the drain terminal of Q1, the source terminal is connected to the source terminal of Q1, and the gate terminal is the reference voltage VREF. , A drain terminal is connected to VDD via a resistance element R2, and a source terminal is composed of a source terminal of Q1 and a MOS transistor Q3 commonly connected to the source terminal of Q2 to constitute a phase adjustment circuit 21. .

Therefore, in the CML circuit of the phase adjustment circuit 21, since Q1 and Q2 are connected in parallel, the propagation delay time until CLKOUTN changes due to the change of CLKINN is the propagation delay time until CLKOUTN changes due to the change of GOUTN. And almost match. In addition, since Q1 and Q2 are not connected in series with other MOS transistors in the CML circuit, the operating voltage that can be used for Q1 and Q2 at the time of CLKOUT output is sufficiently secured within the operating voltage between VDD and VSS. And good responsiveness can be obtained.
Therefore, the rising / falling time of the clock output signal CLKOUT does not change regardless of which of the gating signal GOUT and the free-running clock signal CLKIN is selected as the clock output signal CLKOUT. Therefore, it is possible to extract a good clock component with very little jitter and a clock duty ratio of about 50%.

[Second Embodiment]
Next, a gated VCO circuit 100 according to a second embodiment of the present invention will be described with reference to FIG. 3 and FIG. FIG. 3 is a circuit diagram showing a configuration of a gated VCO circuit according to the second embodiment. FIG. 4 is a signal waveform diagram showing an operation of the gated VCO circuit according to the second embodiment.

  In the first embodiment, the case where the reference voltage VREF is preset in the phase adjustment circuit 21 of the ring oscillator 20 has been described as an example. Here, when VREF deviates from an appropriate value, as shown in FIG. 4, in the clock output signal CLKOUT, between the DC level of the positive phase clock output signal CLKOUTP and the DC level of the negative phase clock output signal CLKOUTN, A differential voltage VDIFF is generated.

  For example, in the phase adjustment circuit 21 of FIG. 3, when a potential higher than an appropriate value is applied as VREF, the on-resistance of the MOS transistor Q3 decreases. As a result, even when the MOS transistors Q1 and Q2 are in the on state and Q3 is originally in the off state, a current easily flows through Q3, and the high level potential of CLKOUTN decreases. For this reason, the waveform of CLKOUTN decreases as a whole, and its DC level decreases.

  Further, when a potential lower than an appropriate value is applied as VREF, the MOS transistor Q3 is less likely to transition to the on state, the MOS transistors Q1 and Q2 are in the off state, and even when the Q3 is originally in the on state, It becomes difficult for current to flow, and the low level potential of CLKOUTN rises. For this reason, the waveform of CLKOUTN rises as a whole, and its DC level rises.

  On the other hand, Q1 and Q2 perform an on / off operation according to the potential of GOUTN or CLKINN regardless of VREF. Normally, since GOUTN and CLKINN change between the output levels of the gate circuit, that is, between VDD and VSS, Q1 and Q2 reach the saturation region in the ON state. For this reason, the DC level of CLKOUTP output from Q1 and Q2 shows a constant value regardless of VREF.

Therefore, when the CLKOUTP and CLKOUTN are received by the differential circuit by the post-stage circuit that receives CLKOUT, the differential circuit does not operate normally due to the VDIFF between the DC levels of the CLKOUTP and CLKOUTN. You will not be able to receive it correctly.
In addition, since the potential of VREF depends on the power supply voltage to be used, that is, VDD and VSS, the potential of VREF is adjusted from the outside of the gated VCO circuit 100 when it can be used with different power supply voltages. There is a need to.

  In the present embodiment, as a configuration for automatically adjusting such VREF, as shown in FIG. 3, a DC level difference detection circuit 31 and a reference voltage generation circuit 32 are provided in a gated VCO circuit 100. is there.

First, the DC level difference detection circuit 31 will be described in detail with reference to FIG. FIG. 5 is a circuit diagram showing the configuration of the DC level difference detection circuit.
The DC level difference detection circuit 31 has a function of detecting and outputting a differential voltage VDIFF indicating a DC level difference between the average DC level of CLKOUTP and the average DC level of CLKOUTN. As a result, whether or not VREF of the phase adjustment circuit 21 exceeds or does not exceed an appropriate value (a value at which the DC level matches) is detected.

As shown in FIG. 5, the direct current level difference detection circuit 31 is provided with low-pass filters 31A and 31B and a differential amplifier circuit 31C.
The low-pass filter 31A includes an amplifier A11 having a series circuit of a resistive element R11 and a capacitive element C11 as a feedback loop, smoothes CLKOUTN, and outputs a voltage whose high level integration and low level integration match. As a result, an average DC level V_CLKOUTN of CLKOUTN is obtained.

  The low-pass filter 31B is composed of an amplifier A12 having a series circuit of a resistor element R12 and a capacitor element C12 as a feedback loop, smoothes CLKOUTP, and outputs a voltage whose high level integration and low level integration match. Thus, an average DC level V_CLKOUTP of CLKOUTP is obtained.

The differential amplifier circuit 31C amplifies the voltage difference between the two DC levels with an amplification factor K, and outputs the result obtained by adding the offset voltage VOFFSET1 as VDIFF. Therefore, VDIFF is expressed by the following equation (1).
VDIFF = K × (V_CLKOUTP−V_CLKOUTN) + VOFFSET1 (1)

Next, the reference voltage generation circuit 32 will be described in detail with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of the reference voltage generation circuit.
The reference voltage generation circuit 32 has a function of generating VREF by comparing VDIFF detected by the DC level difference detection circuit 31 with an offset voltage VOFFSET having a constant potential. That is, when VDIFF is larger than the appropriate value, VREF is adjusted so as to decrease it. When VDIFF is smaller than the appropriate value, VREF is adjusted so as to increase it. Therefore, the DC level difference detection circuit 31 and the reference voltage generation circuit 32 apply feedback to VREF so that their DC levels coincide while monitoring the outputs CLKOUT and CLKOUTN.

As shown in FIG. 6, the reference voltage generation circuit 32 is provided with MOS transistors Q21 and Q22, resistance elements R21 and R22, and a constant current source IS2.
Q21 is formed of an N-type MOS transistor, and has a gate terminal connected to VDIFF, a drain terminal connected to VDD via R21, and a source terminal connected to VSS via IS2.
Q22 is composed of an N-type MOS transistor, the gate terminal is connected to VOFFSET, the drain terminal is connected to VDD via R22, and the source terminal is connected to the source terminal of Q21.

The reference voltage generation circuit 32 has the form of a differential amplifier as a whole, compares the potential of VDIFF input to the gate terminal of Q21 with VOFFSET input to the gate of Q22, and outputs the difference to VREF. At this time, the difference between VDIFF and VOFFSET can be output by outputting VREF from the drain terminal of Q22. When the amplification factor of the differential amplifier is K ′ and the offset voltage is VOFFSET2, VREF is expressed by the following equation (2).
VREF = K '× (VDIFF−VOFFSET1) + VOFFSET2
= K '× K × (V_CLKOUTP−V_CLKOUTN)
+ K '× (VOFFSET1-VOFFSET) + VOFFSET2 (2)

If V_CLKOUTN of CLKOUTN is lower than V_CLKOUTP of CLKOUTP as in the above equation (2), VREF increases by K ′ × K times the difference between these DC levels (V_CLKOUTP−V_CLKOUTN).
Therefore, in the phase adjustment circuit 21, when VREF increases, the gate potential of Q3 increases, and the current flowing through the resistor R2 increases. Thereby, V_CLKOUTP becomes low and coincides with V_CLKOUTN of CLKOUTN.

Conversely, when V_CLKOUTN is higher than V_CLKOUTP, VREF decreases by K ′ × K times the difference in DC level (V_CLKOUTP−V_CLKOUTN).
Therefore, in the phase adjustment circuit 21, when VREF decreases, the gate potential of Q3 decreases, and the current flowing through the resistor R2 decreases. As a result, V_CLKOUTP becomes high and coincides with V_CLKOUTN of CLKOUTN.

[Effect of the second embodiment]
Thus, in the present embodiment, the DC level difference detection circuit 31 detects and outputs the differential voltage VDIFF between the DC level V_CLKOUTP of the normal phase clock output signal CLKOUT and the DC level V_CLKOUTN of the negative phase clock output signal CLKOUTN. The reference voltage generation circuit 32 generates the reference voltage VREF by comparing the differential voltage VDIFF with the offset voltage VOFFSET having a constant potential.

  As a result, the reference voltage VREF that matches the DC levels of CLKOUT and CLKOUTN can be automatically generated in the gated VCO circuit 100 by feedback control. Therefore, the work for adjusting VREF to an appropriate voltage can be automated, and the work load at the time of manufacture or use can be greatly reduced. Further, it is possible to extract a good clock component having very little jitter and a clock duty ratio of about 50% without requiring external adjustment.

  In this embodiment, VOFFSET used in the reference voltage generation circuit 32 may be supplied from outside the gated VCO circuit 100, but may be generated by an internal circuit. For example, in the reference voltage generation circuit 32, resistance division is performed so that VREF = K ′ × (VOFFSET1−VOFFSET) + VOFFSET2 shown in the equation (2) matches the voltage VREF that matches the DC level of CLKOUTP and CLKOUTN. The power supply voltage VDD-VSS may be fixedly generated by a circuit.

  In this embodiment, VOFFSET, VOFFSET1, and VOFFSET2 are required. VOFFSET1 and VOFFSET2 are voltages that are set when the DC level difference detection circuit 31 and the reference voltage generation circuit 32 operate, and VOFFSET is This is a potential that can be set during circuit design. Therefore, it is not necessary to adjust at the time of manufacture or use.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

  In the above embodiment, the case where the phase adjustment circuit 21 adjusts the phase of the clock output signal CLKOUT based on the antiphase gating GOUTN and the antiphase free-running clock signal CLKINN has been described as an example. The combination of signals is not limited to these. When logically coincident with the circuit example described in each embodiment, other signals may be used in combination, or a circuit such as a MOS transistor or an inverter may be added to match the signal logic. .

  DESCRIPTION OF SYMBOLS 100 ... Gated VCO circuit, 10 gating circuit, 11 ... Delay circuit, 12 ... NAND circuit, 20 ... Ring oscillator, 21 ... Phase adjustment circuit, 22 ... Gate circuit group, 31 ... DC level difference detection circuit, 31A, 31B ... Low-pass filter, 31C ... differential amplifier circuit, 32 ... reference voltage generation circuit, Q1 ... MOS transistor (first MOS transistor), Q2 ... MOS transistor (second MOS transistor), Q3 ... MOS transistor (third MOS) Transistor), R1... Resistive element (first resistive element), R2... Resistive element (second resistive element), IS1... Constant current source, VDD... Power supply potential (first power supply potential), VSS. Second power supply potential), VREF ... reference voltage, INPUTDATA ... input data signal, DELAYN ... reverse Delay signal, GOUT ... Gating signal, GOUTN ... Reverse phase gating signal, CLKINN ... Reverse phase free running clock signal, CLKOUTP ... Normal phase clock output signal, CLKOUTN ... Reverse phase clock output signal, V_CLKOUTP, V_CLKOUTN ... DC level, VDIFF ... differential voltage, VOFFSET ... offset voltage.

Claims (3)

A gating circuit that detects a rising edge or a falling edge of each pulse included in the input data signal, and outputs a gating signal including a pulse signal having a predetermined time width in phase synchronization with the edge;
A gate circuit group composed of a plurality of gate circuits connected in series and a phase adjustment circuit are connected in a ring shape, and the gate circuit group and the phase adjustment circuit perform free-running oscillation, whereby the input data signal A free-running clock signal having a frequency corresponding to a bit rate is generated, and the phase adjustment circuit controls the oscillation phase of the free-running clock signal in accordance with the gating signal, whereby the clock component of the input data signal And a ring oscillator that generates a clock output signal indicating
The phase adjustment circuit serves as a reference with a parallel connection circuit of a first MOS transistor that receives the free-running clock signal output from the gate circuit group and a second MOS transistor that receives the gating signal. A third MOS transistor having a reference voltage as an input is a CML circuit that forms a differential pair, and a logical sum of the free-running clock signal obtained by the CML circuit and the gating signal or an inverted logic thereof is obtained. A gated VCO circuit characterized in that it is output as a clock output signal. The gated VCO circuit of claim 1,
The phase adjustment circuit includes:
The gate terminal is connected to the free-running clock signal, the drain terminal is connected to the first power supply potential via the first resistance element, and the source terminal is connected to the second power supply potential via the constant current source. The first MOS transistor;
The second MOS having a gate terminal connected to the gating signal, a drain terminal connected to the drain terminal of the first MOS transistor, and a source terminal connected to the source terminal of the first MOS transistor A transistor,
A gate terminal is connected to the reference voltage, a drain terminal is connected to the first power supply potential via a second resistance element, and a source terminal is connected to the source terminal and the second transistor of the first MOS transistor. A gated VCO circuit comprising: the third MOS transistor commonly connected to the source terminal of the third MOS transistor. The gated VCO circuit according to claim 1 or 2,
A differential voltage between the DC level of the positive phase signal of the clock output signal output from the phase adjustment circuit and the DC level of the negative phase signal of the clock output signal output from the phase adjustment circuit is detected and output. A DC level difference detection circuit;
A gated VCO circuit, further comprising: a reference voltage generation circuit that generates the reference voltage by comparing the differential voltage with an offset voltage having a constant potential.

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