JPH06349949A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance a circuit in matching properties to a preceding and a following circuit by a method wherein a pair of the same logical function gate circuits are arranged close to each other in a scrambling state, one of them is kept in operation, and the other is kept out of operation. CONSTITUTION:Signals taken in through a circuit function A as an input stage are processed through a circuit function B and outputted through a circuit function C as an output stage. The circuit function B is composed of two circuit functions B1 and B2 which comprise small function blocks b1n to b21 to b2n respectively. Furthermore, the circuit functions B1 and B2 are put in a scrambling state corresponding to processed signals, arranged as close to each other as possible, and so laid out as to be nearly equal in processing time. Therefore, it is not required that the circuit functions B1 and B2 are put in operation at the same time, and when one of them is kept in operation, the other is kept out of operation, whereby a semiconductor integrated circuit can be lessened in current consumption and enhanced in function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective for use in a semiconductor integrated circuit device such as a gate array composed of an ECL (emitter coupled logic) circuit. is there.

[0002]

2. Description of the Related Art A defect relief technique in which two circuits having the same function are formed in a semiconductor integrated circuit device for defect relief and the other circuit is used when a defect defect occurs in one of them. There is. Regarding such defect relief, for example, there is JP-A-55-156354.

[0003]

As described above, in the conventional semiconductor integrated circuit device, a circuit whose operating speed is not so fast is not a serious problem, but in a circuit such as an ECL circuit which operates at high speed, there are two problems. The signal path will differ between circuits. As a result, there is a problem in that a difference in signal transmission speed occurs, and a margin at the time of exchanging a signal with the input stage circuit or the next stage circuit deteriorates.

In a circuit such as an ECL circuit in which a current constantly flows, the circuit function that can be mounted in one semiconductor integrated circuit device is equivalently halved due to the heat generated by the consumed current. As a result, the cost per function of the semiconductor integrated circuit device is increased, so that there is a contradiction that the significance of providing the redundant circuit is lost.

An object of the present invention is to provide a semiconductor integrated circuit device which realizes a redundant function or high reliability without sacrificing an operating margin. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the same input signal is input from the adjacent input circuits, the gate circuits having the same logic function are arranged close to each other in the scrambled state, and the corresponding output signal is output from the adjacent output circuit. A pair of signal processing circuits is provided, and one circuit of the pair of signal processing systems is set in an operating state and the other circuit is set in a non-operating state.

[0007]

According to the above-mentioned means, the signal transmission paths of the normal circuit and the standby circuit can be made substantially the same, so that the matching between the pre-stage circuit which forms the input signal and the next-stage circuit which receives the output signal can be ensured. In addition to improving the current consumption, only one circuit can be operated at any one time, so that the total current consumption is small, and since the entire circuit is distributed, the circuit function that can be formed in one semiconductor integrated circuit can be increased.

[0008]

1 is a schematic block diagram of an embodiment of a semiconductor integrated circuit device (logic LSI) according to the present invention. It should be noted that the drawing is drawn differently from the layout and functional blocks in an actual semiconductor integrated circuit in order to facilitate understanding of the invention.

Although not particularly limited, the circuit function originally possessed by the semiconductor integrated circuit device is roughly divided into a circuit function A as an input stage such as an input interface. The signal taken in through the circuit function A is processed by the circuit function B. A circuit function C is provided as an output stage such as an output interface. The above-mentioned circuit functions A and C are set to be in a constantly operating state as a common part.

The circuit function B, which is the center of the signal processing, is provided with two circuit functions B1 and B2 having the same function for the purpose of relief of defect defects and backup for high reliability. The circuit functions B1 and B2 are arranged such that gates having the same function are adjacent to each other, instead of separately arranging each circuit as one unit as in the conventional case. To conceptually show such a configuration, the circuit function B1 is composed of small function blocks b11 to b1n, and the circuit function B2 is composed of the same small function blocks b21 to b2n.

Small functional blocks that perform the same logical processing such as signal processing are arranged adjacent to each other as indicated by b11 and b21. Hereinafter, similarly, b12 and b22 to b1n and b2n
Are arranged adjacent to each other. The small function block b1
The same input signal is supplied to 1 and b21 from the circuit function A as an input stage. Other small function blocks b12 and b2
The same applies to 2 to b1n and b2n.

As mentioned above, in order to facilitate understanding of the invention, one small functional block is drawn to form one output signal for one signal. In view of the circuit form, this configuration is merely a signal transmission path that does not actually perform any signal processing. In actual signal processing, a plurality of input signals and stored signals are logically processed with each other. Therefore, it is not appropriate to represent an actual circuit as a small functional block as described above, but it should be understood that it is expressed as above for conceptually explaining the present invention.

The circuits forming the two output signals obtained as a result of the same logical processing are arranged adjacent to each other and are transmitted to the input of the circuit function C as an output stage. That is, in the circuit function B in the figure, at least the input section for receiving a signal from the circuit function A on the input stage side and the output section for the circuit function C on the next stage side are provided adjacent to each other. The internal circuit is conceptually a circuit having the same logical function as described above, and is scrambled according to the signal to be logically processed, but each logical gate circuit or flip-flop circuit is as much as possible. The signal processing system having the circuit function B1 and the signal processing system having the circuit function B2 are arranged close to each other and are laid out so that the signal processing system performs the same signal processing time.

Although not particularly limited, the semiconductor integrated circuit device is composed of a gate array. In a gate array, a desired logic circuit is configured by designing a wiring path by a master slice method with respect to a semiconductor chip in which basic gates such as logic gates are formed in an array. This structure is convenient for forming a pair of circuits having the above-mentioned circuit functions B1 and B2. That is, in the gate array, since the gates of the above units are arranged in an array, it is comparatively possible to select a gate circuit that performs the same signal processing as described above and a latch circuit that stores a signal adjacent to each other. This is because it can be done easily.

Functional block B for realizing the circuit function B
1 and B2 perform exactly the same signal processing to form an output signal. Therefore, two functional blocks B1 and B
It is not necessary to activate 2 and 3 at the same time. Therefore, when the functional block B1 is placed in the operating state, the functional block B2 is placed in the non-operating state. Conversely, functional block B2
Is placed in the operating state, functional block B1 is placed in the non-operating state.

When the semiconductor integrated circuit device is composed of a CMOS circuit, the input signal thereof is set to a fixed level when the functional block B1 or B2 is made inactive.
Therefore, in the case of a CMOS circuit, switching gate circuits or multiplexers are provided at the input parts of the small functional blocks b11 and b21, and the input signal on the inactivated side is set to a fixed level. When the signal is set to the fixed level in this way, no direct current path is formed in the CMOS circuit, so that no current is consumed and only heat is generated corresponding to the current consumed by one functional block B1 or B2.

ECL (or CM) semiconductor integrated circuit device
L: current mode logic) circuit, when the functional block B1 or B2 is set in the non-operating state, the constant current transistor for flowing the operating current of the logic gate is turned off. Therefore, in the configuration including the ECL circuit, one input signal is shared by the input circuits of the two small function blocks b11 and b21 without providing a switching gate circuit in the input parts of the small function blocks b11 and b21. Supplied. When the constant current transistor for supplying the operating current is turned off in this way, no current is consumed in the ECL circuit, so that only heat generation corresponding to the current consumed by one functional block B1 or B2 occurs.

As a result, the semiconductor chip is provided with two functional blocks B1 and B2 having the same circuit function for the purpose of defect defect relief and a backup function for high reliability. From the viewpoint of heat generation, only one functional block B1 or B2 exists. Therefore, only one functional block B1 or B2 is visible regarding the limitation of the number of elements that can be mounted on the chip due to heat generation. Therefore, in the semiconductor integrated circuit device according to this embodiment, the limit of the signal processing function that can be mounted is determined due to the limitation due to the chip size or the like, and as a result, it is possible to achieve a high degree of integration.

FIG. 2 is a block diagram showing an embodiment of the semiconductor integrated circuit device according to the present invention viewed from the constant voltage supply path side. In this embodiment, it is directed to a gate array composed of ECL circuits.

Constant voltage V formed by the constant voltage generating circuit
CS is output as constant voltages VCS1, VCS2 and VCS3 via the distribution circuit 1, the distribution circuit 2 and the distribution circuit 3. These constant voltages VCS1, VCS2, and VCS3 extend along the wiring channel between the gate columns of the gate array, although not particularly limited thereto.

The constant voltage VCS1 output from the distribution circuit 1 is supplied to the gate circuit and the flip-flop circuit which are constantly placed in the operating state like the circuit functions A and C. On the other hand, the constant voltage VCS2 output from the distribution circuit 2 is supplied to the gate circuit or the flip-flop circuit on the side of one of the functional blocks B1 which constitutes the functional block B, and the other function which constitutes the same functional block B is supplied. The constant voltage VCS3 output from the distribution circuit 3 is supplied to the gate circuit and the flip-flop circuit on the block B2 side.

In order to selectively activate the functional blocks B1 and B2 as described above, in other words, when one functional block B1 is activated, the other functional block B2 is deactivated. On the contrary, when the other functional block B2 is activated, one of the functional blocks B1 is deactivated, so that the distribution circuit 2 and the distribution circuit 3 have complementary output signals of the flip-flop circuit FF. Is controlled by Q and Q '.

When the flip-flop circuit FF is in the set state, the output signal Q becomes high level and the distribution circuit 2
Becomes the operating state, and the constant voltage VCS2 is output. As a result, an operating current is made to flow in the ECL circuit on the functional block B1 side. At this time, in the distribution circuit 3, the output signal Q ′ is set to the low level due to the set state of the flip-flop FF, the constant voltage VCS3 is set to the low level, the constant current transistor is turned off, and the operation of the ECL circuit on the functional block B2 side is performed. Cut off the current.

On the contrary, when the flip-flop circuit FF is in the reset state, the output signal Q'becomes a high level, the distribution circuit 3 is in the operating state, and the constant voltage VCS3 is output. As a result, an operating current is made to flow in the ECL circuit on the functional block B2 side. At this time, the distribution circuit 2
Is due to the reset state of the flip-flop circuit FF,
The output signal Q is set to low level, the constant voltage VCS2 is set to low level, the constant current transistor is turned off, and EC
The operating current of the L circuit is cut off.

The individual logic gates and flip-flop circuits that form the functional blocks B1 and B2 including the functional blocks A and C are optimally arranged corresponding to the circuits on the preceding stage side and the circuits on the output stage side. To the scrambled state. Even in this case, the constant voltage VCS as described above is corresponding to the functional block A, C, B1 or B2 to which it belongs.
The wiring process is performed so as to select 1, VCS2 and VCS3.

In particular, the internal logic gates and flip-flop circuits that form the functional blocks B1 and B2 are arranged as close to each other as possible, and finally the functional blocks B1 and B2 are made to correspond to the above. Although the wiring process is performed so that it is connected to either the constant voltage VCS2 or the VCS3, the voltage wiring process described above causes two functional blocks B1 and B2 can be operated alternatively.

FIG. 3 shows a layout diagram of an embodiment seen from the constant voltage supply path side in the semiconductor integrated circuit device according to the present invention. In this embodiment, it is directed to a gate array composed of an ECL circuit as described above.

A distribution circuit is provided corresponding to each gate row, and its output constant voltage is supplied to the constant voltage supply line according to which functional block the gate provided in each gate example is used for. Wiring is allowed to take place.

In this embodiment, a distribution circuit is provided corresponding to each column, but a plurality of gate columns may be provided corresponding to one distribution circuit. As described above, the number of distribution circuits and the number of gate rows can be variously changed according to the current supply capability of the distribution circuit.

In this embodiment, one constant voltage supply line is shown to be allocated between the gate columns, but a circuit to which two or more constant voltage supply lines are assigned to each gate column and the gate belongs to. It may be connected to any of the constant voltage supply lines depending on the functional block. Function block B
In the area where only 1 and B2 are configured, if the constant voltages VCS2 and VCS3 are alternately allocated between the gate columns, the wiring channels above and below the gate columns must always have VCS.
2 or VCS3 exists, so functional block B1 or B
The constant voltage supply to the logic gate or flip-flop belonging to 2 becomes simple.

FIG. 4 shows a circuit diagram of an embodiment of the semiconductor integrated circuit device according to the present invention. In the figure, the distribution circuit 2 and one gate circuit for receiving the output constant voltage VCS2 are exemplarily shown as a representative.
Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

Differential transistors Q1 and Q2 and an emitter follower output transistor Q3, a resistor R1 provided at the collector of the differential transistor Q2, a constant current source and an output transistor provided at the emitters of the differential transistors Q1 and Q2. Resistor R2 provided at the emitter of Q3
Forms a voltage follower circuit, receives the constant voltage VCS formed by the constant voltage generating circuit, amplifies the current, and outputs a constant voltage VCS2.

In order to control the output of the voltage follower circuit as described above by the control signal SC, the following control circuit is provided. The control signal SC is a signal output from the output terminal Q of the flip-flop circuit FF of FIG. This signal SC controls the operation as described above. The control signal SC is level-shifted through an emitter follower circuit composed of a resistor R4 provided at the emitters of the transistors Q6 and Q6. This level-shifted signal is supplied to the base of the differential transistor Q5. The reference voltage V of the ECL circuit is applied to the base of the differential transistor Q4 that performs a differential operation with the differential transistor Q5.
BB is level-shifted and input by the diode D1 and the resistor R3. A constant current source Ics is provided to the emitters shared by the differential transistors Q4 and Q5. The collector of the differential transistor Q4 is connected to the collector of the differential transistor Q2 of the voltage follower circuit.

The output constant voltage VCS2 of the distribution circuit 2 is E
It is supplied to the base of the transistor Q7 of the CL logic circuit. An emitter resistor R5 is provided at the emitter of the transistor Q7. As a result, the transistor Q7
Forms a constant current corresponding to the constant voltage VCS2 and the resistor R5. The collector of the transistor Q7 has a transistor Q8 receiving the reference voltage VBB and a transistor Q8.
8 and a transistor Q adapted to be operated differentially
It is connected to a common emitter with 9, Q10 and Q11. As a result, the constant current formed by the constant current transistor Q7 is caused to flow in either of the differential transistors Q8 or Q10 to Q11.

A load resistor RL is provided at the collector of the transistor Q8 and the common collector of the transistors Q9 to Q11 connected in parallel. An OR output OR is formed from the collector of the transistor Q8, and a NOR output NOR is formed from the shared collectors of the transistors Q9 to Q11.

When the control signal SC is at a high level due to the set output signal Q of the flip-flop circuit FF, etc., the transistor Q5 is turned on and the current of the constant current source Ics flows. Therefore, the voltage follower circuit current-amplifies the constant voltage VCS supplied to the base of the transistor Q1 and outputs it as the output constant voltage VCS2. This allows
Since the constant current transistor Q7 of the logic circuit forms a predetermined constant current, the logic circuit corresponding to it is activated.

When the control signal SC is at a low level due to the reset output signal Q of the flip-flop circuit FF or the like, the transistor Q5 is turned off, and instead the transistor Q4 is turned on. As a result, the constant current source I
The current of cs is applied to the resistor R1 of the voltage follower circuit. Therefore, the output constant voltage V of the voltage follower circuit is
CS2 is forced to the low level in response to the current flowing through the resistor R1 through the transistor Q4. As a result, the constant current transistor Q7 of the logic circuit is turned off. Due to the off state of the transistor Q7, no operating current flows through the logic circuit, and as a result, the logic circuit is deactivated. In the non-operating state due to the cutoff of the operating current, both the output signals NOR and OR of the ECL circuit become high level.

FIG. 5 is a circuit diagram of an embodiment of the input circuit in the semiconductor integrated circuit device according to the present invention. In this embodiment, a through latch circuit is used as an input circuit in order to make a diagnosis by boundary scan. Although the circuit symbols attached to the circuit elements in the figure partially overlap with those in FIG. 4, it should be understood that they respectively realize different circuit functions.

The number of input / output pins of a semiconductor integrated circuit device having a logical function has increased, and some of them have several hundreds of pins. As described above, in a logic LSI having a large number of input / output pins, it is difficult to diagnose the failure of the internal logic circuit. For example, when testing a logic LSI by a probe test, if the number of input / output pins (terminals) is large, the terminal spacing becomes narrow, and it is very difficult for the probe to accurately contact all terminals (pads). . In particular, CCB (Contro
In a lled collapse (bonding) type LSI, it is difficult to contact the probe with all pads because the distance between each terminal is short.

Therefore, as a diagnostic method for the logic LSI,
A serial scan method is known. This serial scan method is a method of operating as a shift register by connecting a plurality of flip-flop circuits in a logic LSI in series at the time of diagnosis. That is, at the time of diagnosis, first, a plurality of flip-flops are connected so as to operate as a shift register, and test data is written in each flip-flop circuit that constitutes the shift register. After that, each flip-flop circuit
By connecting the same circuit as in the normal operation, the test data can be supplied to the logic circuit in the subsequent stage of each flip-flop circuit. Next, the logic LSI is operated so that the test data is supplied to the subsequent logic circuit.

The subsequent logic circuit executes a predetermined logical operation in response to the test data, and the resulting data (test result data) is latched by a plurality of flip-flop circuits in the latter logic circuit. It The test result data is output to a tester provided outside the logic LSI by connecting the flip-flop circuit so as to operate as a shift register as described above.

Therefore, according to the diagnosis of the general scan method as described above, it is easy to test the logic circuit at the stage subsequent to the flip-flop circuit. However, in order to diagnose the logic circuit from the input circuit to the first flip-flop circuit, it is necessary to apply a probe to the input terminal and input the test signal.

In order to solve this problem, a boundary scan flip-flop circuit is provided at the input part of the logic LSI, and this flip-flop circuit holds test data (test pattern) at the time of diagnosis.
A method is known in which diagnosis using a probe is unnecessary. I E E E 1990 Bipolar Circuit and Technology Meeting (IEEE 19
90 Bipolar Circuit and Technology Meeting) 6,2 pp122
-131, there is disclosed a technique of forming a boundary scan flip-flop by combining an ECL circuit and a CMOS (complementary MOS) circuit.

A random scan method is known as another diagnostic method. This diagnostic method is configured so that each flip-flop in the semiconductor integrated circuit device can be addressed during diagnosis, which is different from the serial scan method described above. 1 in the semiconductor integrated circuit device at the time of diagnosis in the random scan system
One flip-flop circuit is brought into a selected state based on an address signal supplied from the outside of the semiconductor integrated circuit device. Then, the test data is set or the test data is read from the selected flip-flop circuit. Regarding such a random scan method, there is US Pat. No. 4,701,922. In the present application, as will be described later, a diagnostic function combining the boundary scan flip-flop and the random scan method is added.

In FIG. 5, the differential transistors Q1 and Q
A transistor Q7 that receives the clock CK is connected to the common emitter of 4. The emitter of the transistor Q7 is provided with a transistor Q12 that acts as a constant current source by supplying a constant voltage VCS to the base and an emitter resistor R5. The system data terminal IN is connected to the base of the transistor Q1. A reference voltage VBB such as -1.15V is supplied to the base of the transistor Q4. These circuits are input circuits for normal operation.

In order to add a latch function, the transistor Q7 is provided with a transistor Q8 in a differential form. A clock CKB having a phase opposite to that of the clock CK is supplied to the base of the transistor Q8. The collector of the transistor Q8 is provided with differential transistors Q5 and Q6 in the form of a latch in which the base and the collector are cross-connected to each other. The load resistor R1 is connected to the collectors of these differential transistors Q5 and Q6.
And R2 are provided.

The output signal of the latch section is output through the emitter follower output transistors Q10 and Q11. The emitters of the transistors Q10 and Q11 are connected to the output terminals Q and Q '. These transistors Q10
And emitters of Q11 have emitter load resistors R3 and R4
Is provided. Although not particularly limited, in order to reduce the current consumption, the power source to which the resistors R3 and R4 are connected is -2.
It is a VTT like V. On the other hand, the emitter resistor R5 forming the constant current source is connected to the power supply voltage VEE. In addition, the load resistors R1 and R2 and the output transistor Q
The collectors of 10 and Q11 are the ground potential (GND) of the circuit.
Connected to.

In this embodiment, in order to add the diagnostic function utilizing the flip-flop circuit as described above, the transistors Q7 and Q8 and the transistors Q13 and Q14 having a common emitter are provided. Transistor Q
The base of 13 is connected to the set terminal S. The base of the transistor Q14 is connected to the reset terminal R.
The collectors of these transistors Q13 and Q14 are connected to a pair of input / output nodes of the latch circuit, and when the transistor Q13 is turned on, the latch section is set, and when the transistor Q14 is turned on. Resets the latch section.

In the normal operation mode, both the set terminal S and the reset terminal R are set to low level. As a result, in the flip-flop circuit, when the clock signal CK is at the high level and the clock signal CKB is at the low level, the transistor Q7 is turned on and the transistor Q8 is turned off. When the transistor Q7 is turned on, a constant collector current of the transistor Q12 is caused to flow through the differential transistors Q1 and Q4, and when the transistor Q8 is turned off, no operating current flows through the transistors Q5 and Q6 in the latch section. As a result, the data terminal IN
The input signal supplied from the differential transistors Q1 and Q4
Also, the signal is directly transmitted to the output terminal Q through the output transistors Q10 and Q11, and its inverted signal is output from the output terminal Q '.

When the clock signal CK is set to the low level and the clock signal CKB is set to the high level, the transistor Q7 is turned off and the transistor Q8 is turned on accordingly. When the transistor Q8 is turned on, the collector constant current of the transistor Q12 is made to flow to the differential transistors Q5 and Q6 forming the latch part, and when the transistor Q8 is turned off, the transistor Q8 of the input part is turned on.
No operating current is passed through 1 and Q4. As a result, the input signal supplied from the data terminal IN is held by the latch units of the differential transistors Q5 and Q6 and output through the output transistors Q10 and Q11. Thus, when using a flip-flop circuit as an input circuit,
The clock signal CK is at a high level, and the clock signal C
KB is set to the low level to allow the input signal input from the data terminal IN to pass as it is. This also applies when a similar circuit is operated as an output circuit.

In the diagnostic mode, the clock signal CK is set to low level and the clock signal CKB is set to high level.
Then, the test data is input to the set terminal S and the reset terminal R. For example, when the transistor Q6 in the latch section is in the on state and the transistor Q5 is in the off state, when a high level is supplied to the set terminal S, the transistor Q13 is in the on state and the base of the differential transistor Q6 in the latch section. The potential is pulled out to a low level to turn it off. When the transistor Q6 is in the off state, its collector potential becomes high level and the transistor Q5 is turned on. As a result, the output terminal Q outputs a high level corresponding to the off state of the transistor Q6, and the output terminal Q ′ outputs a low level corresponding to the on state of the transistor Q5.

In the set state in which the transistor Q5 is on and the transistor Q6 is off as described above, when the set terminal S is set to low level and the reset terminal R is set to high level, the transistor Q14 is turned on. , The base potential of the differential transistor Q5 in the latch section is pulled out to a low level to turn it off. When the transistor Q5 is turned off, its collector potential becomes high level and the transistor Q6 is turned on. As a result, the output terminal Q outputs a low level corresponding to the ON state of the transistor Q6, and the output terminal Q ′ outputs a high level corresponding to the OFF state of the transistor Q5.

In the diagnostic mode, the flip-flop circuit operates as an SR flip-flop circuit by setting the clock signal CK to low level and CKB to high level.

In the normal operation, the clock signal CK of the flip-flop circuit FF becomes low level and C
When KB is fixed to the high level, it operates as an input circuit that allows the input signal to pass as it is. In the diagnostic mode, set / reset by random access scan operation without touching the probe to the input terminal. Can hold any input data. In the output circuit, output data can be read by a random access scan operation without touching the probe.

FIG. 6 is a circuit diagram for explaining the diagnostic mode using the flip-flop circuit as described above. In this embodiment, in order to explain the diagnostic operation by the random scan method, an address selection circuit, a data input circuit and an output circuit focusing on one flip-flop circuit are shown as representatives.

The output signals of the AND gate circuits G1 and G2 are commonly supplied to the set terminal S and the reset terminal R of the flip-flop circuits FF11 and FF21 belonging to the functional blocks B1 and B2. That is, the same address is assigned to the flip-flop circuits FF11 and FF21 having the same circuit function in the functional blocks B1 and B2. Output signals of the decoder DEC receiving the X address signal and the decoder DEC receiving the Y address signal are supplied to the inputs of the AND gate circuits G1 and G2. The set signal SET is supplied to the other one input of the AND gate circuit G1 corresponding to the set terminal S, and the reset signal RESET is supplied to the other one input of the AND gate circuit G2 corresponding to the reset terminal R. To be done.

Flip-flop circuits FF11 and FF21
The signal at the output terminal Q is supplied to the remaining one input of the AND gate circuit G3 which receives the output signal of the decoder as described above. The output signal of the AND gate circuit G3 passes the scan out data SOD through the OR gate circuit.
Is output as.

When the flip-flop circuit is designated by the decoder DEC, the gate circuits G1 to G3 open the gates. At this time, if the set signal SET is at the high level, the output signal of the AND gate circuit G1 is set to the high level. The circuit FF11 or FF21 is set. As described above, the flip-flop circuit FF11
Or when FF21 is selected, reset signal RES
If ET is at high level, the output signal of the AND gate circuit G2 is set to high level, so the flip-flop circuit FF
11 or FF21 is reset. Then, the output signal Q of the flip-flop circuit FF11 or FF21 selected by the address designation as described above is output as the scan out data SOD through the OR gate circuit G6.

As described above, the flip-flop circuit FF1
Since the operating current flows through only one of FF1 and FF21, there is no problem even if the inputs are shared as described above, and the flip-flop circuit FF11 or FF21 which is put into the operating state is set or reset. Then, the output signal Q is also input to the AND gate circuit G3, so that the output signal Q is automatically output. That is, the output signal of the logic circuit which is brought into the non-operating state is set to the high level (logic 1) in response to the stoppage of the operating current, so that it is brought into the operating state by utilizing the AND gate circuit. Things can be output automatically.

For example, the flip-flop circuit FF shown in FIG.
11 and the output signal Q of the FF 21 are input to the logic function C, they are combined using the AND gate circuit G4 and are input to the functional block C (not shown). As described above, in the case where the operating current of the ECL circuit is cut off to bring it into a non-operating state, all the output signals of the circuit placed in the non-operating state are all set to the high level, so the corresponding one is input to the AND gate circuit. By doing so, it is possible to equivalently output the output signals of the circuits that are equivalently operated in the form of a logical sum.

In the diagnostic mode as described above, the clock signal CK supplied to the flip-flop circuit FF is at low level and the clock signal CKB is at high level. In the normal operation, the clock signal C
K is set to the high level and the clock signal CKB is set to the low level. When switching from normal operation to diagnostic mode,
The data immediately before that is held in the flip-flop circuit FF11 or FF21 placed in the operating state, and the held data of the flip-flop circuit F11 or FF21 selected by the above address designation is used as the scan-out data SOD. Can be output.

FIG. 7 is an overall schematic diagram of the semiconductor integrated circuit device for explaining the above-mentioned diagnostic function. In the figure, each circuit block is shown according to the actual geometrical arrangement on the semiconductor substrate. That is, the X decoder is formed along one side of the logic LSI, and the output signal of the decoder is formed in the vertical direction, in other words, in the vertical direction. Wiring buses for test mode signals, scan-in data, and clocks are provided on the side opposite to the side on which the X decoder is provided, and branch lines for transmitting the signals are provided so as to be parallel to the output lines of the X decoder. It is provided.

A Y decoder is arranged along the other side adjacent to these, and an output OR gate circuit is formed along the other side facing the Y decoder. A data output line is provided along an output line formed to extend in the lateral direction from the Y decoder and is input to the OR gate circuit.

Inside the chip surrounded by these,
At the intersections of the output lines and output data lines of the decoder, cells that can form the flip-flop circuit and cells in which input / output elements are formed are arranged in an array. As a result, random access scan can be performed on the input circuit, the output circuit, and the internal data latch flip-flop circuit. Even in this case, in the functional blocks B1 and B2 corresponding to the circuit function B, since the flip-flops having the same function are arranged almost adjacent to each other, it is possible to easily assign the same address as described above.

In the failure diagnosis mode as described above, a test is performed with the circuit function B1 in the operating state, and the same test is performed again with the circuit function B2 in the operating state. In this configuration, since the test address and the test pattern by the tester are only repeated, the failure diagnosis can be performed by repeating the common test program despite having the circuit function for twice.

In the fault diagnosis as described above, when the defect exists on one side and the defect does not exist on the other side, the control signal is formed so that only the other circuit is always in the operating state.
Perform defect relief. If both circuits are non-defective, one of them can be used for backup such that one of them is in an operating state and the other circuit is switched to when an error occurs in the system.

The operational effects obtained from the above embodiment are as follows. That is, (1) the same input signal is input from adjacent input circuits, gate circuits having the same logical function are arranged in a close scrambled state, and corresponding output signals are output from adjacent output circuits. By providing at least a pair of signal processing circuits, one circuit of the pair of signal processing systems is in an operating state and the other is in a non-operating state so that the signal transmission paths between the normal circuit and the standby circuit are almost the same. Since the same can be done, it is possible to obtain the effect of improving the matching with the preceding circuit that forms the input signal and the succeeding circuit that receives the output signal.

(2) According to the above (1), since only one circuit is operated at any one time, the total current consumption is small, and since the entire circuit is dispersed, the circuit function that can be formed in one semiconductor integrated circuit can be increased. The effect is obtained.

(3) When the operating current of the ECL circuit is cut off to bring it into a non-operating state, the fact that all the outputs of the circuit brought into the non-operating state are set to the high level is utilized to make the two circuits It is possible to easily form the signal for transmitting the output signal to the next stage circuit by using the AND gate circuit.

(4) In fault diagnosis by random scan, the same address is assigned to the flip-flop circuits having the same circuit function so that the selection circuit becomes 1
An effect is obtained in that the circuit program is sufficient and the test program for one circuit can be executed by putting the above two circuits into the operating state and repeating the test twice in total.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the unit gate circuit, flip-flop circuit and boundary
Various embodiments can be adopted as specific circuits of the input circuit and the output circuit which form the flip-flop. The diagnostic mode may be performed by a probe test if possible. The semiconductor integrated circuit device may be composed of a pair of circuits from an input circuit to an output circuit. That is, the circuit function A or C in FIG. 1 is omitted, and a pair of circuit functions B having the same circuit function B from the external input terminal.
1 and B2 may be provided, or the output signals of the circuit functions B1 and B2 having the same circuit function B may be output to the external output terminal.

The semiconductor integrated circuit device may be composed of a random logic circuit other than the gate array. In the case of a circuit configured by a random logic circuit, a standard cell may be formed for each specific function such as an arithmetic circuit, and the standard cells may be combined to form a circuit. This invention is an ECL circuit or CM
It can be widely used for a semiconductor integrated circuit device including a circuit that does not consume current in an inactive state like an OS circuit.

[0073]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the same input signal is input from the adjacent input circuits, the gate circuits having the same logic function are arranged close to each other in the scrambled state, and the corresponding output signal is output from the adjacent output circuit. A pair of signal processing circuits are provided, and one circuit of the pair of signal processing systems is set in an operating state and the other circuit is set in a non-operating state, whereby the signal transmission paths of the normal circuit and the standby circuit can be made substantially the same. Therefore, it is possible to improve the matching between the front-stage circuit that forms the input signal and the next-stage circuit that receives the output signal, and since only one circuit is always in the operating state, the total current consumption is small and the circuit Since it is distributed throughout, the circuit function that can be formed in one semiconductor integrated circuit can be increased.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a block diagram showing an embodiment seen from the constant voltage supply path side in the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a layout diagram showing an embodiment seen from the constant voltage supply path side in the semiconductor integrated circuit device according to the present invention.

FIG. 4 is a circuit diagram showing an embodiment of a constant voltage distribution circuit and a logic circuit formed in the semiconductor integrated circuit device according to the present invention.

FIG. 5 is a circuit diagram showing an embodiment of an input circuit in the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a circuit diagram for explaining a diagnostic mode based on a random scan method.

7 is an overall schematic diagram of a semiconductor integrated circuit device for explaining the diagnostic function of FIG.

[Explanation of symbols]

A, B1, B2, C ... Circuit function, b11-b2b ... Small functional block, Q1-Q12 ... Transistor, RL, R1
-R5 ... Resistors, G1-G4 ... Gate circuits, FF, FF1
1, FF21 ... Flip-flop circuit, DEC ... Decoder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Shimizu 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Yuko Ito 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Kengo Miyazawa 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (5)

[Claims] 1. The same input signal is input from adjacent input circuits, gate circuits having the same logical function are closely arranged in a scrambled state, and corresponding output signals are output from adjacent output circuits. A semiconductor integrated circuit device comprising at least a pair of signal processing circuits according to claim 1, wherein one circuit of the pair of signal processing systems is in an operating state and the other is in a non-operating state. 2. The input circuit and the output circuit are provided with a latch function by combining flip-flop circuits, and the same addresses are assigned to corresponding ones of the flip-flop circuits of the internal circuit including these flip-flop circuits. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a failure diagnosing function that enables writing / reading by selecting by a selection signal formed by a common decoder circuit. 3. The input circuit, the internal circuit, and the output circuit are composed of an ECL circuit or a CML circuit, and a circuit in a non-operating state is a circuit in which a transistor forming an operating current is turned off. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the output signal output from the output circuit is input to an AND gate circuit that adopts positive logic in which a high level is logic 1. 4. The circuit that forms the input signal or the next-stage circuit that receives the output signal is provided with one circuit that is constantly operated as a common unit. The semiconductor integrated circuit device according to claim 2 or 3. 5. The claim 1, claim 2, claim 3 or claim 3, wherein the other signal processing circuit is used for repairing a defect of one signal processing circuit or for backing up the defect. The semiconductor integrated circuit device according to claim 4.