JPH06350062A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To accelerate or compensate an operation margin by a method wherein the reference voltage or operation current for an ECL circuit is made variable by means of the information being set in a register or the information formed on a program element that made possible to be written after the circuit test. CONSTITUTION:For an ECL circuit, a reference voltage VBB is fed to the base of a transistor that is driven for the transistor receiving an input signal, and it is determined whether the input signal is in a high level or in a low level. Moreover, the operation voltage is generated by a constant current transistor provided on the emitter that is common-connected to the operating transistor. Constant voltage VCS is fed to the base of that constant current transistor. By making the reference voltage VBB and constant voltage VCS be variable from outside, it is possible to find the circuit that is close to a margin with a margin acceleration test, and conversely, it is possible to compensate the margin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective for use in a semiconductor integrated circuit device such as a gate array composed of an ECL (emitter coupled logic) circuit. is there.

[0002]

2. Description of the Related Art In recent years, the number of input / output pins of a semiconductor integrated circuit device (hereinafter, sometimes referred to as a logic LSI) having a logical function has increased, and many have a few hundred pins. In this way, logic L with a large number of input / output pins
In SI, failure diagnosis of internal logic circuits becomes difficult. For example, when testing a logic LSI by a probe test, if the number of input / output pins (terminals) is large, the terminal spacing becomes narrow, and it is very difficult for the probe to accurately contact all terminals (pads). . In particular, CCB (Controll
In an LSI of the ed Collapse Bonding method, it is difficult to contact the probe with all pads because the distance between the terminals is short.

Therefore, as a diagnostic method for logic LSIs,
A serial scan method is known. This serial scan method is a method of operating as a shift register by connecting a plurality of flip-flop circuits in a logic LSI in series at the time of diagnosis. That is, at the time of diagnosis, first, a plurality of flip-flops are connected so as to operate as a shift register, and test data is written in each flip-flop circuit that constitutes the shift register. After that, each flip-flop circuit
By connecting the same circuit as in the normal operation, the test data can be supplied to the logic circuit in the subsequent stage of each flip-flop circuit. Next, the logic LSI is operated so that the test data is supplied to the subsequent logic circuit.

The subsequent logic circuit performs a predetermined logical operation in response to the test data, and the resulting data (test result data) is latched by a plurality of flip-flop circuits in the latter logic circuit. It The test result data is logically L level by connecting the flip-flop circuit so as to operate as a shift register as described above.
It is output to the tester provided outside SI.

Therefore, according to the diagnosis of the conventional general scan method, it is easy to test the logic circuit at the subsequent stage of the flip-flop circuit. However, in order to diagnose the logic circuit from the input circuit to the first flip-flop circuit, it was necessary to apply a probe to the input terminal and input the test signal.

In order to solve this problem, a boundary scan flip-flop circuit is provided at the input part of the logic LSI, and this flip-flop circuit holds test data (test pattern) at the time of diagnosis.
A method is known in which diagnosis using a probe is unnecessary. I E E E 1990 Bipolar Circuit and Technology Meeting (IEEE 19
90 Bipolar Circuit and Technology Meeting) 6,2 pp122
-131, there is disclosed a technique of forming a boundary scan flip-flop by combining an ECL circuit and a CMOS (complementary MOS) circuit.

A random scan method is known as another diagnostic method. This diagnostic method is configured so that each flip-flop in the semiconductor integrated circuit device can be addressed during diagnosis, which is different from the serial scan method described above. 1 in the semiconductor integrated circuit device at the time of diagnosis in the random scan system
One flip-flop circuit is brought into a selected state based on an address signal supplied from the outside of the semiconductor integrated circuit device. Then, the test data is set or the test data is read from the selected flip-flop circuit. Regarding such a random scan method, there is US Pat. No. 4,701,922.

[0008]

As described above, in the conventional semiconductor integrated circuit device, it is sufficient to test whether or not the internal circuit realizes a desired circuit function. However, among the good products, it was built into the actual system,
Some are found to be defective by the system operation test. Therefore, the inventor of the present application provides a function of forcibly accelerating a margin in a unit test of a semiconductor integrated circuit device to enable a more reliable circuit test,
We considered adding a function to compensate the operating margin by using a circuit for that purpose.

An object of the present invention is to provide a semiconductor integrated circuit device which realizes high reliability. Another object of the present invention is to provide a semiconductor integrated circuit device capable of compensating for an operating margin. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the reference voltage or the operating current of the ECL circuit is made variable according to the information set in the register or the information formed by the program element which is writable after the circuit test to accelerate or compensate the operating margin.

[0011]

According to the above-mentioned means, by accelerating the margin and performing the test, it is possible to wash out the marginal one and to make it defective, or to compensate the defective circuit by compensating the margin.

[0012]

1 is a schematic block diagram of an embodiment of a semiconductor integrated circuit device (logic LSI) according to the present invention. In order to facilitate understanding of the present invention, this figure is drawn focusing on the part related to margin acceleration and compensation. Therefore, a circuit portion having a function originally possessed by the semiconductor integrated circuit device is omitted.

Although not particularly limited, the circuit function portion originally possessed by the semiconductor integrated circuit device is constituted by a known gate array (not shown). Alternatively, it is configured by a standard cell system in which functional cells prepared in advance are combined, or a building block system in which functional blocks are combined.

In this embodiment, the input circuit and the output circuit are made to have a latch function in order to enable failure diagnosis without applying a probe to the input terminal and the output terminal. Although not particularly limited, the through latch circuit is also formed in the input circuit and the output circuit so that the through operation is performed in the normal operation and the latch operation is performed in the test operation.

The internal circuit as described above is composed of an ECL circuit. In the ECL circuit, the reference voltage VBB is applied to the bases of the transistors that are operated differentially with respect to the transistors that receive the input signal, and the high level /
A low level determination is made. The operating current is
It is formed by a constant current transistor provided on the commonly connected emitters of the differential transistors as described above.
A constant voltage VCS is supplied to the base of the constant current transistor.

In the present invention, the reference voltage VBB as described above is used.
A margin acceleration test is performed to wash out a circuit that is close to the margin by making the constant voltage V.sub.CS or the constant voltage V.sub.CS externally variable. On the contrary, margin compensation is performed.

The address register is supplied with an address designating a voltage generation circuit for accelerating the margin. This address signal is serially supplied as a scan-in signal. The decoder decodes the fetched address and forms one selection signal.

A control signal for accelerating the margin is supplied to the data register. This data is also serially supplied as a scan-in signal. Although not particularly limited, data is supplied following the address signal and set in the corresponding registers.

Each voltage generation / distribution circuit is provided with a data register D, a preset register, a selector for selecting the output of these registers, and a latch S for forming a selector switching signal. The output signal of the selector is supplied to the control circuit. The control circuit changes the output signal of the circuit for generating or distributing the constant voltage VBB or VCS according to the output signal of the register.

The address decoder has a gate circuit G1.
Form the selection signals of G3. These gate circuits G1 to G
The output signal of 3 forms the data fetch signal of the data register D and the set signal of the latch S corresponding to each voltage generation / distribution circuit.

When testing the acceleration margin and the like, the data designating the address designation of each voltage generation / distribution circuit and the change of the margin is input and written into each data register. As a result, the reference voltage VBB and the constant voltage VSC corresponding to each block can be adjusted.

The preset register P is composed of non-volatile storage means such as a fuse, although not particularly limited thereto. After the circuit function test by the margin acceleration as described above, it is used to change the direction of expanding the margin as necessary. That is, in the semiconductor integrated circuit device of this embodiment, in normal operation, after the power is turned on, a reset signal is input from the reset terminal to reset the latch S and each selector selects the preset register P. As a result, during normal operation, the output voltage of each voltage generation / distribution circuit outputs the voltage VBB or VCS corresponding to the contents of the preset register.

FIG. 9 is a block diagram of a base chip of an embodiment of a semiconductor integrated circuit device to which the present invention is applied. The base chip is configured by arranging internal gates and I / O columns in an array. Although not particularly limited, the clock signal is input from the input portion indicated by a white circle in the central portion of the chip, corresponding to the symbol shown in the clock distribution system.

The clock input terminals indicated by white circles extend above and below (left and right in the drawing) the base chip, and are branched to the left and right at an intermediate portion to be guided to a total of four first distribution portions indicated by black circles. Focusing on the first distribution section at the lower left of the base chip, it extends vertically from there, branches left and right on the lower side, is guided to two second distribution sections indicated by crosses, and branches leftward on the upper side. Then, it is guided to one second distribution portion indicated by a cross mark. From the first distributor on the bottom right, use the same pattern
It is led to the 2nd distribution part of a place. The upper half of the base chip is arranged point-symmetrically to the lower side. In this way, the second distributor is provided at 12 places in total.

From the above-mentioned second distributing section, it extends vertically above and below the base chip, branches left and right, and is guided to a total of four final distributing sections. As described above, each of the 12 second distributors has 4 final distributors, so that the total of the final distributors is 1
2 × 4 = 48 places are provided. A clock pulse is supplied to the flip-flop FF and the like from this final distribution unit. Since the flip-flops FF provided in the base chip of this embodiment have the same distribution system from the input terminals, there is no skew between the clocks and high-speed operation is possible.

Although not particularly limited, the reference voltages VBB and VCS are also distributed in correspondence with the above clock pulse distribution. Since the voltages VBB and VCS are DC voltages and do not have a problem such as a delay like a clock pulse, the base chip may be divided into larger parts and the distribution part may be provided. For example, four distribution units may be provided corresponding to the first distribution unit of the clock, and the voltages VBB and VCS may be supplied to each block formed by dividing the base chip into four.

FIG. 2 is a block diagram for explaining the relationship between the voltage generator and the distributor. In this embodiment, the case where only one register is used and only one of margin acceleration and compensation is performed is shown. FIG. 1
To add a function similar to the above, a selector may be provided at the input of the control circuit to selectively input the outputs of the data register and the preset register.

In this embodiment, a register and a control circuit are provided for the VBB (reference voltage) generating circuit and the VCS (constant voltage) generating circuit, and the output reference voltage VBB and the output constant voltage VCS can be adjusted. To be

Although not particularly limited, the reference voltage (reference voltage) VBB is provided separately for the input circuit and the internal circuit. That is, the reference voltage V for the input circuit is controlled by the distribution circuit controlled by the register and the control circuit.
BB1 and the reference voltage VBB2 for the internal circuit are formed. As described above, by changing the reference voltage VBB1 for the input circuit, the test is performed in a state in which the level margin of the input signal input through the external terminal is accelerated, and the marginal margin is washed out to make it defective. On the contrary, it is possible to compensate for a defective margin. On the other hand, by changing the reference voltage VBB2 for the internal circuit, it is possible to identify and compensate for the margin shortage due to the process variations of the elements of the semiconductor integrated circuit itself.

As described above, even with the same reference voltage VBB, the margin in the input circuit changes due to the other semiconductor integrated circuits and their signal transmission paths, whereas the margin in the internal circuit changes due to the process variations of its own. However, since the factors of fluctuations in the margins are different, they can be adjusted separately as described above.

Although not particularly limited, the constant voltage VCS is provided separately for the output circuit and the RAM (random access memory). That is, the constant voltage VCS1 for the output circuit and the constant voltage VCS2 for the RAM are formed by the distribution circuit controlled by the register and the control circuit. In this way, the level of the output signal output through the external terminal can be adjusted by changing the constant voltage VCS1 for the output circuit. Also, the constant voltage V of RAM
By changing CS2, the level of the output signal read from the RAM can be adjusted.

The distribution circuit for the reference voltage as described above is R
It may be provided for AM. Alternatively, a constant voltage distribution circuit may be provided for the input circuit. However, since the reference voltage and the constant voltage have a correlation with each other like the reference voltage and the signal level, it is sufficient to adjust one of them in practice.

The distribution circuit for the input circuit and the distribution circuit for the internal circuit may be provided in each of a plurality of blocks of the semiconductor integrated circuit device. Similarly, a distribution circuit for output or RAM may be provided by dividing the semiconductor integrated circuit device into a plurality of blocks or corresponding to a plurality of RAMs.

In this embodiment, a pulse width generating circuit is provided in addition to the reference voltage and the constant voltage. This pulse width generation circuit receives a clock input from the outside and adjusts the pulse width by a register or control circuit similar to the above. For example, marginal acceleration is performed by narrowing the pulse width of the clock pulse, and the circuit operation is tested, so that the marginal shortage is identified.

FIG. 3 shows a circuit diagram of an embodiment of the distribution circuit. This distribution circuit includes a differential transistor Q1.
And Q2, and the constant current source Io provided in the common emitter
A load resistor RL provided at the collector of the differential transistor Q2, an emitter follower output transistor Q3 whose base is supplied with the collector output voltage of the transistor Q2, and a load resistor R11 provided at the emitter of the transistor Q3. , An amplifier circuit composed of a feedback resistor R6 provided between its emitter and the base of the differential transistor Q2 is used. The resistors R6 and R
With 11, the basic gain of the amplifier circuit is set. Resistance R
When the resistance value of the resistor R11 is sufficiently larger than that of 6, the amplifier circuit operates as a voltage follower circuit having a gain of 1.

In order to adjust the voltage of the output terminal OUT to which the emitter of the output transistor Q3 is connected, the reference voltage VBB or the constant voltage VCS input from the input terminal IN is applied to the differential transistor Q1 through the resistor R1. Supplied to the base. Resistors R2 to R5 are provided between the base of the transistor Q1 and the negative power supply terminal (VEE) via the switches S1 to S4.

When the switches S1 to S4 are off, the voltage VBB or V input from the input terminal IN is input.
CS is directly transmitted to the base of the transistor Q1.
On the other hand, if any one of the switches S1 to S4 is turned on, the resistor R1 and the voltage dividing circuit are configured, and the voltage VBB or VCS input from IN is input after being reduced in level. It

Resistors R7 to R10 are also provided to the emitter of the output transistor Q3 via the switches S5 to S8. When the switches S5 to S8 are in the off state, the gain of the amplifier circuit is the
Set by. When any one of the switches S5 to S8 is turned on, the resistance R11 is different from the resistance R11.
Any of 7 to R10 are arranged in parallel to reduce the combined resistance and increase the gain.

The switches S1 to S8 are on / off controlled by the information bits set in the register. For example, the switch corresponding to the bit set to logic 1 is turned on, and the switch corresponding to the bit set to logic 0 is turned off. Although not particularly limited, the switches S1 to S8 are composed of MOSFETs (insulated gate MOSFETs).

A desired voltage is output from the output terminal OUT so as to perform margin acceleration or margin compensation by the combination of the level reduction due to the voltage division of the input level on the input side and the level amplification action by the gain setting of the amplifier circuit. You can Although not particularly limited, in the VBB generation circuit and the VCS generation circuit of FIG. 2 as well, the differential amplifier circuit as described above is arranged at the output section of each reference voltage generation circuit or constant voltage generation circuit, and its output level May be adjusted according to the information stored in the register.

FIG. 4 shows a circuit diagram of an embodiment of the pulse width generation circuit of FIG. In this embodiment, the input pulse supplied to the input terminal IN is supplied to the delay circuits DL1, DL2 and DL3 shown in the form of an AND gate circuit.
The delayed signals are formed, and the respective delayed signals are selectively formed through the AND gate circuits G1 to G3 and the OR gate circuit G4 in correspondence with the selection signals formed by the registers. The signal thus formed and the input pulse supplied from the input terminal IN are supplied to the AND gate circuit G5 to form a pulse width adjusted output pulse at the output terminal OUT.

The output pulse output from the output terminal OUT rises in synchronization with the high level of the input pulse and has a pulse width corresponding to the delay time of the delay circuits DL1 to DL3. When the gate circuit G1 is selected by the register, the output pulse having the narrowest pulse width defined by the delay circuit DL1 is formed. When the gate circuit G2 is selected by the register, an output pulse having a pulse width corresponding to the delay time of the delay circuit DL2 is formed. And
When the gate circuit G3 is selected by the register, the output pulse having the widest pulse width corresponding to the delay time of the delay circuit DL3 is formed.

In order to take in the input pulse as it is as an internal pulse, the latch S as described above is provided and a selector for selecting and outputting the output signal of the gate circuit G5 or the input pulse is provided. You can do this.

FIG. 5 shows a circuit diagram of an embodiment of the preset register shown in FIG. The circuit symbols in the figure partially overlap with those in FIGS. 3 and 4 in order to prevent the drawings from being complicated, but it is understood that each has a separate circuit function. I want to. This also applies to other drawings.

This circuit uses the fuse means F1 to F5 formed of a polysilicon layer or the like as a nonvolatile memory element or program element. A high level H signal is input to the gate circuits G1 to G5 through these fuse means F1 to F5. Gate circuit G1
Pull-down resistors R1 to R5 are provided between the input of G5 and the negative power supply voltage terminal VEE or VTT.

When the initial register output has a pattern such as HLLHL in a state where the fuse means F1 to F5 are not cut, the non-inverted signals are valid in the gate circuits G1 and G4 corresponding to the high level output H. Is output,
The gate circuits G2, G3 and G5 corresponding to the low level output L are output with the inverted output being valid.

The initial output pattern of the preset register as described above is set by the master slice method, although not particularly limited. For example, in a distribution circuit as shown in FIG. 3, in the case of configuring a preset register in which the voltage of the input terminal IN is current-amplified as it is and output from the output terminal OUT, the output of each gate circuit is output to the inverting terminal. All of the outputs are connected to the low level and the switches S1 to S6 are turned off.

According to the result of the circuit test, when the margin compensation is performed, the fuse means F1 to F5 are selectively cut by irradiating the laser beam to change the output bit of the preset register to maximize the margin. Is set as follows.

FIG. 6 is a circuit diagram of an embodiment of the input circuit in the semiconductor integrated circuit device according to the present invention. A through latch circuit is used as an input circuit in order to perform the above-described boundary scan diagnosis.

A transistor Q7 receiving the clock CK is connected to the common emitter of the differential transistors Q1 and Q4. The emitter of the transistor Q7 is provided with a transistor Q12 that acts as a constant current source by supplying a constant voltage VCS to the base and an emitter resistor R5. The system data terminal IN is connected to the base of the transistor Q1. A reference voltage VBB such as -1.15V is supplied to the base of the transistor Q4. These circuits are input circuits for normal operation.

In order to add a latch function, the transistor Q7 is provided with a transistor Q8 in a differential form. A clock CKB having a phase opposite to that of the clock CK is supplied to the base of the transistor Q8. The collector of the transistor Q8 is provided with differential transistors Q5 and Q6 in the form of a latch in which the base and the collector are cross-connected to each other. The load resistor R1 is connected to the collectors of these differential transistors Q5 and Q6.
And R2 are provided.

The output signal of the latch section is output through the emitter follower output transistors Q10 and Q11. The emitters of the transistors Q10 and Q11 are connected to the output terminals Q and Q '. These transistors Q10
And emitters of Q11 have emitter load resistors R3 and R4
Is provided. Although not particularly limited, in order to reduce the current consumption, the power source to which the resistors R3 and R4 are connected is -2.
It is a VTT like V. On the other hand, the emitter resistor R5 forming the constant current source is connected to the power supply voltage VEE. In addition, the load resistors R1 and R2 and the output transistor Q
The collectors of 10 and Q11 are connected to the ground potential of the circuit.

In this embodiment, in order to add the diagnostic function utilizing the flip-flop circuit as described above, the transistors Q7 and Q8 and the transistors Q13 and Q14 having a common emitter are provided. Transistor Q
The base of 13 is connected to the set terminal S. The base of the transistor Q14 is connected to the reset terminal R.
The collectors of these transistors Q13 and Q14 are connected to a pair of input / output nodes of the latch circuit, and when the transistor Q13 is turned on, the latch section is set, and when the transistor Q14 is turned on. Resets the latch section.

In the normal operation mode, both the set terminal S and the reset terminal R are set to low level. As a result, in the flip-flop circuit, when the clock signal CK is at the high level and the clock signal CKB is at the low level, the transistor Q7 is turned on and the transistor Q8 is turned off. When the transistor Q7 is turned on, a constant collector current of the transistor Q12 is caused to flow through the differential transistors Q1 and Q4, and when the transistor Q8 is turned off, no operating current flows through the transistors Q5 and Q6 in the latch section. As a result, the data terminal IN
The input signal supplied from the differential transistors Q1 and Q4
Also, the signal is directly transmitted to the output terminal Q through the output transistors Q10 and Q11, and its inverted signal is output from the output terminal Q '.

When the clock signal CK is set to the low level and the clock signal CKB is set to the high level, the transistor Q7 is turned off and the transistor Q8 is turned on accordingly. When the transistor Q8 is turned on, the collector constant current of the transistor Q12 is made to flow to the differential transistors Q5 and Q6 forming the latch part, and when the transistor Q8 is turned off, the transistor Q8 of the input part is turned on.
No operating current is passed through 1 and Q4. As a result, the input signal supplied from the data terminal IN is held by the latch units of the differential transistors Q5 and Q6 and output through the output transistors Q10 and Q11. Thus, when using a flip-flop circuit as an input circuit,
The clock signal CK is at a high level, and the clock signal C
KB is set to the low level to allow the input signal input from the data terminal IN to pass as it is. This also applies when a similar circuit is operated as an output circuit.

In the diagnostic mode, the clock signal CK is set to low level and the clock signal CKB is set to high level.
Then, the test data is input to the set terminal S and the reset terminal R. For example, when the transistor Q6 in the latch section is in the on state and the transistor Q5 is in the off state, when a high level is supplied to the set terminal S, the transistor Q13 is in the on state and the base of the differential transistor Q6 in the latch section. The potential is pulled out to a low level to turn it off. When the transistor Q6 is in the off state, its collector potential becomes high level and the transistor Q5 is turned on. As a result, the output terminal Q outputs a high level corresponding to the off state of the transistor Q6, and the output terminal Q ′ outputs a low level corresponding to the on state of the transistor Q5.

In the set state in which the transistor Q5 is on and the transistor Q6 is off as described above, when the set terminal S is set to low level and the reset terminal R is set to high level, the transistor Q14 is turned on. , The base potential of the differential transistor Q5 in the latch section is pulled out to a low level to turn it off. When the transistor Q5 is turned off, its collector potential becomes high level and the transistor Q6 is turned on. As a result, the output terminal Q outputs a low level corresponding to the ON state of the transistor Q6, and the output terminal Q ′ outputs a high level corresponding to the OFF state of the transistor Q5.

As described above, in the diagnostic mode, the flip-flop circuit operates as an SR flip-flop circuit by setting the clock signal CK to the low level and the CKB to the high level.

In the normal operation, the clock signal CK of the flip-flop circuit FF becomes low level and C
When KB is fixed to the high level, it operates as an input circuit that allows the input signal to pass as it is. In the diagnostic mode, set / reset by random access scan operation without touching the probe to the input terminal. Can hold any input data. In the output circuit, output data can be read by a random access scan operation without touching the probe.

The reference voltage VBB1 supplied to the base of the transistor Q4 is made variable according to the information set by the register 1. The register 1 is a data register or a preset register as described above. Alternatively, it is a data register or preset register selected through the selector.

By adjusting the reference voltage VBB as described above,
You can check the level merge of the input circuit. For example, as shown in the waveform diagram of FIG. 7, by forming a reference voltage VBB1 ″ whose level is lowered with respect to the reference voltage VBB1 and performing margin acceleration, an input circuit that is lagging the reference voltage VBB1 can be provided. It is washed out and the margin is insufficient, resulting in a defect.

On the contrary, based on the result of the margin acceleration as described above, the preset register is used to displace the reference voltage VBB1 'to the high level side so that the margin of the input level is expanded and the product is shipped as a good product. You can also

The adjustment of the reference voltage VBB as described above may be used to enhance the reliability by exclusively accelerating the margin and conducting the circuit test under more severe conditions. Those that become defective due to shortage may be used to relieve by using a preset register. The compensation may be performed so as to obtain the optimum margin from the result of the margin acceleration test.

In FIG. 6, the constant voltage VCS1 supplied to the base of the transistor Q12 is made variable according to the information set by the register 2. The register 2 is a data register or a preset register as described above. Alternatively, it is a data register or preset register selected through the selector.

By adjusting the constant voltage VCS1 as described above,
The output level transmitted to the internal circuit can be adjusted. For example, the constant voltage VCS1 is increased to increase the transistor Q1.
If the constant current value formed by 2 is increased, the resistance R1
And the current flowing through R2 increases, and the amplitude of the output level increases. On the other hand, if the constant voltage VCS1 is lowered to decrease the constant current value formed by the transistor Q12, the current flowing through the resistors R1 and R2 is reduced and the amplitude of the output level is reduced.

By adjusting the amplitude of such an output signal, the margin of the reference voltage VBB of the internal circuit can be examined. On the contrary, from the result of margin acceleration, the constant voltage VCS1 may be increased by the preset register to expand the output signal amplitude and increase the margin of the input level of the internal circuit.

When the circuit of FIG. 6 is used as an output circuit, it is used for level adjustment so as to compensate for variations in the amplitude of the output signal due to process variations of the element.

FIG. 8 shows a block diagram of an embodiment of an information processing system using the semiconductor integrated circuit device according to the present invention. A semiconductor integrated circuit device L according to the present invention is mounted on a mounting board (board) such as a printed wiring board.
The SI is installed to form one information processing and signal processing system.

For example, each semiconductor integrated circuit device LSI is
Each has the same microcomputer function, and it is like constructing one high-speed data processing system by performing distributed processing of information. Alternatively, each semiconductor integrated circuit device has a separate information processing or signal processing function, and each of them is combined on the board to form one information processing or signal processing system, or
It constitutes a section.

Each semiconductor integrated circuit device is provided with the functions for margin acceleration and margin compensation as described above.
They are connected to each other by a bus for transmitting a scan signal, a write signal and a reset signal provided on the board. This feature can also be used to compensate for system margin shortages on the board. That is, the output level is adjusted according to the input margin between the semiconductor integrated circuit devices mounted on the board, and conversely, the input reference voltage is finely adjusted according to the output level to adjust the output voltage on the board. A highly reliable system can be configured by expanding the signal transmission margin.

In order to improve the reliability in such a system, the preset register is written on the system. In order to enable writing on such a system, in the case of using a fuse means, it may be cut by an electric current instead of a laser beam. Alternatively, the preset register may be configured using a non-volatile storage element such as EPROM.

In the case where the power supply unit for generating the reference voltage or the constant voltage is provided on the board, the distribution circuit for voltage adjustment as described above is arranged in the power supply input unit of each semiconductor integrated circuit device. Good. With this configuration, individual semiconductor integrated circuit devices are only tested as in the past, but in a system operation test on the board, defective chips can be easily washed out due to accelerated margin, and compensation for insufficient margin etc. Can be done.

The operational effects obtained from the above embodiment are as follows. That is, (1) the reference voltage or operating current of the ECL circuit or the pulse width of the clock pulse is made variable by the information set in the register or the information formed by the program element writable after the circuit test to accelerate the operating margin. As a result, it is possible to wash out the marginal margin and to compensate for it.

(2) According to the above (1), the reliability on the system can be enhanced and the practical product yield can be enhanced.

(3) The system reliability can be improved by performing margin acceleration and compensation on a system composed of semiconductor integrated circuit devices mounted on the board. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, a concrete circuit forming a flip-flop circuit which is also used as an input circuit and an output circuit can adopt various embodiments. The test of the internal circuit may be performed by the probe test.

The semiconductor integrated circuit device is not only for a specific application such as a gate array or a standard cell system,
It may be anything configured by a random logic circuit. INDUSTRIAL APPLICABILITY The present invention can be widely used for an ECL circuit for identifying a high level / low level of a signal level using a reference voltage, or a semiconductor integrated circuit device capable of controlling an output signal amplitude by an operating current.

[0078]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the reference voltage or the operating current of the ECL circuit or the pulse width of the clock pulse is made variable by the information set in the register or the information formed by the program element that is writable after the circuit test to accelerate the operating margin and increase the margin. You can wash out slick things and compensate for them.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a block diagram for explaining the relationship between the voltage generator and the distributor of FIG.

FIG. 3 is a circuit diagram showing an embodiment of the distribution circuit of FIG.

FIG. 4 is a circuit diagram showing an embodiment of the pulse width generation circuit of FIG.

5 is a circuit diagram showing an embodiment of the preset register of FIG.

FIG. 6 is a circuit diagram showing an embodiment of an input circuit in the semiconductor integrated circuit device according to the present invention.

7 is a waveform chart for explaining an example of the operation of the input circuit of FIG.

FIG. 8 is a block diagram showing an embodiment of an information processing system using the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a configuration diagram of a base chip showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied.

[Explanation of symbols]

S ... Latch, D ... Data register, P ... Preset register, Q1-Q12 ... Transistor, R1-R10 ... Resistor, Io ... Constant power supply, S1-S8 ... Switch, DL1-D
L3 ... Delay circuit, G1 to G5 ... Gate circuit, F1 to F5
... fuse means, LSI ... semiconductor integrated circuit device.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yuko Ito 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Takeo Yamada 2326 Imai, Ome City, Tokyo Hitachi Device Development Center (72) Inventor Kengo Miyazawa 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (7)

[Claims] 1. An ECL circuit and a first for supplying a reference voltage to an input signal of the ECL circuit to the ECL circuit.
And a means for changing the output voltage of the first constant voltage generating circuit according to the information set in the first register. 2. An ECL circuit, a second constant voltage generating circuit which forms a constant voltage supplied to the base of a constant voltage transistor which forms an operating current of the ECL circuit, and a second constant voltage generating circuit. And a means for changing the output voltage according to the information set in the second register. 3. A circuit in which a plurality of ECL circuits are arranged by being divided into a plurality of circuit blocks, and an output voltage of a first constant voltage generating circuit which forms a reference voltage for an input signal of the ECL, or an operating current of the ECL. Distribution circuit for amplifying the output voltage of the second constant voltage generating circuit that forms the constant voltage supplied to the base of the constant voltage transistor that forms the current and transmitting it to the ECL circuit of the corresponding block, and the output voltage of each distribution circuit And a means for changing the information according to the information set in the register. 4. An ECL circuit, a first constant voltage generating circuit that supplies a reference voltage to an input signal to the ECL circuit, and an output voltage of the first constant voltage generating circuit are writable after a circuit test is completed. And a means for changing the information according to the information formed by the program element, the semiconductor integrated circuit device. 5. An ECL circuit, a second constant voltage generating circuit that forms a constant voltage supplied to the base of a constant voltage transistor that forms an operating current of the ECL circuit, and a second constant voltage generating circuit. A semiconductor integrated circuit device, comprising: means for changing the output voltage according to information formed by a writable second program element after the circuit test is completed. 6. A circuit in which a plurality of ECL circuits are arranged by being divided into a plurality of circuit blocks, an output voltage of a first constant voltage generating circuit which forms a reference voltage for an input signal of the ECL, or an operating current of the ECL. Distribution circuit for amplifying the output voltage of the second constant voltage generating circuit that forms the constant voltage supplied to the base of the constant voltage transistor that forms the current and transmitting it to the ECL circuit of the corresponding block, and the output voltage of each distribution circuit And a means for changing the information according to information formed by a writable program element after the circuit test is completed. 7. A digital circuit which operates by receiving a clock pulse supply, and a clock pulse formed by an internal circuit or a clock pulse supplied from an external terminal to receive information stored in a register or a circuit test end A semiconductor integrated circuit device comprising: a clock width adjusting circuit which changes a pulse width according to information formed by a program element which is writable later and supplies the pulse width to the internal circuit.