JPH0626234B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device,
In particular, the present invention relates to a master slice type semiconductor integrated circuit device which is capable of significantly reducing the pad dedicated to diagnosis entrance / exit and is suitable for obtaining a high diagnosis detection rate.

[Background of the Invention]

The master slice LSI is to manufacture an LSI having a desired electric circuit operation by creating only a mask corresponding to a wiring among ten or more masks used when manufacturing the LSI according to the development type.

The configuration of a conventional master slice LSI is shown in FIG. L
The SI chip 11 has a bonding pad and an inlet / outlet circuit area 12 on the outer periphery thereof, and a basic cell row 14 in which basic cells 13 composed of elements such as transistors are arranged in the X-axis direction is repeated inside the wiring area 15 in the inside. The arrangement is adopted. To obtain a desired electric circuit operation, one or several adjacent basic cells 13 are connected to form a NAND.
Gates, flip flops, etc. are formed (hereinafter, the logic gate formed in this way is called a block). Then, by connecting according to a logic diagram between various logic blocks formed by a plurality of basic cells 13, one LS is formed.
Form I. Placement and wiring of logic blocks are automatically performed by a DA system (Design Automation System).

FIG. 3 is a plan view showing an example of a conventional basic cell 13. The basic cell 13 is a P-type MOS transistor (hereinafter P
P ⁺ type region 20 serving as a source or drain of a MOS), N ⁺ type region 21 serving as a source or drain of an N-type MOS transistor (hereinafter referred to as NMOS),
P formed in an N-type substrate to form an N ⁺ -type region
-WELL region (not shown), PMOS and NMOS poly-Si gate electrode (one of which is shared by the PMOS and NMOS) 22, V _cc is supplied to the power supply voltage to both transistors
It is formed of a power supply line 25 and a GND power supply line 26. In this case, the mask (custom mask) that changes for each product type is the P
⁺ Type region 20 or N ^{+ type} region 21, poly-Si electrode 22
Of contact holes (referred to as CT holes) for connecting the Al1 wiring with the Al1 wiring, the Al1 wiring mask, the Al1 wiring and A
There are a few masks of contact holes (referred to as TH holes) in the interlayer insulating film for connecting the 12 wiring and four Al2 wiring masks. In FIG. 3, reference numerals 23 and 24 denote V to the N-type substrate and the P-WELL region through the CT holes, respectively.
P ⁺ type region for supplying _cc potential and GND potential, N ⁺
It is a type area.

FIG. 4 (a) shows an example in which a logic block of a 3-input NAND gate (a logic symbol is shown in FIG. 4 (b)) is formed on the basic cell array 14. The underlying basic cells are symbolized by using transistor symbols for simplification, and the same or equivalent components as those shown in FIG. 3 are represented by the same symbols. Fourth
In Figure (a), the thick black solid line is Al1 wiring and the dotted line is Al2.
Wiring, x marks are CT holes, and □ marks are TH holes. A 2-input NAND transistor is connected by the Al1 wiring, and the input terminals A, B, C (equipotential terminals A ', B', C ') are made of Al.
The output terminal D (equipotential terminal D ') is formed by one wire and is formed by an Al2 wire. As described above, various logic blocks are formed by forming the transistor connection pattern mainly using the Al1 wiring. Then, these logic blocks are arranged at arbitrary positions in the basic cell row 14, and between the logic blocks in the wiring region 15 mainly in the X direction Al1.
Wiring is performed using Al2 wiring in the Y direction and TH holes at the connection points. In the input / output circuit area 12, input / output circuit cells (I / O cells) for forming an input / output buffer are arranged.

By the way, in a logic LSI, the number of failure circuits exponentially increases with the high integration, and thus it becomes difficult to create a test pattern that can detect all failures in the LSI, and at the same time, the work man-hour (diagnosis) The number of man-hours) increases sharply. In particular, in the case of a gate array, the ratio of diagnostic man-hours to the total man-hours required for developing products is large, which is a major reason for shortening the development period. Therefore, in general, custom L
In the case of SI, a so-called divided diagnosis method is widely adopted in which the entire circuit is divided into a combination circuit group and a sequential circuit group, and the diagnosis is performed for each combination circuit group. In this case, each flip-flop must have a function of writing (skipping in) and reading (skipping out) the diagnostic data (input test pattern or output test pattern of the combinational circuit group) from an external pin. On the other hand, diagnostic pins for inputting / outputting diagnostic data have large restrictions because they cannot be shared with normal pins. Therefore, the circuit system for diagnosis has large restrictions. For example, there is an LSSD method in which internal flip-flops are connected in a shift register shape to reduce the number of pins dedicated to diagnosis, and scan-in and scan-out are performed by the shift register operation (Japanese Patent Publication No. 5).
7-3107, Level sensitive test method for logic devices, IB
Company M). However, the number of test steps tends to be large when applied to a master slice LSI.

Therefore, there is an example in which a part of the logic circuit is incorporated in all the I / O cells in the chip (Japanese Patent Laid-Open No. 58-44741). However, when the number of I / O cells is large, the required gate area increases. Tend.

[Object of the Invention]

It is an object of the present invention to provide a diagnostic circuit built-in type master slice LSI in which normal pins can also be used as diagnostic pins to improve diagnostic performance.

[Outline of Invention]

The present invention is intended to reduce the number of dedicated diagnostic pads by implementing a circuit system in which the normal diagnostic pad can also be used as a diagnostic pad when the divided diagnostic system is applied to the gate array. We are considering application to a diagnostic method that reads / writes (skian out, skiin in) simultaneously for several bits.

FIG. 5 shows a chip configuration of a gate array LSI to which the above-mentioned divisional diagnosis method is applied and the present invention is applied. In the chip 11, the I / O cell region 45 in the peripheral region 12 has an I
/ O cells, for example, 44-0 to 44-4 are arranged, and various logic blocks are arranged in the basic cell column 14. For convenience of explanation, here, the entire circuit is a combinational circuit group 41-
1 and combination circuit block 41-2, FF block 40-
It is assumed to be divided into 1, 40-2 and 40-3. Reference numeral 42 is a diagnostic timing generating circuit block including a decoder and a random gate, and 43-1 to 43-4 are I / O cell control logic blocks, all of which are diagnostic additional circuit blocks.

The diagnosis procedure is as follows. First, the diagnostic signal group 46 having diagnostic dedicated pads such as diagnostic clock and read / write signal and the FF address signal ADR are input to the diagnostic timing generation circuit block 42, and the read / write signal group 47 of each FF block is generated. The individual FF blocks are selected by the signal group 47, and the diagnostic input data SI0, SI1 and diagnostic output data SO0 are input from an external pad (not shown) via a diagnostic bus (bidirectional data bus) indicated by a solid black line. , SO1 are input and output, respectively. In order that the diagnostic pad and the normal pad can be used in common, the normal mode and the diagnostic mode are provided, and the I / O in the diagnostic mode is set.
The cells 44-0 to 44-2 are used as input buffers for I / O.
Cells 44-3 and 44-4 need to act as output buffers. Therefore, in the present invention, since the I / O cell logic function is switched by the normal mode / diagnosis mode signal, the I / O cell control logic blocks 43-1 to 43-4 are inserted into the diagnosis bus. The logic block for controlling the I / O cell is composed of an internal logic block. If the signal logic in the normal operation mode is inserted between the I / O cell and the internal logic block connected in the user-designed logic diagram without changing the signal logic. Since it is good, it is convenient to automatically generate a diagnostic circuit by a DA program. Further, since the I / O cell control logic block is generated by the number of necessary diagnostic pads, all logic functions equivalent to the I / O cell control logic block are stored in the I / O cell. Compared with the method, the area of the diagnostic additional circuit can be significantly reduced. For example, in the latter method, the maximum number of I / O cell control blocks is 6.
Comprised of a gate (converted to 2-input NAND), the number of pads is 1.
In the case of 80, 1080 gates are also spent as a diagnostic circuit.

The diagnostic additional circuit block may be automatically arranged in the same manner as a normal logic block, or an I / O to be connected in advance before being automatically arranged and wired.
It may be fixedly arranged near the cell. In this case, a good result can be expected for the automatic wiring by the automatic wiring program, that is, the number of unwired wires can be reduced.

Here, FIG. 6 shows the principle of insertion of the logic block for controlling the I / O cell. FIG. 6 (a) shows a case of normal logic, in which the I / O cell 100 has wirings A, B, ... N for an internal logic block (not shown), and a wiring 103 has a bonding pad (hereinafter referred to as "bonding pad").
Simply referred to as a pad) 102. Here, the normal logic means a logic without a diagnostic additional circuit or a logic designed by a logic designer (customer or user in the case of a gate array) without being aware of the diagnosis. In this logic, since the pad 102 is also used for diagnosis, an I / O cell control logic block 101 is inserted between the internal logic block and the I / O cell 100 as shown in FIG. 6 (b). To do. In the logic block 101, a signal line group 104 is a diagnostic signal line group, and includes a diagnostic mode signal, a diagnostic write timing signal,
A diagnostic read timing signal and the like are superposed, but these are determined by the type of the I / O cell control logic block 101.

As is apparent from the above configuration, the connection relationship (normal logic circuit) between the signal lines A, B, ... N and the internal logic block is unchanged by the addition of the I / O cell control logic block. Moreover, in the normal operation mode, the signals A, B, ...
The signal logic between the pad 102 and the pad 102 is kept the same as in the case of FIG. 6 (a). The present invention is characterized in that the I / O cell control logic block is inserted for each pad that is used for both normal and diagnostic purposes, that is, for each I / O cell (the pad corresponds to the I / O cell). Is.

Although the signal delay of the normal path increases due to the insertion of the logic cell, the effect is small as described in the embodiment.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. First
The figure shows the combinations of I / O cells and I / O cell control blocks for various logic functions required in the diagnostic mode when the pad specifications are input, output, and 3-state input / output buffers in the normal mode. It is a thing.

First, consider the case of input buffer in normal mode. That is, when there is no diagnosis, it is represented by the I / O cell 61 as shown in FIG. Here, 62 is a pad, K is an input signal, and k is an output signal of the I / O cell.

Figure 1 (b) shows the case of address input in diagnostic mode,
Inverter blocks 63 and 63 'are connected to the signal k line to supply the address signal a _i to the internal logic circuit. The speed of the signal k is not so much influenced by the load being one fanout and the Al wiring being slightly increased. In the case of inputting the diagnostic data, as shown in parentheses in FIG. 1 (b), the 3-state buffer block 64 controlled by the write timing signal SW is connected to the signal k line, and the diagnostic data d _j is supplied to the internal logic circuit. Supply. The 3-state buffer 64
Is the circuit shown in FIG. 7 (clocked gate inverter)
Is formed by. That is, the PMOS transistor M1,
M2 and NMOS transistors M3 and M4 are connected to the _Vcc terminal 72
And a GND terminal 73 are connected in series, the input signal k is commonly input to the gate electrodes of M1 and M4 via the inverter 70, and the write timing signal SW is supplied to the gate electrode of M3 and the inverter of M2 via the inverter 71. Input to the gate electrode. Therefore, the write timing signal SW
Is at "0" level, the gate electrode input of M2 (output of the inverter 71) is at "1" level, and the gate input of M3 is at "0" level, so M2 and M3 are off, that is,
The output signal d _j is in a high impedance state. next,
When the signal SW is at "1" level, the level is opposite to the logic level, so that both M2 and M3 are turned on, and the d _j output becomes the same logic level output as the signal k.

On the other hand, the case of data output in the diagnostic mode is shown in FIG. 1 (c). Output D of output buffer 62 'in normal mode
_In order to prevent the competition between _j and the input signal k, the input buffer I /
The O cell 61 is a 3-state input / output buffer I / O cell 62.
And is controlled by the read timing signal SR. The I / O cell 62 is actually shown in the circuit configuration of FIG. 8, and the 3-state buffer 62 'has a _Vcc terminal 72 and a GN.
A PMOS transistor M5 and an NMOS transistor M whose source and drain are connected in series between the D terminals 73
6, and an internal logic block 62 ″ for controlling three states. The logic block 62 ″ is a 2-input NAN.
D80, 2-input NOR 81, and inverter 82.
The operation will be described. First, in the normal mode, the read timing signal SR is at "0" level,
Since one of the inputs of D80 becomes "0" level and one of the inputs of the 2NOR 81 becomes "1" level, the signal line 83 becomes "1" level, the signal line 84 becomes "0" level, and M
Both 5 and M6 are turned off. Therefore, the signal K / D _j
The line goes into a high impedance state and pad 62 functions as an input pad. Next, when the read timing signal SR is at "1" level (occurs in the diagnostic mode), one of the inputs of the 2NAND 80 is at "1" level and the 2NO
Since one of the inputs of R81 is at "0" level, both signal lines 83 and 84 are at the inverted logic level of the diagnostic data d _j , and the output signal K / D _j is at the same logic level as d _j . The 3-state output buffer 62 'may be of the clocked gate inverter type shown in FIG. 7, and in this case, there is an advantage that the 3-state controlling internal logic block 62 "is unnecessary.

Consider the case where the I / O cell is the output buffer in the normal mode. When the diagnostic pad is unnecessary, the I / O cell forms an output buffer 65 as shown in FIG. 1 (d). S is an input signal of the output buffer, and S is an output signal.

FIG. 1 (e) shows the case of using as an address input pad in the diagnostic mode (mode signal M = "0"). That is, I
/ O cell 65 is a 3-state input / output buffer I / O cell 6
Replaced with 2. The 3-state input / output buffer 62 comprises a 3-state output buffer 62 ′ controlled by the diagnostic mode signal M and a input buffer 61. In the diagnostic mode (M = "0"), the output of the output buffer 62 'with three states is in a high impedance state.
The address signal A _i is input to the input buffer 61, and the address signal a _i is supplied to the internal diagnostic logic. 3 state buffer 6 for diagnostic data input
4 is added, and diagnostic data d _j is generated in synchronization with the write timing signal SW (when SW = “0” level, d
_{The j} signal line is in a high impedance state). In the normal mode (M = "1"), the 3-state output buffer 62 'constitutes a normal non-inverting output buffer and outputs the output signal S from the external pad. In this case, the output side load capacitance increases by the amount of the gate capacitance of the input buffer 61, but is sufficiently smaller than the external load capacitance,
The influence of the output signal S on the speed is small.

When it is also used as diagnostic data output, it is shown in FIG. 1 (f). The I / O cell 65 constitutes an output inverting buffer as usual, but a multiplexer logic block 67 is inserted between the I / O cell 65 and the input signal.
In the diagnostic mode, when the read timing signal SR = “1”, the multiplexer block 67 selects the diagnostic data d _j and the I / O cell 65 outputs the diagnostic data D _j . In the normal mode, SR = "0", and this time, the normal input signal is selected and the normal operation is performed.

In normal mode, 3-state input / output buffer I / O
A case where the cell (FIG. 1 (g)) is also used for diagnosis will be described. In FIG. 1 (g), c is a 3-state control signal, s is an input signal of the output buffer 62 ', K is an input signal of the input buffer 61, and the I / O cell 62 is actually the same as in FIG. 1 (c). Same logic block 62 ″ and I / as described
It is composed of O cells 62.

FIG. 1 (h) shows the case where it is also used as an address input.
In this case, the I / O cell 62 is unchanged and a 2-input AND gate block 68 is added. It should be noted that not only this figure but the same and equivalent parts as those described above are represented by the same symbols. In the diagnostic mode (M = "0"), the output of the 2-input AND gate block 68 becomes "0" level, and the buffer with 3-state 6
Since 2'is turned off, the address input A _i is input via the input buffer 61 and the inverter blocks 63, 63 '. When also used as diagnostic data input, the first
3-state buffer block 64 shown in parentheses in Figure (h)
To add. Since the operation is the same as the above, it is omitted. In the normal mode (M = "1"), the 2-input AND gate block 68 output has the same logic level as that of the 3-state control signal c, so that the I / O cell 62 forms a normal 3-state input / output buffer.

FIG. 1 (i) shows a case where it is also used as diagnostic data output. In this case as well, the I / O cell may be the same as the normal 3-state input / output buffer I / O cell 62, but a new 2-input OR gate block 69, 2-input 2-wide AND-O is newly added.
The R gate 70 is added. In diagnostic mode (M =
"0") indicates that the output of the OR gate block 69 is "1".
Since it is at the level, it operates as a 3-state output buffer 62 'non-inverting output buffer. Also,
Since the gate 70 outputs the diagnostic data d _j , the diagnostic data D _j is output to the external pad. On the other hand, in the normal mode (M = “1”), the gate 70 outputs the normal input signal S, and the OR gate normally outputs the 3-state control signal c.
Since it is supplied to the buffer with state 62 ', the normal output signal S is output to the external pad when the signal c is at "1" level. That is, normal operation is performed.

[Effect of the Invention] According to the present invention, since a pad for normal use at an arbitrary position can also be used as a pad for diagnostic use, the number of dedicated pads for diagnosis can be minimized and at the same time the fault detection rate can be increased by the additional diagnostic circuit. There is an effect that can be increased. Further, since the I / O cell control circuit is incorporated not in the I / O cell but in the internal logic block, it is sufficient to prepare as many diagnostic blocks as the number of diagnostic pads, which is advantageous in that the diagnostic additional circuit area can be reduced. is there. Further, since the I / O cell control block is inserted between the normal internal logic blocks connected to the corresponding I / O cell, the diagnostic circuit can be easily generated by DA.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the structure of the present invention, FIG. 2 is a chip plan view showing the structure of a conventional master slice LSI, and FIG. 3 is a plan view showing an example of a conventional basic cell. Fourth
Figure (a) is a connection diagram showing a conventional logic block, Figure 4 (b) is a logic symbol diagram, Figure 5 is a chip plan view showing the outline of the present invention, and Figure 6 is a block showing the principle of the present invention. FIG. 7, FIG. 7 and FIG. 8 are circuit diagrams supplementarily explaining FIG. 100 ... I / O cell, 101 ... I / O cell control logic block, 61 ... Input buffer, 62 ... 3-state input / output buffer, 62 '... 3-state output buffer, 63, 63' ... … Inverter gate, 64 …… Internal buffer with 3 states, 65 …… Inverted output buffer, 6
7: Multiplexer block, 69: 2-input OR
Gate, 70 ... 2 Wide 2-input AND-OR gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ikuro Masuda Inventor Ikuro Masuda 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Research Institute, Ltd. Inside Hitachi Research Laboratory (72) Inventor Toshiaki Masuda 32-1 Sachimachi, Hitachi City, Ibaraki Hitachi Engineering Co., Ltd. (56) Reference JP-A-59-111343 (JP, A)

Claims (5)

[Claims] 1. A column of basic cells made up of transistor elements is arranged on a semiconductor chip, and I / O cells made up of transistor element groups forming an input buffer and an output buffer are arranged at the periphery of the semiconductor chip. In a master slice type semiconductor integrated circuit device in which an external pad connected to the I / O cell is arranged around the semiconductor chip, a unit for generating a signal such as a diagnostic timing signal according to a normal mode / diagnostic mode control signal, An I / O for switching the connection between the logic block formed by the basic cell in the normal mode or the diagnostic logic block formed by the basic cell in the diagnostic mode and the I / O cell according to the signal such as the diagnostic timing signal. A cell control logic block is arranged in a column of the basic cell, and the I / O cell and the logic block The I / O between
A semiconductor integrated circuit device characterized in that logic blocks for cell control are connected by wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein the I / O cells are assigned to a first I / O buffer circuit that inputs and outputs signals in the normal mode and the external pad. The second I / O buffer circuit for inputting / outputting the generated diagnostic signal and the output terminal of the first I / O buffer circuit or the second I / O buffer circuit in a high impedance state according to the normal mode / diagnosis mode control signal. And a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the I / O cell and at least one logic block such as a flip-flop are used for diagnostic scan-in or scan-out data. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected through a bus line, and the I / O cell control logic block is inserted on the bus line. 4. The semiconductor integrated circuit device according to claim 1, wherein the I / O cell and the logic block for controlling the I / O cell are diagnostic mode signals. Alternatively, a semiconductor integrated circuit device, which receives a scan-in timing signal or a scan-out timing signal as an input. 5. The semiconductor integrated circuit device according to any one of claims 1, 2, 3, and 4, wherein the I / O cell control logic block includes a plurality of logic blocks. A semiconductor integrated circuit device.