JP2000111615A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit system capable of reducing an area overhead by a scan circuit. SOLUTION: Scanning flip-flop circuits 11-1 to 11-j are arranged with every input terminal, output terminal and input/output terminal of respective modules 10 in an integrated circuit, and a module terminal is arranged through the flip-flop circuits 11-1 to 11-j. The respective modules 10 have shift scan circuits by connecting the flip-flop circuits 11-1 to 11-j in a chain shape at test mode time. A test of the integrated circuit is performed by shift-scanning the whole chip by connecting the shift scan circuits of the respective modules 10 in a chain shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (L).
More specifically, the present invention relates to a technology that can easily perform tests and diagnoses and reduce test design man-hours and test costs, particularly to an LSI designed by incorporating a module and a design property (IP) circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device (hereinafter, referred to as an LSI), it is necessary to reduce the number of test pattern steps and make the failure detection rate by the test pattern close to 100% in order to improve mass productivity and reliability. There is.

In an LSI including a logic circuit, an input signal of a test pattern is externally added, and an output signal is compared with an expected value to determine whether various elements can obtain desired functions and performances. This is commonly called a test. Here, the input test pattern needs to be one that can test the internal elements without omission, and the ratio of the number of testable elements to the total number of elements is defined as the detection rate. When making an input test pattern, it is necessary to achieve a practically sufficient detection rate with as few steps as possible.

However, in a highly integrated LSI having a scale of several hundred thousand to several million gates, it is difficult to increase a detection rate only by a test pattern, and a test circuit for increasing the detection rate is added. I have. However, there is a problem that the entire circuit scale is increased by the test circuit, and the degree of integration of the chip is reduced.

[0005] Usually, a division test (diagnosis) system is used. In this method, the whole logic circuit is divided into a flip-flop (FF) group and a combination circuit group surrounded by the FF group, and the failure detection of the whole logic circuit is replaced with a test (detection) of the combination circuit group. Things. Therefore, the internal flip-flop (FF) (or the latch circuit (L
A)) is composed of FFs (or LAs) with a scan function, each FF (or LA) is connected to a shift register, external test data is scanned in from the pad, and internal FF (or LA) data is transmitted from the pad. Be able to scan out. Examples of the configuration of the FF with a scan function include a Mux scan FF, a two-phase clock scan FF, and a two-port scan FF.

FIG. 2 shows a test circuit configuration showing a conventional example. The logic circuit includes combinational circuits 30 and 31 and FF circuits 34-1 @ 34-k, 35-1 @ 35-m, 36-1
$ 36-n. In this conventional example, a two-port scan FF is used as the scan FF, but other scan FFs described above can also be used. Scan FF
Are the terminal CK, the data input terminal D, and the data output terminal Q of the system clock signal 33 in the normal mode.
Terminal SC of scan clock signal 32 in test mode
K, a terminal SI for a scan input data signal 37, and a terminal SO for a scan-out data signal 38.
As described above, the shift register is configured by connecting the FFs of the internal circuit in series, an input signal is supplied to the integrated circuit through the shift register, the integrated circuit is operated, and the result is taken out to the outside by the shift register. is there.

[0007] Also, in the patent gazette (a method of designing a semiconductor integrated circuit and its test pattern: Japanese Patent Laid-Open No. 6-82529),
In addition to the above-described split test method, a scan FF is inserted in the connection path between each logical module to enable detection of a combinational circuit (not sandwiched between FF groups) directly connected to an input / output terminal in the module, thereby causing a failure. It increases the detection rate and improves the reliability of the test. In this case, it is necessary to determine whether or not the scan FF should be interposed and arranged between the module boundary connection paths based on a logical net. The logical net of the logical module does not include the scan FF and does not include the scan FF. However, there is a problem that the wiring delay increases, the fluctuation from the module design delay is large, and the design accuracy is lowered. In addition, since the scan FFs are arranged at the boundary between modules, it is necessary to individually scan in and out individual modules for testing, and there is a problem that the number of test steps increases. Further, the necessity of setting test patterns in all FFs also increases the number of test steps. In such a scheme,
Since it is assumed that all FFs in the integrated circuit are replaced with FFs with a scan circuit, there is a problem that the gate size and the scan wiring area increase, and the chip size increases.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention can reduce the gate size of the scan circuit, the wiring area for the scan circuit, and the number of test patterns and test design steps. It is an object of the present invention to provide a test facilitation circuit system that can perform the test.

[0009]

According to the present invention, as a first means, a plurality of logic modules in an integrated circuit are provided.
A scan flip-flop circuit (FF) or a latch circuit (LA) is provided for each input terminal, output terminal, and input / output terminal of the logic module, and terminals are provided via the flip-flop circuit or the latch circuit. Each of the logic modules includes a shift scan circuit in which the flip-flop circuit or the latch circuit is connected in a chain (series) in the test mode. The test of the entire integrated circuit is performed by connecting the shift scan circuits or latch circuits of at least two or more of the logic modules in a chain and performing a shift scan of the entire chip. Since all FFs (LAs) in the integrated circuit do not necessarily need to be replaced with FFs (LAs) with a scan, logical overhead due to the scan circuit is reduced. Further, the test pattern designed at the time of module development can be used as it is as a scan FF (LA) setting (scan-in) test pattern, so that the number of test design steps is reduced. That is, there is a feature that the design property (IP) can be effectively used.

The second means includes, in addition to the first means, a shift scan flip-flop circuit provided in the wiring area between the logic modules, wherein the flip-flop circuit for the logic module is provided in the wiring area between the logic modules. The chain-like connection is configured by a plurality of lower wiring layers, and the wiring in the normal user mode on the inter-logic module wiring area in which the FF (LA) is embedded is configured by an upper wiring layer. With this configuration, the wiring area between logic modules can be used as a wiring area in the normal user mode, so that an increase in area due to the addition of a scan circuit can be reduced. Of course, the FF (L
It is clear that the wiring layer can be formed by using the entire wiring layer in the region where A) is not embedded.

A third means is that in the first or second means, the flip-flop circuit or the latch circuit in the normal mode has at least a normal terminal active in the normal mode and a scan-in / scan-out operation in the test mode. Is a means for making a scan control terminal and a scan data terminal that are to be active.

[0012]

FIG. 1 is a circuit block diagram showing a basic configuration of a module with a scan circuit according to the present invention. In the following drawings, the same components as those described above or components having the same functions are denoted by the same reference numerals. In FIG. 1, a module 9 with a scan circuit includes a module 10 composed of a logical or memory circuit and a scan FF 11.
-1 to 11-j. Scan FF 11-1
11-j are a scan-in signal terminal SI and a scan-out signal terminal SO for scanning in addition to the data input terminal D and data output terminal Q for normal (normal mode).
(The other terminals, the clock terminal, the scan clock terminal, and the test mode terminal are not shown for convenience of explanation). The scan FFs 11-1 to 11-j are connected to the signal line 1
4 and 15 connected in series with each other,
A shift scan circuit (scan shift register circuit) is formed between the scan-in terminal 12 and the module scan-out terminal 13.

In the test mode, the shift scan circuit becomes effective and performs scan-in and scan-out operations.
In the normal mode, the module output signal 16 is taken out as the output signal of the module 9 with the scan circuit through the Q output signal 17 of the scan FF 11-2, and the input signal 19 of the module 9 with the scan circuit is the Q signal of the scan FF 11-1. Module 10 through output signal 18
Is input to In this case, scan FFs 11-1 and 11
-2 input / output data is in a through state, and scan F
F does not affect the logical operation in the normal mode at all.

In this basic configuration, there is no particular restriction on the input / output terminal arrangement order, and the input terminals and the output terminals may be grouped. In this case, there is a feature that a test pattern can be easily set in the shift scan circuit.

FIG. 3 is a circuit block diagram showing a detailed configuration of the module 9 with a scan circuit according to the present invention. The module 9 with a scan circuit includes a module 10, scan FFs 11-1 to 11-m for input terminals, and scan FFs 11- (m + 1) to 11-j for output terminals.
Since the basic configuration is the same as the configuration in FIG. 1, only the features unique to this embodiment will be described here. It should be noted that the scan FF does not impair the spirit of the present invention even if it is replaced with the scan LA.
Will be described.

The scan latch circuit (LA) is shown in FIG.
The circuit shown in FIG. The scan LAs 11-1 to 11-j in FIG.
It comprises a selector circuit 21 and a NAND gate 22. The selector circuit 21 is composed of, for example, an AND or gate. In addition to the normal mode signal terminals, scan (test) signal terminals include a select terminal SEL, a test mode terminal TE, a scan-in terminal SI, a scan-out terminal (can also be used as a data output terminal Q) SO, and a scan clock terminal SCK. Is provided. In this scan LA, when the test mode signal TE = "1", the SCK terminal signal becomes active, and when TE = "0", the terminal CK input is fixed at "1". Become. Further, the normal data D and the scan-in data SI terminal signal can be independently selected by the SEL terminal signal.

When the flip-flop circuit (FF) is used, the configuration of the FF circuit is shown in FIG. The FF circuits 11-1 to 11-j include a level latch circuit 20-
1, 20-2 and an inverter 23. The level latch circuits 20-1 and 20-2 are equivalent to the scan LAs 11-1 to 11-j in FIG. Book FF
Operates as an edge clock type FF by two level latch circuits, but the scan control operation is the same as that in the case of scan LA, so description thereof will be omitted. In the following, a case where a scan FF is used will be described for convenience. However, it is clear from the following description that the present invention can be applied without impairing the effectiveness of the present invention even when a scan LA is used.

The operation of the module with scan circuit 9 will be described with reference to an operation time chart of FIG. In the scan mode, the test mode signal 53 is set to "1". Scan-in terminal 1 by shift scan operation
2 scan input test patterns from scan FFs 11-1 to 11-1
1-m is set (scan-in operation). Thereafter, the select signal 54 is set to “1” for at least one clock period,
The output signal of the module 10 is scanned by the scan FF 11- (m
+1) to 11-j at the rising edge timing of the scan clock SCK. Select signal 54
Is returned to "0", a shift scan operation is performed, and scan-out data is output from the scan-out terminal 13. In the present embodiment, nothing is limited to the latch circuit and the flip-flop circuit shown in FIGS. 4A and 4B, and other circuit configurations may be appropriately adopted without impairing the spirit of the present invention. Can also.

(Embodiment 1) FIG. 6 shows an embodiment according to the present invention and is a plan view of an LSI. 40 is an LSI chip, 41 is a CPU module, 42 is a DRA
M (memory) module, 43 is an IP module, 44
Is a custom user circuit module, 45 is an external pad for scan-in, and 46 is an external pad for scan-out. Each logic module is a logic module with a scan circuit having the configuration shown in FIGS. 1 and 3, and is connected in a chain via a scan-in terminal 12 and a scan-out terminal 13. The test mode signal, scan clock signal, or select signal can be used also as a dedicated pad or a normal pad (not shown). In this embodiment, since the shift scan circuit is built in the logic module in advance, there is a feature that the test design property of the logic module can be used.

(Embodiment 2) FIG. 7 shows a second embodiment according to the present invention. The difference from FIG. 6 is that the scan FF (LA) and the scan wiring are arranged in the wiring area between the logic modules adjacent to the periphery of the logic module. Therefore, only the configuration and operation different from the embodiment shown in FIG. 6 will be described. The logic modules 41a, 42a,
Reference numerals 43a and 44a denote ordinary logic, memory, IP, and user circuit modules that do not include a shift scan circuit. The scan-in and scan-out operations are the same as in the previous embodiment, and a description thereof will be omitted.

The logic module is arranged in a logic module peripheral area 52 in the inter-logic module wiring area 51,
Wiring of scan FF circuits and scan signals using embedded and lower arbitrary wiring layers enables wiring for normal circuits using the upper wiring layer on the inter-module wiring area, thus reducing area overhead due to test circuits. can do.

In the present invention, it is not necessary that all the modules in the chip be modules with a scan circuit. Even if the present invention is applied to a specific IP module (for example, a module newly introduced from the outside), its effects can be sufficiently exhibited. Is clear from the above description of the embodiment. Further, the configuration of the scan FF is not limited to a configuration having a superior function, but includes a Mux type FF, a two-phase clock type FF,
Alternatively, it is clear that the object of the present invention can be achieved even if it is constituted by a level-sensitive latch circuit.

[0023]

As described above, according to the present invention, a scan shift register is constructed by inserting a scan FF into its input / output terminal for each module (or functional unit). Since the scan circuit is embedded in the inter-wiring region, the product overhead due to the scan circuit can be reduced. Further, the test design property of the module can be inherited, the number of test pattern steps can be reduced, and the number of test steps and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of a module with a scan circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a conventional example.

FIG. 3 is a circuit block diagram showing a detailed configuration of a module with a module circuit according to the present invention.

FIGS. 4A and 4B are a latch circuit diagram and a flip-flop circuit diagram for supplementarily explaining FIG. 3;

FIG. 5 is a time chart for explaining a test operation of the module of FIG. 3;

FIG. 6 is a block diagram showing a first embodiment of the present invention.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

[Description of Signs] 9: Module with scan circuit, 10: Module,
11-1 to 11-j: scan latch circuit or scan flip-flop circuit, 12: module scan-in terminal, 13: module scan-out terminal, 20, 20-1, 20-2 ... level latch circuit,
21 selector circuit, 22 NAND gate, 23 inverter, 40 LSI chip, 41, 41a CPU
Module, 42, 42a ... DRAM (memory) module, 43, 43a ... IP module, 44, 44a ...
User circuit module, 45: external pad for scan-in, 46: external pad for scan-out.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA01 AA04 AC03 AC10 AG07 AH04 AK01 AK11 AK14 AK15 5B048 AA20 CC20 DD05 FF01 5F038 BE05 CA05 DF05 DF14 DT02 DT04 DT06 EZ20

Claims (3)

[Claims] In a semiconductor integrated circuit device comprising a plurality of logic modules, each of the logic modules is provided with a scanning flip-flop circuit or a latch circuit for each input terminal, output terminal, and input / output terminal of the logic module.
A shift scan circuit in which the flip-flop circuits or latch circuits are connected in a chain in the test mode, and the shift scan circuit of at least any of the logic modules is connected in a chain to perform a shift scan of the entire chip. A semiconductor integrated circuit device. 2. The shift scanning flip-flop circuit or latch circuit according to claim 1, wherein the flip-flop circuit or the latch circuit is arranged in a wiring area between the logic modules, and the chain connection of the flip-flop circuit or the latch circuit is formed by a plurality of lower wiring layers. A semiconductor integrated circuit device, wherein a normal user-mode wiring is configured by an upper wiring layer on the wiring area between logic modules. 3. The flip-flop circuit or the latch circuit according to claim 1, wherein at least a normal terminal is active in a normal mode, and a scan control terminal for controlling scan-in and scan-out operations in a test mode. A semiconductor integrated circuit device having a terminal activated.