KR100271259B1 - Semiconductor integrated circuit and its evaluating method - Google Patents

Abstract

The semiconductor integrated circuit is a combination formed of a plurality of passes including a plurality of logic gates and disposed between a flip-flop (F / F) group (1, 2) and a F / F group (1, 2) formed of a plurality of flip-flops. And a functional circuit composed of a circuit (3), a dual input logic gate (5), an output buffer (6), and an input buffer (7). The combination circuit 3 has a plurality of paths extending from the output side of the F / F group 1 to the input side of the F / F group 2. However, only the critical path 20 with the longest delay is shown. For the plurality of logic gates included in the critical path 20, only the initial stage logic gate 4 is shown and all logic gates subsequently connected in series are omitted. Thereby, a semiconductor integrated circuit and its evaluation method for performing AC testing easily and inexpensively are provided without increasing the chip size.

Description

Semiconductor integrated circuits and evaluation methods therefor {SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS EVALUATING METHOD}

The present invention relates to a semiconductor integrated circuit and an evaluation method thereof.

In general, in evaluation tests performed to measure the delay time of the critical path of a semiconductor integrated circuit, mainly DC and AC tests have been used. In recent years, as the high performance and high integration of semiconductor integrated circuits and their size have increased, the price of semiconductor integrated circuits has increased. Thus, AC test selection is particularly needed for the inspection of single semiconductor integrated circuits.

On the other hand, many facilities and processes are required to perform an AC test similar to the AC test for a device of a single semiconductor integrated circuit. For this reason, the balance with the AC test selection for inspection of a single semiconductor integrated circuit is one of the problems to be solved.

Taking one example (former example 1) performed so far, in a conventional semiconductor integrated circuit, in particular in a logic LSI, automatic placement and wiring is performed as a netlist of desired functions as inputs, whereby problems are found in the delay analysis results. If not, the process enters the wafer stage and then proceeds to the inspection stage.

During the AC test on the sample to be measured, the test pattern used for the functional test is usually made, and the operation of the desired frequency is tested for the desired evaluation function by the LSI tester or the like.

If another example (previous example 2) is selected, the ring oscillator is pre-installed in the semiconductor integrated circuit separately from the original functional circuit, and the frequency counter is used to measure the frequency of the ring oscillator, thereby replacing the AC test for the original functional circuit. Use this for Referring to FIG. 12, which is a conceptual diagram showing a substrate arrangement example of a semiconductor integrated circuit in this conventional example, a ring oscillator 29 corresponding to a functional circuit included in the semiconductor integrated circuit 27 is disposed, and the ring oscillator 29 is provided. Corresponding signal pulling-out pads 30, 31 are provided. The contents of specific examples corresponding to this prior art example 2 are disclosed in JP-A-160377 / 1992.

As another conventional example (prior example 3), a method of measuring and evaluating a delay time of a part of a functional circuit has been used in place of an AC test for a functional circuit in a semiconductor integrated circuit. This method is described with reference to FIG. 13 which is a conceptual diagram of such a semiconductor integrated circuit. In the evaluation method shown in FIG. 13, the delay time T1 in the bus 36 passing through the circuit 34 to be measured in the functional circuit 33 included in the semiconductor integrated circuit 13, and the circuit to be measured ( The delay time T2 on the bus 37 not passing through 34 is measured, and with reference to the measured time difference T1-T2 between the two, the delay time in the measuring circuit is evaluated.

However, the above-mentioned semiconductor integrated circuits of the prior art examples 1 to 3 have disadvantages to be described below.

In the case of the prior art example 1, in the evaluation method, it is generally difficult to make a test pattern corresponding to the original functional test in a semiconductor integrated circuit, and a measuring device such as an LSI tester used for this purpose is very expensive.

In the case of the prior art example 2, since the built-in ring oscillator is very small compared with the original functional circuit, when the characteristics of the various transistors disposed in the semiconductor chip are very uneven, it is correlated with the AC test characteristics of the functional circuit. It's hard to get a relationship. As a result, the test function used in place of the AC test on the function circuit is lost.

Also, in the case of the conventional example 3, if the number of circuits measured in the semiconductor integrated circuit is as small as in the case of the conventional example 2, it is difficult to obtain a correlation between the measured result of the measured circuit and the AC test characteristics of the whole functional circuit. it's difficult. If there are multiple measured circuits, the overhead of the additional test circuit is large and the size of the semiconductor chip is increased.

An object of the present invention is to solve the above problem.

Another object of the present invention is to provide a semiconductor integrated circuit comprising a ring oscillator including a critical path by alternately connecting a plurality of input logic gates for designated testing to an initial stage of the critical path, and the frequency of the oscillation output of such a ring oscillator. It is to provide an evaluation method capable of performing the evaluation by measuring.

An object of the present invention is a combination circuit having a plurality of paths, which is constituted by serial connection of several logic gates, and an output terminal of a critical path having the longest delay time is connected to one input terminal, and evaluation testing is performed on another input terminal of the combination circuit. A dual input logic gate into which a specific level signal is input, a plurality of input logic gates arranged in place of a logic gate arranged at an initial stage of a critical path, and having an output terminal of a dual input logic gate connected to one input terminal, and a functional evaluation Is achieved by a semiconductor integrated circuit having a ring oscillator comprised of a critical path including a plurality of input logic gates and a dual input logic gate.

It is also an object of the present invention to provide a first step of using a netlist of a desired function as an input, a second step of performing automatic placement and wiring on a chip of a semiconductor integrated circuit after receiving the netlist input of the first step, A third step of performing a delay analysis for all the plurality of passes in the combined circuit included in the functional circuit of the semiconductor integrated circuit; based on the result of the delayed analysis, the criticality having the longest delay time among the plurality of passes located in the combined circuit A fourth step of extracting a path, a fifth step of connecting a plurality of designated input logic gates for testing by replacing a logical gate of an initial stage of the critical path by configuring a ring oscillator including the critical path, and a ring oscillator Set the oscillation mode and measure the frequency of the oscillation output with a frequency counter. And a functional evaluation method used during AC testing and design of a semiconductor integrated circuit, comprising a sixth step of performing.

The critical path is extracted through delay analysis based on automatic placement and wiring information, and the ring oscillator including the critical path is configured by alternately connecting a plurality of designated input logic gates to the initial stage of the critical path for testing. Since the frequency of the oscillating output of this ring oscillator is measured and its delay time is evaluated, the present invention is very easy and effective for performing low cost AC testing.

Further, the present invention is effective in obtaining the same evaluation condition as the evaluation condition for operating the functional circuit by the actual frequency, because the overhead of the testing circuit is reduced and the AC test aims at the critical pass.

When referring to the following detailed description and drawings, the above and other objects, features, and advantages of the present invention will become more apparent.

1 illustrates an embodiment of the present invention.

Fig. 2 is a block diagram showing the circuit structure for evaluation testing of the first embodiment.

3 is a block diagram showing a designated circuit structure of the first embodiment;

Fig. 4 is a block diagram showing a designated circuit structure for evaluation testing of the first embodiment.

5 is a block diagram showing a second embodiment of the present invention;

Fig. 6 is a block diagram showing a circuit structure for evaluation testing of the second embodiment.

Fig. 7 is a block diagram showing the designated circuit structure of the second embodiment.

Fig. 8 is a block diagram showing a designated circuit structure for evaluation testing of the second embodiment.

Fig. 9 is a block diagram showing a designated circuit structure for evaluation testing of the third embodiment.

Fig. 10 is a block diagram showing a designated circuit structure for evaluation testing of the fourth embodiment.

11 is a flowchart showing the process of the evaluation method of the present invention.

12 shows a prior art.

13 shows another prior art.

Explanation of symbols on the main parts of the drawings

1, 2: F / F group 3: Combination circuit

5, 13 dual input logic gate 6, 7 output buffer

9, 11, 17, 18: dual input NAND gates 10, 14, 16, 61: inverter

12: initial stage logic gate 15: a plurality of input logic gate

20: Critical Pass 50, 52, 62: NOR Gate

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a conceptual configuration diagram of a semiconductor integrated circuit of the first embodiment.

Referring to FIG. 1, a functional circuit includes a plurality of logic gates, which are disposed between flip-flop groups (hereinafter referred to as F / F groups) (1, 2) and F / F groups (1, 2). Combination circuit (3), dual input logic gate (5), and output buffer (7) composed of paths.

In the combination circuit 3, a plurality of passes are provided which extend from the output side of the F / F group 1 to the input side of the F / F group 2 and include various logic gates. However, in Fig. 1, only the critical path 20 having the longest delay time is shown, and the other paths are omitted for the purpose of explanation. For the plurality of logic gates included in the critical path 20, only the initial stage logic gate 4 is shown, and all of the various logic gates connected in series thereafter are omitted.

In the first embodiment, when performing evaluation during design or AC testing, as shown in FIG. 2, the initial stage logic gate 4 of the critical path of the combination circuit 3 is removed and a plurality of inputs are instead. The logic gate 8 is arranged and connected. The original signal line from the F / F 1 is connected to one input terminal of the plurality of input logic gates 8. Point A on the output side of the dual input logic gate 5 shown in FIG. 1 is connected to the other input terminal. In particular, instead of the logic gate 4, a plurality of input logic gates 8 are added to the critical path 20 as test circuits, and the feedback loop circuit includes a criterion including the plurality of input logic gates 8. It is composed of a tick path 20 and a dual input logic gate 5.

In this case, the conditions for defining the dual input logic gate 5 and the plurality of input logic gates 8 are as follows.

(1) a critical path 20 including a plurality of input logic gates 8 when the evaluation specifying signal Tin is input to the dual input logic gate 5 through the input buffer 7 at a specific logic level, and The feedback loop circuit composed of the double input logic gate 5 should be configured as a ring oscillator.

(2) When the evaluation specifying signal Tin is input to the double input logic gate 5 through the input buffer 7 at a logic level opposite to the specific logic level, corresponding to the input signal of the F / F 1, The output level of the critical path 20 including the plurality of input logic gates 8 should be the output level of the critical path 20 including the logic gate shown in FIG. 1, which is the same as the original mode. Corresponds to the input signal of F / F (1).

The double input logic gate 5 and the plurality of input logic gates 8 are determined to satisfy the above-described conditions. When the evaluation is performed during design or AC testing, the testing circuit, as described above, is subjected to the initial stage logic gate 4 of the critical path 20 of the combination circuit 3 shown in FIG. 1 under the above conditions. It is configured by defining a dual input logic gate 4 and a plurality of input logic gates 8 on the basis. Thereafter, by maintaining the evaluation designation signal Tin at the specific logic level described above, the feedback loop circuit composed of the double input logic gate 5 and the critical path 20 is used as the ring oscillator. Thereafter, the frequency of the evaluation output signal output from the dual input logic gate 5 and output to the outside through the output buffer 6 by oscillation is measured using an external frequency counter, thereby evaluating the semiconductor integrated circuit. AC testing for is performed.

Further, by setting the evaluation designation signal Tin to a logic level opposite to the above-described specific logic level, the feedback loop circuit is released from its function as a ring oscillator, and the combination circuit 3 functions as the original combination circuit shown in FIG. Return to.

FIG. 3 is a block diagram showing a designation circuit corresponding to the first embodiment shown in FIG. Referring to FIG. 3, the logic gate 4 of FIG. 1 is composed of an inverter 10, and the dual input logic gate 5 is composed of a dual input NAND gate 9. As shown in FIG.

When the evaluation of the designation circuit shown in FIG. 3 is performed during design and AC testing, as shown in FIG. 4, the initial stage inverter 10 included in the critical path 20 of the combination circuit 3 is The original signal line from the F / F 1 is connected to the input terminal of the NAND gate 11, replaced by the dual input NAND gate 11, and the point on the output side of the dual input NAND gate 9 shown in FIG. B is connected to another input terminal, whereby a test evaluation circuit is formed.

The feedback loop circuit composed of the NAND gate 9 and the critical path 20 including the NAND gate 11 transfers the evaluation designation signal Tin of " H " level to the NAND gate 9 in this condition through the input buffer. By input, it consists of a ring oscillator. The oscillation output of the ring oscillator from the output buffer 6 is externally output as the evaluation output signal Tout. Therefore, by measuring the frequency of the evaluation output signal Tout using the frequency counter, AC testing for evaluation of the semiconductor integrated circuit can be performed.

By bringing the evaluation designation signal Tin to the "L" level, the feedback loop circuit is released from its function as a ring oscillator and the combination circuit 3 returns to the original circuit function.

Next, a second embodiment of the present invention will be described.

5 is a conceptual configuration diagram of the second embodiment. Referring to FIG. 5, the functional circuit is disposed between a flip-flop group (hereinafter, referred to as an F / F group) (1, 2) and a F / F group (1, 2) composed of a plurality of flip-flops, and a logic gate. And a combination circuit (3), a dual input logic gate (13), an inverter (14), an output buffer (6), and an input buffer (7).

In the combination circuit 3, as in the case of the first embodiment, a plurality of paths are provided which extend from the output side of the F / F group 1 to the input side of the F / F group 2 and include several logic gates. . However, only the critical path 20 having the longest delay time among them is shown in FIG. 5, and other passes are omitted for the purpose of explanation. For the plurality of logic gates included in the critical path, only the initial stage logic gate 12 is shown, and all other logic gates subsequently connected in series are omitted.

As is apparent from the comparison with FIG. 1, in the second embodiment, a new inverter 14 is added to the output end of the critical path 20, and the output side of the inverter 14 is connected to one of the dual input logic gates 13. It is connected to the input terminal.

In the second embodiment, as shown in FIG. 6, when evaluation is performed during design or AC testing, the initial stage logic gate 12 of the critical path 20 of the combination circuit 3 is removed, instead. A plurality of input logic gates 15 are arranged in and connected thereto. The original signal line from the F / F 1 is connected to one input terminal of the plurality of input logic gates 15, and the point B on the output side of the dual input logic gate 13 shown in Fig. 5 is connected to the other input terminal. .

That is, a plurality of input logic gates 15 are added to the critical path 20 instead of the logic gate 12 as a testing circuit, and the feedback loop circuit includes a critical path including the plurality of input logic gates 15. 20, the dual input logic gate 13, and the inverter 14 are configured.

In this case, the conditions for defining the dual input logic gate 13 and the plurality of input logic gates 15 are as follows.

(1) When the evaluation specifying signal Tin is input to the dual input logic gate 13 through the input buffer 7 at a specific logic level, the feedback composed of the double input logic gate 13 and the plurality of input logic gates 15. The loop circuit should be configured as a ring oscillator.

(2) When the evaluation specifying signal Tin is input to the double input logic gate 13 through the input buffer 7 at a logic level opposite to the above-described specific logic level, it corresponds to the input signal of the F / F 1; The output level of the critical path including the plurality of input logic gates 15 should be the output level of the critical path 20 including the logic gate 12, which is the same as the original mode shown in FIG. This corresponds to the input signal of F / F 1.

The dual input logic gate 13 and the plurality of input logic gates 15 are determined to satisfy the above condition.

Corresponding to the initial stage logic gate 12 of the critical path 20 of the combination circuit 3 shown in FIG. 5, as described above and as shown in FIG. 6, the evaluation is performed during design or AC testing. When, under the above conditions, the dual input logic gate 13 and the plurality of input logic gates 15 are defined, thereby constructing a testing circuit. Thereafter, the evaluation designation signal Tin is brought to the above-described specific level, whereby a feedback loop composed of the critical path 20 including the dual input logic gate 13, the inverter 4, and the plurality of input logic gates 15. The circuit is used as a ring oscillator. Then, using a frequency counter, AC testing for evaluating the semiconductor integrated circuit is performed by measuring the frequency of the evaluation output signal Tout output from the dual input logic gate and output to the outside through the output buffer 6 by oscillation. do.

Further, by bringing the evaluation designation signal Tin to a logic level opposite to the above-described specific logic level, the feedback loop circuit is released from its function as a ring oscillator and the combination circuit 3 returns to the original combination circuit function shown in FIG. Is returned.

FIG. 7 is a block diagram showing a designation circuit corresponding to the second embodiment shown in FIG. Referring to FIG. 7, the logic gate 12 of FIG. 5 is composed of an inverter 16, and the input logic gate 13 is composed of a dual input NAND gate 17. As shown in FIG.

As shown in FIG. 8, during the design or AC testing, when an evaluation is performed on the circuit of FIG. 7, the initial stage inverter 16 included in the critical path 20 of the combination circuit 3 is a dual input. Replaced by a NAND gate 18, the original signal line from the F / F 1 is connected to one input terminal of the NAND gate 18, and the point B on the output side of the dual input NAND gate 17 in FIG. It is connected to an input terminal, whereby a testing evaluation circuit is comprised. In this condition, the critical pass 20 including the NAND gate 18, the NAND gate 17, and the inverter by inputting the evaluation designation signal Tin of the "H" level to the NAND gate 17 through the input buffer. The feedback loop circuit composed of (14) becomes a ring oscillator. From the output buffer 6, the oscillation output of the ring oscillator is output externally as the evaluation output signal Tout. Therefore, by measuring the frequency of the evaluation output signal Tout using the frequency counter, AC testing for evaluation of the semiconductor integrated circuit can be performed.

Further, by bringing the evaluation designation signal Tin to the "L" level, the feedback loop circuit is released from its function as a ring oscillator and the combination circuit 3 returns to its original function.

Hereinafter, with reference to the accompanying drawings, a third embodiment of the present invention will be described.

9 is a block diagram showing a circuit group of the semiconductor integrated circuit of the third embodiment.

In the third embodiment, the NOR gate 50 is used in place of the dual input logic gate 5 of the first embodiment, and the inverter 51 is used in place of the initial stage logic gate 4 and replaces the inverter 51. As the NOR gate 52 is used. Other parts of the configuration are the same as those of the first embodiment, and thus description thereof is omitted.

During design or AC testing, when an evaluation is made for the designation circuit shown in FIG. 8, the initial stage inverter 51 included in the critical path 20 of the combination circuit 3 is a dual input NOR gate 52. The original signal line from the F / F 1 is connected to one input terminal of the NOR gate 52, and the point C on the output side of the dual input NOR gate 50 shown in Fig. 9 is connected to the other input terminal. This constitutes a testing evaluation circuit.

The feedback composed of the critical path 20 including the NOR gate 52 and the NOR gate 50 by inputting the evaluation designation signal Tin of the "H" level to the NOR gate 50 under this condition through the input buffer. The loop circuit is configured as a ring oscillator. From the output buffer 6, the oscillation output of the ring oscillator is output externally as the evaluation output signal Tout. Therefore, by measuring the frequency of the evaluation output signal Tout using the frequency counter, AC testing for evaluation of the semiconductor integrated circuit can be performed.

Further, by bringing the evaluation designation signal Tin to the "L" level, the feedback loop circuit is released from its function as a ring oscillator and the combination circuit 3 returns to its original function.

Referring to the accompanying drawings, a fourth embodiment of the present invention will be described below.

Fig. 10 is a block diagram showing a circuit group of the semiconductor integrated circuit of the fourth embodiment.

In the fourth embodiment, the NOR gate 609 is used in place of the dual input logic gate 13 of the second embodiment, the inverter 61 is used in place of the initial stage logic gate 12 and replaces the inverter 61. As the NOR gate 62 is used. Other parts of the configuration are the same as those of the second embodiment, and thus description thereof is omitted. When the evaluation is performed on the particular circuit shown in FIG. 10 during design or AC testing, the initial stage inverter 61 contained in the critical path 20 of the combination circuit 3 is routed to the dual input NOR gate 62. The original signal line from the F / F 1 is connected to one input terminal of the NOR gate 62, and the point D on the output side of the dual input NOR gate 60 of Fig. 10 is connected to the other input terminal, This constitutes a testing evaluation circuit.

In this condition, the critical path 20 including the NOR gate 62, the NOR gate 60, and the inverter are input by inputting the evaluation designation signal Tin having the "H" level to the NOR gate 60 through the input buffer. The feedback loop circuit composed of 14 is configured as a ring oscillator. From the output buffer 6, the oscillation output of the ring oscillator is output externally as the evaluation output signal Tout. Therefore, by measuring the frequency of the evaluation output signal Tout using the frequency counter, AC testing for evaluation of the semiconductor integrated circuit can be performed.

Further, by bringing the evaluation designation signal Tin to the "L" level, the feedback loop circuit is released from its function as a ring oscillator and the combination circuit 3 returns to its original function. Operations for the first and second embodiments have been described including their specific modes. Also, as described above, when the ring oscillator is configured during design or evaluation testing, the initial stage inverter of the critical pass is replaced with a NAND gate or a NOR gate. However, by configuring the input side F / F as a scan register, the input can be freely set to the "H" level or "L" level through the scan pass during AC testing of the functional evaluation, so that the NAND gate or NOR The gate may be predetermined with any one of the logic gates.

Next, the procedure of the evaluation method of the semiconductor integrated circuit of this invention is demonstrated. 11 is a flowchart showing an evaluation procedure during design or AC testing in the first or second embodiment. First, using the net list of the desired function as an input (step 21), automatic placement and wiring is performed (step 22).

Thereafter, delay analysis is performed for all the plurality of passes including various logic gates constituting a combination circuit disposed between the F / F group on the input side and the F / F group on the output side (step 23).

Thereafter, a critical path having the longest delay among the plurality of passes located inside the combination circuit is typically extracted by an automatic program (step 24), and the specific plurality of input logic gates are initially stage logic gates of the critical path. Is connected in place of a ring oscillator, and a ring oscillator including a critical path is configured (step 25).

Finally, by setting the ring oscillator to oscillation mode, the frequency of its oscillation output is measured by a frequency counter and AC testing for evaluation is performed (step 26).

As described above, the critical path is extracted through the delay analysis based on the automatic placement and the wiring information after the wiring, and the ring oscillator including the critical path includes a plurality of designated input logic gates for the initial test of the critical path. The present invention is very effective for performing low-cost AC testing very easily because it is constructed by alternately connecting to a stage, the frequency of the oscillating output of this ring oscillator is measured and its delay time is evaluated.

In addition, the present invention is effective in obtaining the same evaluation condition as the evaluation condition for operating the functional circuit by the actual frequency, because the overhead of the testing circuit is reduced and the AC test aims at the critical pass.

Claims (21)

In a semiconductor integrated circuit, A combination circuit having a plurality of passes, A dual input logic gate having one input terminal connected to an output terminal of a critical path having the longest delay time in the combination circuit and a specific level signal for evaluation test being input to the other input terminal; Disposed at an initial stage of the critical path, the input terminal having a plurality of input logic gates connected to an output terminal of the dual input logic gate, And wherein when a functional evaluation is performed, a ring oscillator is formed by a critical pass including the dual input logic gate and the plurality of input logic gates. The method of claim 1, The dual input logic gate and the plurality of input logic gates include the plurality of input logic gates when the signal having an output level logically inverted from the output level of the specific signal is input to the dual input logic gate. And wherein the input / output level of the medical path is configured to coincide with the input / output level of the originally placed critical path including the logic gate. The method of claim 1, A plurality of flip-flops disposed on an input side and connected to the combination circuit, and And a plurality of flip-flops disposed on an output side and connected to the combination circuit. The method of claim 1, The initial stage logic gate of the critical path is an inverter, and the dual input logic gate and the plurality of input logic gates are respectively dual input NAND gates. The method of claim 1, And the initial stage logic gate of the critical path is an inverter, the dual input logic gate is a dual input NOR gate, and the plurality of input logic gates is a dual input NOR gate. The method of claim 1, And an inverter connected to an output end of the critical path and an input end of the dual input logic gate. The method of claim 1, An input buffer to which the specific level signal is input, and And an output buffer for outputting an oscillation signal of the ring oscillator. Automatic wiring arrangement is performed by inputting the netlist of the built-in function circuit, extracting the critical path having the longest delay time from the combination circuit included in the function circuit, and measuring the delay time of the critical path. In a semiconductor integrated circuit whose function is evaluated, A plurality of flip-flops arranged on the input side, A plurality of flip-flops arranged on the output side, A combination circuit comprising a plurality of paths and formed by connecting several logic gates in series to interconnect the plurality of flip flops on the input side and the plurality of flip flops on the output side, A dual input logic gate having one input terminal connected to the output terminal of the critical path having the longest delay time in the combination circuit, and a specific level signal for evaluation test input to the other input terminal; and A plurality of input logics arranged in place of a logic gate disposed at an initial stage of the critical path when a functional test is performed, wherein an output terminal of the dual input logic gate is connected to one input terminal and operated on behalf of the logic gate; With a gate, And wherein when the functional evaluation is performed, a ring oscillator is formed by the critical path including the dual input logic gate and the plurality of input logic gates. The method of claim 8, The dual input logic circuit and the plurality of input logic circuits include a critical input including the plurality of input logic gates when a signal having an output level logically inverted from the output level of the specific signal is input to the dual input logic gate. And the input / output level of the path is configured to match the input / output level of the intactly disposed critical path including the logic gate. The method of claim 8, And the initial stage logic gate of the critical path is an inverter, and the dual input logic gate and the plurality of input logic gates are respectively dual input NAND gates. The method of claim 8, And the initial stage logic gate of the critical path is an inverter, the dual input logic gate is a dual input NOR gate, and the plurality of input logic gates is a dual input NOR gate. The method of claim 8, An input buffer to which the specific level signal is input, and And an output buffer for outputting an oscillation signal of the ring oscillator. The function is evaluated by performing automatic wiring arrangement with a nest of built-in function circuits, extracting the critical path having the longest delay time from the combination circuit included in the function circuit, and measuring the delay time of the critical path. In a semiconductor integrated circuit, A plurality of flip-flops arranged on the input side, A plurality of flip-flops arranged on the output side, A combination circuit including a plurality of paths and formed by connecting several logic gates in series to interconnect the plurality of flip flops on the input side and the plurality of flip flops on the output side, An inverter connected to an input of an output of a critical path having the longest delay time in the combination circuit; A dual input logic gate to which an output terminal of the inverter is connected to one input terminal and a specific level signal for evaluation test is input to the other input terminal, and A plurality of input logic gates arranged in place of the logic gates arranged in the initial stage of the critical path when the functional evaluation is performed, the output terminals of the dual input logic gates connected to one input terminal, and operated in place of the logic gates; And And when the functional evaluation is performed, a ring oscillator is formed by the critical path including the inverter and the plurality of input logic gates. The method of claim 13, And the initial stage logic gate of the critical path is an inverter, and the dual input logic gate and the plurality of input logic gates are respectively dual input NAND gates. The method of claim 13, And the initial stage logic gate of the critical path is an inverter, the dual input logic gate is a dual input NOR gate, and the plurality of input logic gates is a dual input NOR gate. The method of claim 13, An input buffer to which the specific level signal is input, and And an output buffer for outputting an oscillation signal of the ring oscillator. Automatic wiring arrangement is performed by using the netlist of the built-in function circuit, the critical path having the longest delay time is extracted from the combination circuit included in the function circuit, and the delay time of the critical path is measured. In a semiconductor integrated circuit whose function is evaluated, A plurality of flip-flops arranged on the input side, A plurality of flip-flops arranged on the output side, A combination circuit including a plurality of paths and formed by connecting several logic gates in series to interconnect the plurality of flip flops on the input side and the plurality of flip flops on the output side, Input buffer for inputting a specific level signal for evaluation test, A first NAND gate having an output of a critical path having the longest delay time in the combination circuit connected to one input terminal and an output terminal of the input buffer connected to the other input terminal, An output buffer connected to an output terminal of the NAND gate, and A second NAND disposed in place of the inverter originally placed at the initial stage of the critical path when the functional evaluation is performed, the NAND gate connected to one input terminal, and a plurality of flip-flops on the input side connected to the other input terminal; With a gate, When the functional evaluation is performed, a ring oscillator is formed by the critical pass including the first NAND gate and the second NAND gate, and when the specific level signal is output from the input buffer, the output buffer And an oscillation signal of said ring oscillator is detected from the semiconductor integrated circuit. The method of claim 17, And a first NOR gate and a second NOR gate are disposed in place of the first and second NAND gates. Automatic wiring arrangement is performed by using the netlist of the built-in function circuit, the critical path having the longest delay time is extracted from the combination circuit included in the function circuit, and the delay time of the critical path is measured. In a semiconductor integrated circuit whose function is evaluated, A plurality of flip-flops arranged on the input side, A plurality of flip-flops arranged on the output side, A combination circuit including a plurality of paths and formed by connecting several logic gates in series to interconnect the plurality of flip flops on the input side and the plurality of flip flops on the output side, An inverter connected to one input of an output of a critical path having the longest delay time in the combination circuit, Input buffer for inputting a specific level signal for evaluation test, A first NAND gate connected to one input terminal of the output terminal of the inverter and to another input terminal of the input buffer; When the functional evaluation is performed, it is disposed in place of the inverter originally arranged in the initial stage of the critical path, and an output terminal of the NAND gate is connected to one input terminal, and a plurality of flip-flops on the input side are connected to another input terminal. Having a second NAND gate, When the functional evaluation is performed, a ring oscillator is formed by the critical pass including the first NAND gate and the second NAND gate, and when the specific level signal is output from the input buffer, the output And an oscillation signal of the ring oscillator from a buffer is detected. The method of claim 19, And a first NOR gate and a second NOR gate are disposed in place of the first and second NAND gates. A method of evaluating semiconductor integrated circuits used during design and AC testing, The first step of entering a netlist of desired functions, A second step of receiving the netlist input in the first step and performing automatic placement and wiring on a chip of the semiconductor integrated circuit, A third step of performing delay analysis on all the plurality of passes in the combination circuit included in the functional circuit of the semiconductor integrated circuit, A fourth step of extracting a critical path having the longest delay time among the plurality of passes in the combination circuit based on a result of the delay analysis; A fifth step of arranging and connecting a plurality of specific input logic gates for testing instead of the logic gates in the initial stage of the critical path, and forming a ring oscillator comprising the critical path; and And setting a ring oscillator in an oscillation mode and performing an AC test for evaluation by measuring a frequency of the oscillation output using a frequency counter.

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