JP3182442B2 - Logic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology of a logic integrated circuit and a technology effective when applied to a diagnostic circuit and a layout system in the logic integrated circuit.
The present invention relates to a technology effective for use in the configuration of a bipolar logic LSI composed of (emitter-coupled logic) circuits and data latch means used therein.

[0002]

2. Description of the Related Art In recent years, the number of input / output pins of a logic LSI has increased, and some of them have several hundred pins at most. Thus, in a logic LSI having many input / output pins, it is difficult to diagnose the internal logic circuit. For example, LSI
When performing the testing by the probe test, if the number of input / output terminals is large, the terminal interval becomes narrow, and it is very difficult to make accurate contact of the probe to all the terminals (pads). In particular, CCB (controlled collapse bo)
In an LSI of the (nding) type, it is difficult to contact the probe with all pads. Therefore, as a diagnostic method of a logic LSI, a scan method has been proposed in which flip-flops disposed before and after a combinational logic circuit are connected in series and operated as a shift register, thereby facilitating the diagnosis.

According to the diagnosis of the conventional general scan method, it is easy to test a logic circuit subsequent to a flip-flop, but to check the function of the logic gate from the input circuit to the first flip-flop, It was necessary to separately input a probe to the input terminal and input a test signal. Therefore, the boundary of the input part of the logic LSI
There has also been proposed a method in which a scan flip-flop is provided and the test pattern is held in the flip-flop at the time of diagnosis, thereby eliminating the need for diagnosis using a probe. Further, in a logic LSI having a built-in diagnostic circuit of the boundary scan method, a high-speed and low-power-consumption one has been proposed in which a boundary scan flip-flop is configured by combining an ECL circuit and a CMOS circuit. (IEEE 1990 B
ipolar Circuit and Techno
logy Meeting 6.2 pp128-pp
131).

[0004]

However, in the above-described boundary scan flip-flop, a signal at the ECL level is received and latched by the CMOS flip-flop, and is again converted into a signal at the ECL level in the next-stage logic circuit. Since it is a circuit format that sends a signal to
Between the ECL input unit (series gate) and the CMOS flip-flop and between the CMOS flip-flop and the ECL
A level conversion circuit is required between the output section and the output section. Therefore, there is a problem that a circuit design for adjusting a signal level is troublesome and a signal transmission speed is reduced.

An object of the present invention is to provide a data holding means (flip-flop) with a diagnosis control auxiliary circuit which is easy in circuit design and has a small signal delay in a logic integrated circuit having a diagnosis function. . It is another object of the present invention to provide a circuit integrated circuit having a diagnosis function, which facilitates element layout design and automatic wiring design, and is particularly effective when applied to a gate array. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The outline of a typical invention among the inventions disclosed in the present application is as follows. That is, flip-flops (data holding means) arranged before and after the combinational logic circuit are selected by an externally applied address signal and test data is directly input from the outside, or data held by a specific flip-flop is directly sent to an external terminal. In a logic LSI with a diagnostic function configured to be readable, a latch circuit to which an original system signal is supplied is constituted by a bipolar transistor circuit, and a diagnostic signal is supplied to form a control signal to the latch circuit. Diagnostic auxiliary circuit with latch function is C
In addition to the MOS circuit, the output signals of the latch circuit and the diagnostic auxiliary circuit are output via a bipolar logic gate.

A region including a plurality of bipolar transistor elements and a resistance element for forming the latch circuit, and a plurality of M for forming the diagnostic auxiliary circuit.
A cell in which the region including the OSFET element is arranged is regarded as one cell, the cells are regularly arranged on a semiconductor chip, and wiring within and between the cells is formed by a master slice method to obtain desired logic and logic. A diagnostic circuit is configured.

[0008]

According to the above-mentioned means, the latch circuit to which the system data is supplied in the normal operation mode is constituted by the bipolar transistor circuit, so that the signal delay is small, and since the latch circuit does not operate in the normal operation mode, high speed is not required. Since the diagnostic auxiliary circuit is constituted by a CMOS circuit, power consumption can be reduced. In addition, since the output signals of both circuits are output via the bipolar logic gate, a level conversion circuit is not required, and the circuit design is simplified. In addition, since a region including a plurality of bipolar transistor elements and a resistance element and a region including a plurality of MOSFET elements are formed into cells and arranged regularly, element layout design and automatic wiring design become easy. In addition, a high-speed logic circuit (a flip-flop or a logic gate) can be formed by using a bipolar transistor element and a resistance element.
A diagnostic auxiliary circuit can be formed at an arbitrary portion (flip-flop) using the ET element.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a logic LSI to which the present invention is applied. In the figure, reference numerals 11, 12, and 13 denote combinational logic circuits having predetermined logic, each of which is a sequential circuit having no internal storage capability, and FF11 to FF42.
Are flip-flops for data latches provided between the combinational logic circuits 11, 12, and 13 and at the preceding and subsequent stages. These flip-flops FF11
A diagnostic auxiliary circuit 72 is added to each of the FF42 to FF42.

Further, the flip-flops FF11-FF
Of the F42, FF11 to FF13 are flip-flops which also serve as input circuits, and the input pins 41 and FF13 are synchronized with a diagnostic input clock CKi input from the external terminal 31.
An operation of latching the signals input from 42 and 43 or passing the signals as they are is performed. FF21 and FF
22 and FF31 and FF32 and FF33 are flip-flops for latching transmission signals between the combinational logic circuits 11, 12, and 13, respectively.
The data latch operation is performed by the system clocks CK1 and CK2 input from 33. Further, FF41 and FF42 are flip-flops which also serve as output circuits, and output a diagnostic output clock C inputted from the external terminal 34.
An operation of latching data or passing the data as it is by Ki is performed. Flip-flops FF41 and FF
The output signal at the time of system operation is output pins 51 and 5
2 is output.

On the other hand, each of the flip-flops FF11-FF11
The latch data 42 is output from the diagnostic data output pin 55 to the outside in the diagnostic mode. 10 decodes an address signal given from the external address pins 61 to 65 in the diagnostic mode to form a selection signal SEL for each of the flip-flops FF11 to FF42, and to input pins 67 and 6
A diagnostic control circuit that forms a set / reset signal S / R for the diagnostic auxiliary circuit 72 based on the test data TD and the scan clock CKs input from 8, 69 and distributes a diagnostic mode switching signal TM to each flip-flop. In this embodiment, a CMOS circuit is used.

FIG. 2 shows the flip-flop FF11.
One embodiment of the logical function of FF42 is shown. In the figure, reference numeral 71 denotes a latch circuit for latching system data during normal operation, reference numeral 72 denotes a diagnostic auxiliary circuit, and reference numeral 73 denotes a selection from the diagnostic control circuit 10. A NOR gate for outputting an output signal Q ′ of the latch circuit 71 to the diagnostic data output pin 55 as scan-out data So based on the signal SEL. The latch circuit 71 includes a data terminal D to which system data is input, a set terminal S, a reset terminal R, a clock input terminal C, and a row input fixed terminal for fixing input latch data to a low level prior to system data. LI, a high input fixed terminal H for fixing input latch data to a high level prior to system data
I and output terminals Q and Q '(Q' is an inverted signal of Q).

The diagnostic auxiliary circuit 72 includes a terminal to which a selection signal SEL, a set signal S, a reset signal R, and a mode switching signal TM supplied from the diagnostic control circuit 10 are input, and a latch section LT. The flip-flop is selected by SEL, and the mode switching signal T
When the set signal S or the reset signal R is set to the low level when the diagnostic mode is specified by M, a signal for setting or resetting the latch circuit 71 is formed, and the set state or the reset state is held in the latch unit LT. I do. The held data is used as a signal for fixing the input latch data of the latch circuit 71 to a low level and a signal for fixing the input latch data of the latch circuit 71 to a high level by the NOR gates G1 and G2. It is supplied to the input fixed terminal HI.

In this embodiment, the latch circuit 71 is constituted by a series gate composed of bipolar transistors as shown in FIGS.
2 is constituted by a CMOS logic gate as shown in FIG. 3 to 5, the circuit shown in FIG. 3 is a latch circuit suitable for the input flip-flops FF11 and FF12, and the circuit shown in FIG. 4 is a latch circuit suitable for the flip-flops FF21 to FF33. The circuit shown in FIG. 5 is the output flip-flop F
This is a latch circuit suitable for F41 and FF42. The latch circuits shown in FIGS. 3 to 5 have almost the same configuration.
The difference is that the input latch circuit (FIG. 3) has an input terminal 4
1 (42, 43), and the output latch circuit (FIG. 5) has three inputs and an output transistor Qo having a large driving force is open.
The only difference is that the output terminal 51 (52) is connected to the output terminal 51 (52) in the form of an emitter, and the buffer amplifier 82 of the differential type is provided in the preceding stage.

In the circuits shown in FIGS. 3 to 5, a transistor Q1 receiving an input signal of a system data terminal D, a transistor Q2 receiving an input signal of a row input fixed terminal LI,
A transistor Q3 that receives an input signal of the high-high input fixed terminal HI forms a differential circuit in which the emitters are commonly connected. At the same time, the signals input from the diagnostic auxiliary circuit 72 to the low input fixed terminal LI and the high input fixed terminal HI are input to the system data terminal D while being at the CMOS level (for example, 0 V to -2.5 V). The signal is at the ECL level (for example, -0.8 V to -1.3 V). Therefore, when a high-level signal is input to the low-input fixed terminal LI or the high-input fixed terminal HI at the CMOS level, the transistor Q1 is turned off and Q2 or Q3 is turned on regardless of whether the system data signal is high or low. The signal of the low input fixed terminal LI or the high input fixed terminal HI is taken into the latch circuit 71 prior to the system data. FIG. 6 shows an example using an ECL gate as a circuit configuration example of the NOR gate 73 that outputs the scan-out data So, together with a specific circuit example of the diagnostic auxiliary circuit 72. By using the ECL gate for the output circuit of the scan-out data So, a level conversion circuit becomes unnecessary.

Next, an example of a specific diagnosis method in a logic LSI to which the flip-flop of the above embodiment (FIG. 2) is applied will be described with reference to FIG. FIG. 7 schematically shows three flip-flops taken out of many flip-flops in order to facilitate understanding of the diagnostic system in the present invention.
Here, the outputs of the flip-flops FF1 and FF2 are O
It is configured to be input to the system data terminal D of the flip-flop FF3 via the R gate G10.
The system clock CK1 is supplied to the clock terminal C of the flip-flops FF1 and FF2, and the system clock CK2 is supplied to the clock terminal C of the flip-flop FF3. The configuration of each flip-flop is shown in FIGS.
It is the same as that shown in FIG.

The diagnostic control circuit 10 decodes address signals A0 and A1 supplied from the outside and selects the select signals SEL1, SEL2 and SEL2 of the flip-flops FF1 to FF3.
A decoder DEC composed of three NAND gates forming SEL3, test data TD and scan clock C
Ks and two NAND gates G11, G11, which form a set signal S and a reset signal R for each flip-flop.
G12 and a buffer BFF for distributing the mode switching signal TM to each flip-flop. Also,
The scan-out data So of each of the flip-flops FF1 to FF3 is output to the outside from the diagnostic data output pin 55 via the OR gate G13. The above OR gate G10
And G13, when the last stage of the flip-flops FF1 to FF3 is constituted by an emitter follower,
It can be wired or.

As an example, a description will be given of a method of diagnosing whether the output signal of the flip-flop FF2 rises, that is, whether the signal rises within a predetermined delay time.
In this diagnosis, first, the mode switching signal TM is set to "0".
(Normal operation mode), the address signals A0 and A1 for selecting the flip-flop FF1 are input to the decoder DEC, the test data TD is set to "0", and the scan clock CKs (pulse) is applied. Then, the output of the NOR gate G4 in the diagnostic auxiliary circuit 72 of the flip-flop FF1 changes to high level, the latch circuit 71 in the FF1 is reset, and "0" is held. next,
A similar operation is performed for flip-flops FF2 and FF3.

Then, the mode switching signal TM is set to "1".
(Diagnosis mode), input the address signals A0 and A1 for selecting the flip-flop FF1, set the test data TD to "0", and set the scan clock CKs
(Pulse) to cause the latch circuit LT in the diagnostic auxiliary circuit 72 of the flip-flop FF1 to latch “0”. Further, the mode switching signal TM is set to "1" (diagnosis mode).
Then, address signals A0 and A1 for selecting the flip-flop FF2 are input, the test data TD is set to "1", a scan clock CKs (pulse) is applied, and the latch circuit in the diagnostic auxiliary circuit 72 of the flip-flop FF2 is supplied. Let LT latch "1".

Thereafter, the mode switching signal TM is set to "1" (diagnosis mode), the address signals A0 and A1 for selecting the flip-flop FF3 are input, and the system clock CK1 (pulse) is given. At this time, since “0” is latched in the latch LT in the flip-flop FF1, the state of the row input fixed terminal LI is taken into the latch circuit 71 prior to the system data. Also,
Since “1” is latched in the latch LT in the flip-flop FF2, the state of the high input fixed terminal HI is taken into the latch circuit 71 prior to the system data.

As a result, the output Q of the flip-flop FF2 changes to a high level as shown in FIG. 8 (timing t1). Then, after a predetermined delay time, the output of the NOR gate G10 changes to high level (at timing t).
2). Here, the timing is measured and the system clock C
When K2 (pulse) is given, the latch circuit 71 in the flip-flop FF3 outputs the output Q of the flip-flop FF2.
(High level), the output Q of FF3 changes to High level (timing t3). At this time, if a signal transmission system from the flip-flop FF2 to the flip-flop FF3 has a failure (a delay equal to or longer than a predetermined value), the data "1" is not taken into the flip-flop FF3. On the other hand, the state of the flip-flop FF3 is determined by selecting the flip-flop FF3 by the address signals A0 and A1.
Can be output to the diagnostic data output pin 55 via the interface. Therefore, by monitoring the output pin 55, it is determined that a failure has occurred, that is, the output signal of the flip-flop FF2 does not rise within a predetermined delay time. can do.

Next, an example of a method of diagnosing a logic function in a logic LSI to which the flip-flop (FIG. 2) of the above embodiment is applied will be described with reference to FIG. 7 again. In FIG. 7, the target of diagnosis is flip-flops FF1, F
This is a logical function of the NOR gate G10 between F2 and FF3. In this diagnosis, first, the mode switching signal T
M is set to “0” (normal operation mode), address signals A0 and A1 for selecting the flip-flop FF1 are input to the decoder DEC, and the test data TD is set to “0”.
The scan clock CKs (pulse) is applied, the output of the NOR gate G4 in the diagnostic auxiliary circuit 72 of the flip-flop FF1 is changed to a high level, and the latch circuit 71 in the FF1 is reset to hold “0”. Let it.
Next, the same operation is performed for the flip-flop FF3.

On the other hand, for the flip-flop FF2, the test data TD is set to "1", the mode switching signal TM is set to "0", address signals A0 and A1 for selecting the flip-flop FF2 are input, and the scan clock CKs ( A pulse) is given, and the output of the NOR gate G3 in the diagnostic auxiliary circuit 72 of the flip-flop FF2 is changed to a high level, and the latch circuit 71 in the FF2 is set to a set state to hold “1”.

Next, the system clock CK2 (pulse) is applied to the flip-flop FF3 while the mode switching signal TM is kept at "0" (normal operation mode). Then, the data held in the flip-flop FF2 is taken into the latch circuit 71 of the flip-flop FF3. The data held in the flip-flop FF3 includes the address signals A0, A
By selecting FF3 by 1, it is possible to output to the diagnostic data output pin 55 via the NOR gate 73, and if the data read by monitoring the output pin 55 is “0”, the NOR gate G10 It can be determined that the logic function of the flip-flop (or FF2 or FF3) has a failure.

By applying the above method, the flip-flops FF11-FF1 in the logic LSI of FIG.
3 latches the test data, and then inputs the system clock CK1 to the terminal 32 and fetches the data into the flip-flop FF21 or FF22, so that the logic function of the combinational logic circuit 11 and the flip-flop FF
21, the test data is latched in the FF 22, the system clock CK 2 is input to the terminal 33, and the data is taken in the flip-flop FF 31, FF 32 or FF 33, and the logic function of the combinational logic circuit 12 is further applied to the flip-flops FF 31 to FF 33. By latching the test data and then inputting the diagnostic output clock system clock CKo to the terminal 34 and loading the data into the flip-flop FF41 or FF42, the logic function of the combinational logic circuit 13 can be diagnosed.

Next, a preferred embodiment in a case where the diagnostic system according to the present invention is applied to a gate array will be described. FIG. 9 shows the layout of the entire chip of the gate array. In FIG. 1, reference numeral 100 denotes a semiconductor chip; 110, an input / output unit provided on the periphery of the semiconductor chip 100;
10 indicates that the plurality of input / output circuit cells 111
0 are arranged along the periphery. Each input / output circuit cell 1
Numeral 11 includes a region having an element for forming an input circuit, a region having an element for forming an output circuit, and a bonding pad as an input / output terminal. , An input circuit or an output circuit.

In FIG. 9, reference numeral 200 denotes an internal logic unit. The internal logic unit 200 includes a plurality of basic circuit cells 210 arranged in a matrix. Diagnostic control circuit 10 is arranged. Basic circuit cell 2
As shown in FIG. 10, reference numeral 10 denotes a CMOS area 211 in which a CMOS element capable of forming the above-described diagnostic auxiliary circuit 72 is formed at the center, and a latch circuit 71 and a NOR gate 73 arranged above and below the CMOS area 211 can be formed. The layout of the element is designed to have a rectangular shape as a whole, including bipolar regions 212A and 212B formed with a simple bipolar transistor element and a resistance element.

The basic circuit cell 210 can form any of the flip-flops FF11 to FF42 shown in FIG. 1 or the logic gates forming the combinational logic circuits 11 to 13 by forming wirings by the master slice method. Have been. For example, the basic circuit cell 2 in FIG.
In the case where the flip-flops FF11 to FF42 are configured using the CMOS region 10, as shown in FIG.
The diagnostic auxiliary circuit 72 is formed by using the CMOS element formed in the
A latch circuit 71 and a NOR gate 73 are formed using the bipolar transistor element and the resistance element formed in A and 212B.

On the other hand, when the combinational logic circuits 11 to 13 are constructed using the basic circuit cell 210 of FIG.
As shown in FIG. 2, the CMOS region 211 is an unused region, and a logic gate such as a NOR gate or an OR gate is formed using the bipolar transistor element and the resistance element formed in the bipolar regions 212A and 212B. As described above, by arranging and regularly arranging the region including the bipolar transistor element and the resistor element and the region including the MOSFET element as cells, the layout design and the automatic wiring design of the element are facilitated. A high-speed logic circuit (flip-flop or logic gate) constituting a system can be formed using elements and resistance elements, and a diagnostic auxiliary circuit can be formed at an arbitrary part (flip-flop) using MOSFET elements. Become like

FIG. 13 shows an embodiment of the layout of the elements and wirings of the CMOS region 211 constituting the basic circuit cell 210, and FIG.
One embodiment of the layout of the elements and wirings of the bipolar regions 212A and 212B that are configured is shown. FIG. 14 shows the bipolar regions 212A and 212B.
5 is a layout example when the latch circuit 71 in FIG. 4 is configured using the bipolar transistor element and the resistance element formed in FIG. In FIG. 13, reference numeral 221 denotes a region for forming a P-channel MOSFET, and 222 denotes an N-channel MOSFET.
The ET formation region 223 is a polysilicon gate electrode,
Reference numeral 24 denotes a first-layer metal wiring, and 225 denotes a second-layer metal wiring. Reference characters R ′, TM, and S ′ are input terminals of signals of the same reference numerals shown in FIG. 6, and reference characters R, HI, LI,
S is an output terminal of the signal of the same sign shown in FIG.

In FIG. 14, reference numerals 231 to 244 denote bipolar transistor elements, reference numerals 251 and 252 denote polysilicon resistance elements, reference numeral 261 denotes a first-layer metal wiring, and reference numeral 262 denotes a second-layer metal wiring. Reference numerals C, E, and B denote a collector region, an emitter region, and a base region of the bipolar transistor, respectively. Further, symbols R, HI, LI, S, D, and CK are input terminals of signals of the same code shown in FIG. 4, and symbols Q and Q 'are outputs of signals of the same code shown in FIG. Terminal.

As described above, in the above embodiment, the flip-flops (data holding means) arranged before and after the combinational logic circuit are selected by an externally applied address signal, and test data is directly input from the outside or specified. In a logic LSI with a diagnostic function configured so that data held in the flip-flop can be directly read to an external terminal, a latch circuit to which an original system signal is supplied is constituted by a bipolar transistor circuit and a diagnostic signal is supplied. The diagnostic auxiliary circuit with a latch function for forming a control signal to the latch circuit is constituted by a CMOS circuit, and the output signals of the latch circuit and the diagnostic auxiliary circuit are output via a bipolar logic gate. ,
The flip-flop to which the system data is supplied in the normal operation mode is configured by a bipolar circuit, so that the signal delay is small. In addition, the flip-flop that does not operate in the normal operation mode and does not require high speed is configured by a CMOS circuit. Therefore, power consumption can be reduced. Further, since the output signals of both circuits are output via the ECL gate, there is an effect that a level conversion circuit is not required and circuit design becomes easy.

Also, a region in which a region including a plurality of bipolar transistors and a resistor for forming the flip-flop and a region including a plurality of MOSFETs for forming the diagnostic auxiliary circuit are arranged is one. And a diagnostic control circuit for regularly arranging the cells on a semiconductor chip and for decoding an address signal externally applied in a diagnostic mode to form a signal for the diagnostic auxiliary circuit around the cell array. Since the desired logic and diagnostic circuits are formed by forming wirings in the cells and between the cells by the master slice method, the layout design and automatic wiring design of the elements are facilitated, and furthermore, the bipolar transistor elements are formed. And high-speed logic circuits that configure the system using resistors And forming flops and logic gates) using a MOSFET device there is an effect that it is possible to form the diagnostic auxiliary circuit at any site (flip-flop).

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, the configuration of the basic cell 210 in the embodiment is not limited to that shown in FIG. 10, but one bipolar region and one CMOS
It may be composed only of an area. Also, the shape of the cells is not limited to a rectangle, and may be any shape that does not create a gap when arranged in a regular manner. Further, in the above embodiment, the diagnosis control circuit 10 is designed as a dedicated logic circuit, but may be configured using the basic cell 210.

In the above description, the invention made mainly by the present inventor is based on the ECL which is the field of application which is the background of the invention.
Although the description has been given of the case where the present invention is applied to a logic LSI of the form, the present invention is not limited to this and can be generally used for a bipolar logic LSI.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a logic LSI with a diagnostic function of a random address system in which test data can be input and held data can be output by randomly designating a flip-flop by an address signal, signal delay is reduced and power consumption is reduced. And the circuit design becomes easier.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a logic LSI to which the present invention is applied.

FIG. 2 is a logic configuration diagram showing one embodiment of a flip-flop in a logic LSI to which the present invention is applied.

FIG. 3 is a circuit diagram illustrating an example of a latch circuit forming an input flip-flop;

FIG. 4 is a circuit diagram showing an example of a latch circuit forming a flip-flop between combinational logic circuits;

FIG. 5 is a circuit diagram illustrating an example of a latch circuit forming an output flip-flop;

FIG. 6 is a circuit diagram showing an example of a diagnostic auxiliary circuit forming a flip-flop;

FIG. 7 illustrates a logic LS to which the flip-flop according to the embodiment is applied.
FIG. 3 is a schematic diagram for explaining an example of a specific diagnosis method in I.

FIG. 8 is a timing chart at the time of diagnosis of a rise time of an output signal of a flip-flop.

FIG. 9 is a diagram showing a layout of an entire chip when the present invention is applied to a gate array.

FIG. 10 is a diagram illustrating a configuration example of a basic cell used for a gate array according to an embodiment.

FIG. 11 is an explanatory diagram showing a usage example of a basic cell.

FIG. 12 is an explanatory diagram showing another usage example of the basic cell.

FIG. 13 is a plan view showing an example of a layout of a CMOS region in a basic cell.

FIG. 14 is a plan view showing an example of a layout of a bipolar region in a basic cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Diagnostic control circuit 41, 42, 43 Input pin 51, 52 Output pin 55 Diagnostic data output pin 61-65 Address pin 71 Bipolar latch circuit 72 CMOS diagnostic auxiliary circuit 73 ECL logic gate 100 Semiconductor chip 210 Basic cell 223 Gate electrode 231 to 244 Bipolar transistor

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuo Tanba 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Toru Kobayashi 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Inside the center (72) Kuniaki Kishida 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Noriyuki Sakamoto 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Hitachi Computer Engineering Co., Ltd. (56) References JP-A-62-254460 (JP, A) JP-A-60-66852 (JP, A) JP-A-61-264754 (JP, A) JP-A-62-115765 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (3)

(57) [Claims] 1. A data holding means disposed before and after a combinational logic circuit is selected by an externally applied address signal so that data can be directly input from the outside or held data can be directly read to an external terminal. A latch circuit having a diagnostic function and supplied with a system signal is formed of a bipolar transistor circuit, and a diagnostic auxiliary circuit supplied with a diagnostic signal and forming a control signal to the latch circuit is formed of a CMOS circuit. A logic integrated circuit, comprising: 2. The data holding means comprises the latch circuit and the diagnostic auxiliary circuit, and a signal from the latch circuit and the diagnostic auxiliary circuit is output via a bipolar logic gate. 2. The logic integrated circuit according to claim 1, wherein: (3)Data placed before and after the combinational logic circuit
Data holding means by an externally applied address signal.
Select to enter data directly from the outside, or
A diagnostic function configured to read directly to external terminals
The latch circuit to which the system signal is supplied is
And a diagnostic signal supply
Diagnostic aid for generating a control signal to the latch circuit
The circuit is a logic integrated circuit composed of CMOS circuits.
Method,  A plurality of bipolar transistors for configuring the latch circuit
A region including a transistor element and a resistance element;
Includes multiple MOSFET elements to form auxiliary circuit
A cell in which the area to be
Arrange regularly on the conductor chip and use the master slice method.
By forming wiring inside and between the above cells
To configure the desired logic and diagnostic circuit
Characteristic logic integrated circuitHow to configure.