JP2002050200A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which malfunction can be prevented when a power source is applied. SOLUTION: This device is a logic-containing DRAM/LSI, constituted of a DRAM-MACRO 1, a logic circuit 2 provided at an input side of this DRAM- MACRO 1, a logic circuit 3 provided at an output side of the DRAM-MACRO 1, or the like, flip-flop circuits 4, 5 which latch a signal, have input terminals of a reset signal RESET, and provide a reset function are connected to an input stage and an output stage of the DRAM-MACRO 1, when a power source is applied, an output of a flip-flop circuit 6 of the logic circuit 2 is unstable, even when an input of an unstable level is inputted to the DRAM-MACRO 1, output of the flip-flop circuits of the DRAM-MACRO 1 are fixed by controlling the reset signal RESET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology of a semiconductor device, and more particularly to a technology effective when applied to a semiconductor device suitable as a countermeasure for preventing malfunction at power-on in an LSI such as a logic embedded DRAM.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in an LSI such as a DRAM, a DRA is required to respond to a request for a higher speed from an external device.
Logic embedded DRAM / L with M and logic circuit
SI has been used. This logic embedded DRAM
The speed of the LSI can be improved and the number of bits can be increased as compared with a DRAM / LSI controlled from the outside, so that the data transfer rate can be greatly improved.

It should be noted that such a logic-embedded DRAM.
Examples of the technology relating to LSI include the technology described in “Electronic Materials” P39 to P43 issued by the Industrial Research Council on January 1, 1998.

[0004]

The inventors of the present invention have studied the technology of the DRAM / LSI with embedded logic as described above, and have found the following. For example, a DRAM / LSI with embedded logic is shown in FIG.
As shown in FIG. 5, the DRAM macro 1 includes logic circuits 2 and 3 on the input side and output side, and the input and output stages of the DRAM macro 1 and the logic circuits 2 and 3 have flip-flops. A loop circuit 31 is provided.

[0005] Such a logic-mixed DRAM / LSI
Then, when the power is turned on, as shown in FIGS. 16 and 17,
Until the power supply potential VDD is reached, the output of the flip-flop circuit 31 of the logic circuit 2 is indeterminate.
An undefined level is also input to the AM macro 1, and in such a case, the DRAM macro 1 operates abnormally and may cause a malfunction such as latch-up. In particular,
Since the number of flip-flop circuits is increased due to an increase in the number of bits as compared with a DRAM / LSI, the reset function of the flip-flop circuit may have a large factor.

Therefore, an object of the present invention is to provide a logic embedded D
An object of the present invention is to provide a semiconductor device capable of preventing a malfunction in a RAM / LSI when power is supplied to the LSI.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor device according to the present invention is applied to a semiconductor device in which a logic circuit and a storage circuit are mixed, and a flip-flop with a reset function having a reset signal input terminal at an input stage and an output stage of the storage circuit. A circuit is provided to control the reset signal when the power is turned on to fix the output of the flip-flop circuit with a reset function.

In this configuration, the flip-flop circuit with a reset function has an input / output terminal for diagnostic data and further has a diagnostic function by a scan method.

The reset signal is a signal having a plurality of flip-flop circuits which are supplied from the outside or whose data input terminals are open, and an AND gate circuit which performs an AND operation on outputs of the plurality of flip-flop circuits. A diode and a resistor that are generated as an output signal of a generating circuit or are connected in series between a power supply potential and a ground potential;
This is generated as an output signal of a signal generation circuit having an inverter connected to a connection node between a diode and a resistor.

Therefore, according to the semiconductor device, when the power is turned on, the output of the flip-flop circuit of the logic circuit portion is undefined, and the input to the storage circuit is also input at an undefined level. By using a flip-flop circuit with a reset function and fixing the output of the flip-flop circuit of the memory circuit, abnormal operation at power-on can be prevented.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a schematic layout diagram showing a semiconductor device according to this embodiment, and FIGS. 3 and 4 are schematic layouts showing a reset signal supply system. Figure 5 is a DRAM
6 to 9 are explanatory diagrams showing flip-flop circuits, FIGS. 10 to 12 are explanatory diagrams showing a reset signal generating circuit, and FIGS. 13 and 14 show modified examples of the reset signal generating circuit. FIG.

First, an example of the configuration of the semiconductor device of the present embodiment will be described with reference to FIG. The semiconductor device of the present embodiment is, for example, a logic-mixed DRAM / LSI,
It comprises a DRAM macro 1, a logic circuit 2 provided on the input side of the DRAM macro 1, a logic circuit 3 provided on the output side of the DRAM macro 1, and the like. It is formed on one semiconductor substrate such as crystalline silicon.

The DRAM macro 1 is composed of a storage circuit for storing data, operates in synchronization with, for example, a clock signal, and controls a row address signal, a row address signal and a column address strobe signal based on control of a row address strobe signal and a column address strobe signal.
Data writing / reading operation can be performed on a memory cell selected by a column address signal or the like. The DRAM macro 1 has flip-flop circuits 4, 5 for latching signals at an input stage and an output stage.
Is provided. The flip-flop circuits 4, 5
Has an input terminal for a reset signal RESET, and has a reset function of fixing the output by controlling the reset signal RESET when the power is turned on. Further, the flip-flop circuits 4 and 5 have input / output terminals for diagnostic data, and also have a diagnostic function by a scan method.

The logic circuits 2 and 3 include a DRAM macro 1
, For example, operates in synchronization with a clock signal to generate a row address strobe signal, a column address strobe signal, a row address signal, a column address signal, etc. In addition to the output, the signal output from the DRAM macro 1 can be controlled to be output to the outside. Each of the logic circuits 2 and 3 is provided with a flip-flop circuit 6 for latching a signal at an output stage of the logic circuit 2 on the input side, and a flip-flop circuit 7 for latching a signal at an input stage of the logic circuit 3 on the output side. Is provided.

Logic mixed DR configured as described above
The AM LSI is arranged on a chip as shown in FIG. 2, for example. That is, eight DRAMs, four on each side along the long side direction, on a rectangular chip
A region is provided in which macros (0 to 7) 1 are operably operated independently of each other.
3 is provided. And each DR
A reset signal RESET is distributed to the AM macro 1. This reset signal RESET is supplied externally through an LSI pin 8 as shown in FIG. 3 or generated by a built-in reset signal signal generating circuit 9 as shown in FIG. And so on.

Next, the configuration of the DRAM macro 1 will be described in detail with reference to FIG. The DRAM macro 1 includes a DRAM array 11, a main amplifier 12, a write amplifier 13, a row decoder 14, a column decoder 15, a control circuit 16,
It comprises an FT circuit 17, a Maxell decoder 18, a clock generator 19, a power supply generator 20, a plurality of latch circuits, gate circuits, and the like, as well as a plurality of flip-flop circuits 4 and 5 described above. The flip-flop circuits 4 and 5 include a flip-flop circuit 21 having a latch function and a diagnostic function, a flip-flop circuit 22 having a reset function, and a flip-flop circuit 23 having a test function.

This DRAM macro 1 has a clock signal CLK- necessary for a data write / read operation.
N, row address strobe signal RAS-N, column address strobe signal CAS-N, chip enable signal CE, write enable signal WE, row address signal RASADR, column address signal CASADR, write data WD, reset signal RESET-N, diagnostics , Input signals SID, scan clock signals LSSD-A, LSSD-C, etc., which are necessary for an output signal MUXOUT and scan output data SO.
D or the like is output. In addition, DWMCNT, MUXSE
L, SE, FRCD, CFDS, DGCLK-N, BI
ENB, TDMCK-N, TDMS, CE0TEST,
TDID, LTEN-N, LT, TEMPF, TEMP
Signals such as S are input, and signals such as TMAENT and IJ are output. Further, VSBC, VDBC, V
A power supply such as SBB, VDBB is supplied, and VPP,
Power supplies such as VBB, VPL, and VDDH are output.

Next, a flip-flop circuit 21 having a latch function and a diagnostic function, and a flip-flop circuit 22 having a latch function, a diagnostic function and a reset function will be described in detail with reference to FIGS. 6 is a logic diagram of a flip-flop circuit 21 having a latch function and a diagnostic function, FIG. 7 is a timing chart thereof, FIG. 8 is a circuit diagram of a flip-flop circuit 22 having a latch function, a diagnostic function and a reset function, and FIG. Is an explanatory diagram of the operation mode.

As shown in FIG. 6, a flip-flop circuit 21 having a latch function and a diagnostic function is composed of logic gate circuits L1 and L2, a NAND gate G1, an inverter G2, etc., and has scan input data SID and scan clock signal. LSSD-A, LSSD-C, input data I
N, a clock signal CK is input, and output data OUT,
Scan output data SOD is output. The input terminals D2, C2, D1 and C1 of the logic gate circuit L1 have scan input data SID and scan clock signal LS, respectively.
SD-A, input data IN, scan clock signal LSSD-C via NAND gate G1, clock signal C
K is input, and an output signal is output from the output terminal Q.
The output signals of the logic gate circuit L1 and the clock signal CK are input to the input terminals D1 and C1, respectively, of the logic gate circuit L2, the output data OUT is output from the output terminal Q, and the scan output data SOD is output via the inverter G2. Is output.

As shown in FIG. 7, the flip-flop circuit 21 having the latch function and the diagnostic function first performs a scan clock signal LSS as a scan-in operation (a).
At DA, scan is performed on the logic gate circuit L1, and the scan input data SID is captured. When the scan clock signal LSSD-C = "H", the clock signal C
K strikes only the logic gate circuit L2, and together with data transfer from the logic gate circuit L1 to the logic gate circuit L2,
Data is output from the logic gate circuit L2. Further, as a clock advance operation (b), the clock signal CK
= “L”, the scan clock signal LSSD-C =
At "L", the input data IN is taken into the logic gate circuit L1. Then, as the scan-out operation (c), scan-out is performed in a sequence reverse to that of the scan-in operation.
Thereby, diagnosis can be performed by the scan chain method including the other flip-flop circuits 21 to 23.

As shown in FIG. 8, a flip-flop circuit 22 having a latch function, a diagnostic function, and a reset function is
The flip-flop circuit 21 having the latch function and the diagnostic function shown in FIG.
The configuration is such that a TT is added and a logic gate is added accordingly. In other words, the flip-flop circuit 22 includes the NAs constituting the logic gate circuits L1 and L2.
ND gates G11 and G12 and pass gates G13 to G1
5, a NOR gate G16, a NAND gate G17, inverters G18 to G30, and the like. As shown in FIG. 9, the flip-flop circuit 22 has a reset signal RESETT = “H” and a scan clock signal L
When SSD-A, LSSD-C = “L”, the scan output data SOD = “L”, and the flip-flop circuit 22 can be set to the reset mode. In other normal mode, diagnostic mode, etc., the reset signal R as shown in FIG.
It is set by the input of each signal of ESETT, clock signal CK, input data IN, scan clock signals LSSD-A, LSSD-C, and scan input data SID.

Next, the reset signal generating circuit 9 will be described in detail with reference to FIGS. FIG. 10 is a logic diagram of the reset signal generating circuit 9, FIG. 11 is an explanatory diagram of its truth value, and FIG. 12 is an explanatory diagram of transition of the reset signal potential.

As shown in FIG. 10, the reset signal generation circuit 9 is composed of n flip-flop circuits FF1 to FFn, an n-input AND gate G41 and the like, for example, in the case of n bits. Reset signal RESE
Output as T. Each flip-flop circuit FF1
FFn has an open data input terminal, and each output signal is input to an AND gate G41. Here, the 2-bit and 3-bit output signals are inverted and input. Therefore, in this reset signal generation circuit 9, FIG.
, The input signal to the AND gate G41 is "1, 0, 0, 1,..., 1 bit to n bits in order.
The reset signal RESET becomes "1" only when it is "1", and becomes "0" in the remaining 2 ⁿ -1 cases.

By using the reset signal RESET to control the flip-flop circuits 4 and 5 connected to the input stage and the output stage of the DRAM macro 1, the power supply at the time of power-on as shown in FIG. With respect to the transition of the potential VDD, after the reset period in which the power supply potential VDD reaches the logical threshold voltage of the flip-flop circuits FF1 to FFn, that is, in the normal operation by opening the reset function, the extremely low probability of 1/2 ⁿ , And can be set to “0” with a very high probability of (2 ⁿ −1) / 2 ⁿ . For example, in the case of 5 bits, 1
It becomes "1" only with a probability of / 32, and becomes "0" with a probability of 31/32.

Next, a modified example of the reset signal generating circuit 9 will be described with reference to FIGS. FIG. 13 is a circuit diagram of the reset signal generating circuit 9, and FIG. 14 is an explanatory diagram of transition of the reset signal potential.

As shown in FIG. 13, a reset signal generating circuit 9 includes a diode D51, a resistor R51, and a diode D51 connected in series between a power supply potential VDD and a ground potential.
Inverter G connected to the connection node between
51, and this output signal is a reset signal R
Output as ESET. This reset signal RESE
By controlling the flip-flop circuits 4 and 5 using T, as shown in FIG.
, The power supply potential VDD changes to the diode D5.
After the reset period in which the voltage reaches the sum of the voltage VBE of 1 and the logical threshold voltage of the inverter G51, it does not become "1" but can be set to "0".

Accordingly, the logic-mixed DR of the present embodiment
According to the AM / LSI, the flip-flop circuit 4 with the reset function is provided at the input stage and the output stage of the DRAM macro 1.
When the power supply is turned on, the output of the flip-flop circuit 6 of the logic circuit 2 becomes unstable, and even if the input to the DRAM macro 1 is of an undefined level, the reset function of the flip-flop circuits 4 and 5 allows Since the output can be fixed, abnormal operation at power-on can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, a case has been described in which the present invention is applied to a logic-loaded DRAM / LSI. However, the present invention is not limited to this, and can be applied to all LSIs having a flip-flop circuit. .

[0032]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In the input stage and the output stage of the storage circuit,
By providing a flip-flop circuit with a reset function having a reset signal input terminal, even when the output of the flip-flop circuit of the logic circuit unit becomes undefined at power-on and the input to the storage circuit is also input at an undefined level, Since the output of the flip-flop circuit with the reset function can be fixed by controlling the reset signal, it is possible to prevent an abnormal operation when the power is turned on.

(2) The flip-flop circuit with the reset function has the input / output terminal of the diagnostic data, so that the diagnostic function by the scan method can be realized.

(3) The reset signal can be supplied from the outside or by incorporating a signal generation circuit, so that it can be adapted to the usage pattern of the user.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic layout diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic layout diagram showing a reset signal supply system.

FIG. 4 illustrates a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a schematic layout diagram showing another reset signal supply system.

FIG. 5 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a configuration diagram illustrating a DRAM macro.

FIG. 6 shows a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a logic diagram illustrating a flip-flop circuit.

FIGS. 7A to 7C are timing charts showing operations of a flip-flop circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 8 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 9 is a circuit diagram illustrating another flip-flop circuit.

FIG. 9 illustrates a semiconductor device according to an embodiment of the present invention.
FIG. 9 is an explanatory diagram illustrating an operation mode of another flip-flop circuit.

FIG. 10 is a logic diagram showing a reset signal generation circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 11 is an explanatory diagram showing truth values of a reset signal generation circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 12 is an explanatory diagram showing transition of a reset signal potential of a reset signal generation circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 13 is a logic diagram showing another reset signal generation circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 14 is an explanatory diagram showing a transition of a reset signal potential of another reset signal generation circuit in the semiconductor device according to one embodiment of the present invention;

FIG. 15 is a schematic configuration diagram showing a semiconductor device as a premise of the present invention.

FIG. 16 is an explanatory diagram showing transition of a power supply potential in a semiconductor device which is a premise of the present invention.

FIG. 17 is an explanatory diagram showing transition of an output potential of a flip-flop circuit in a semiconductor device which is a premise of the present invention.

[Explanation of symbols]

 Reference Signs List 1 DRAM macro 2, 3 Logic circuit 4-7 Flip-flop circuit 8 LSI pin 9 Reset signal generation circuit 11 DRAM array 12 Main amplifier 13 Write amplifier 14 Row decoder 15 Column decoder 16 Control circuit 17 DFT circuit 18 Maxell decoder 19 Clock generator 20 Power generators 21 to 23 Flip-flop circuits L1, L2 Logic gate circuits G1 NAND gate G2 Inverter G11, G12 NAND gate G13 to G15 Pass gate G16 NOR gate G17 NAND gate G18 to G30 Inverter FF1 to FFn Flip-flop circuit G41 AND gate D51 Diode R51 Resistance G51 Inverter

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H03K 3/037 H03K 3/037 A (72) Inventor Hiroshi Akasaki 5-chome, Josuihoncho, Kodaira-shi, Tokyo 22-1 Inside Hitachi Ultra SII Systems Co., Ltd. (72) Inventor Shuichi Miyaoka 3-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside Hitachi Device Co., Ltd. Device Development Center (72) Inventor Nakayama Michiaki 3-16-6 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shoji Kume 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture F-term in the Enterprise Server Division of Hitachi Ltd. 5B048 AA20 CC18 DD08 5J032 AA02 AB02 AC14 5J043 AA13 EE01 HH02 JJ03 KK02 5J055 AX57 AX66 BX42 CX27 DX27 EX03 EY12 EZ07 EZ25 EZ29 EZ32 FX13 FX17 GX00 GX01 GX08 5L106 AA01 DD08 EE03 FF08

Claims (5)

[Claims] 1. A semiconductor device in which a logic circuit and a storage circuit are mixedly mounted, wherein a flip-flop circuit with a reset function having a reset signal input terminal is provided in an input stage and an output stage of the storage circuit, A semiconductor device wherein the reset signal is controlled at the time of turning on to fix the output of the flip-flop circuit with a reset function. 2. The semiconductor device according to claim 1, wherein the flip-flop circuit with a reset function has an input / output terminal for diagnostic data, and further has a diagnostic function by a scan method. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the reset signal is supplied from outside. 4. The semiconductor device according to claim 1, wherein said reset signal is a plurality of flip-flop circuits whose data input terminals are open, and a logical product gate for performing a logical product operation on outputs of said plurality of flip-flop circuits. A semiconductor device, which is generated as an output signal of a signal generation circuit having a circuit. 5. The semiconductor device according to claim 1, wherein the reset signal is connected to a diode and a resistor connected in series between a power supply potential and a ground potential, and to a connection node between the diode and the resistor. A semiconductor device which is generated as an output signal of a signal generation circuit having an inverter.