JPH07262797A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device having a decision circuit which shortens the test time of a built-in RAM with a simple constitution and has high reliability. CONSTITUTION:This semiconductor integrated circuit device forms a complementary output signal by receiving the reading out signals outputted in unit of plural bits from the built-in RAM and inputs such output signal as well as the non-inversion signal and inversion signal of an expected value respectively into logic circuits. The outputs of both logic circuits are compared by a coincidence/noncoincidence circuit and a decision output is obtd. Consequently, the simultaneous decision of the output signals from the RAM together with the expected value in the unit of the plural bits is executed, and in addition, the output for diagnosis disposed in the semiconductor integrated circuit device is composed of one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a testing technique for a semiconductor integrated circuit device such as a gate array having a built-in RAM (random access memory; hereinafter simply referred to as RAM). It is related to effective technology.

[0002]

2. Description of the Related Art A technique for testing a built-in RAM is disclosed in, for example, Japanese Patent Laid-Open No. 62-170100.
In this semiconductor integrated circuit device, a selector is provided in order to prevent an increase in the number of terminals for diagnosis, and the output of the built-in RAM is narrowed down by the selector to make an LSI (semiconductor integrated circuit device).
Is output from.

[0003]

In the semiconductor integrated circuit device, since the output of the built-in RAM is narrowed down by the selector and output to be judged as the expected value by the IC tester, the RAM test is frequently activated and the test time is long. There is a problem of enormous volume. Further, if a decision circuit for making a decision with an expected value is provided inside the LSI and a comparison is made for each data, there arises a problem that the circuit area and current consumption increase.

An object of the present invention is to provide a built-in RA with a simple structure.
An object of the present invention is to provide a semiconductor integrated circuit device that realizes a reduction in the test time of M. Another object of the present invention is to provide a semiconductor integrated circuit device including a highly reliable determination circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a complementary output signal is formed by receiving a read signal output from the built-in RAM in units of a plurality of bits, and the output signal and a non-inverted signal of an expected value and an inverted signal are input to each logic circuit, The outputs of both logic circuits are compared by the coincidence / non-coincidence circuit to obtain a judgment output.

[0006]

According to the above-mentioned means, the output signal from the RAM can be collectively judged in units of a plurality of bits together with the expected value, and moreover, only one diagnostic output pin can be provided in the semiconductor integrated circuit device.

[0007]

FIG. 3 is a schematic block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. The circuit circuit block shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The semiconductor integrated circuit device of this embodiment includes a memory circuit RAM and a logic circuit for logically processing the stored information. That is, the semiconductor integrated circuit device of this embodiment is a special-purpose LSI including a gate array or standard cell type RAM and a logic circuit. The logic circuit is composed of a logical sum circuit and / or a logical product circuit.
This semiconductor integrated circuit device has a two-phase external clock CK0,
It operates based on CK1. The external clock CK1 is a clock signal that is 180 ° out of phase with the external clock CK0. The phase shift of the clock CK1 is not limited to 180 °, and the phase shift can be set arbitrarily. The write pulse generation circuit WPG has 2
It receives the phase external clocks CK0 and CK1 and generates an internal clock signal.

Although not particularly limited, the address signals supplied from the address input external terminals A0-Am are taken into the address latches AD0-ADm in synchronization with the clock signal CK0 (rising timing). The write data input from the external terminals D0 to Dn for data input also receives the data in latch W in synchronization with the clock signal CK0.
It is taken into D0 to WDn. The RAM decodes the address signal and decodes n + 1 multiple bits (the number of complementary data lines).
The memory cell corresponding to is selected, and if it is a write operation, the data fetched in the data-in latches WD0 to WDn is written. If it is a read operation, the read signal from the selected memory cell is transferred to the data out latches DO0 to D0.
Output to On.

In the RAM, the internal clock signal generated from the write pulse generation circuit WPG is a control signal C from the outside.
It is controlled based on ONT. In the normal operation mode (when the test signal TST is at low level), the output signals of the data out latches DO0 to DOn are input to the logic circuit and data processing is performed. By the way, in the test mode (when the test signal TST is at a high level), the selector SEL selects the output of the clock signal CK1, and the data out latches DO0 to DOn input / output data in synchronization with the clock signal CK1. .

In this embodiment, a comparison / determination circuit is provided in order to test the RAM in a single time. The data out latches DO0 to DOn are
An output circuit for testing is provided. This output circuit outputs two signals, a non-inverted output (positive signal P) and an inverted output (negative signal N). Further, an expected value is input to a specific data-in latch WDn among the data-in latches, and an output signal thereof is input to the comparison / determination circuit.

The comparison / determination circuit inputs the n + 1-bit non-inverted output P and the inverted output N from the data-out latch and the complementary expected value corresponding to each to a logic circuit, and outputs a match / mismatch determination signal. Send to external terminal.
The comparison / determination circuit determines all "0" or all "1" of all inputs.

The address latches AD0-ADm and the data-in latches WD0-WDn receive input signals to which address signals and write data are directly supplied from external terminals, as well as address signals and write data formed by internal logic circuits. Has an input terminal supplied. That is,
The address latch and data-in latch of the RAM have input terminals connected to the address bus AB and the data bus DB formed inside the semiconductor integrated circuit. Each of the address latches AD0 to ADn has a selector circuit sel.
And address holding circuits ad0 to adm, and each of the data-in latches WD0 to WDn is a selector circuit s.
el and data holding circuits wd0 to wdm. Each selector circuit sel selects an address signal and write data from one of the external terminal or the internal logic circuit according to the supplied test signal, and the address holding circuit ad0
To adm and the data holding circuits wd0 to wdn. When the test signal TST of low level “0” is supplied to the selector circuit sel, the address holding circuits ad0 to ad0
adm and the data holding circuits wd0 to wdn latch the address signal and the write signal from the internal logic circuit.
Further, when the test signal TST of high level “1” is supplied to the selector circuit sel, the address holding circuit ad0
~ Adm and data holding circuits wd0-wdn latch address signals and write signals from external terminals. The test signal supplied to each of the selector circuits may be supplied from a terminal different from the test terminal.

FIG. 10 and FIG. 11 show internal block diagrams of the memory circuit RAM. FIG. 10 shows a block diagram centering on each circuit of the memory array and address selection system, and FIG. 11 shows a block diagram centering on each circuit of the write / read system. Figure 1
1, the Y switch, the memory array, etc., which are duplicated in FIG. 10, are illustrated in a simplified manner.

The memory array is divided into 28 memory blocks MB0 to MB27. Each memory block is
It has a plurality of word lines, a plurality of complementary data lines, and a plurality of memory cells. Multiple Y's corresponding to each complementary data line
Switches YS0 to YS27 are provided, and further read sense amplifiers SA0 to SA27 and write amplifier WA.
0 to WA27 are memory blocks MB0 to M, respectively.
It is provided corresponding to B27.

The address signal supplied from the address latch is supplied to an X system address decoder (X address predecoders 1, 2 for redundancy) and a Y system address decoder (Y address predecoders 1, 2), and further, an X driver. And Y driver to select a complementary data line from each memory block, one Y switch and one Y switch.
A word line of the book is selected.

The write enable signal and the block select signal are externally supplied as a control signal CONT as shown in FIG. The data held in the data-in latch is the corresponding write amplifier WA0-WA.
27 and further to each complementary data line through the selected Y switch. Each of the write amplifiers WA0 to WA27 has a control signal CO.
When the high level "1" write enable signals WE0-N to WE3-N supplied as part of NT are supplied (write L), the data supplied from the data-in latch is the corresponding memory block. Can be supplied to the memory cells inside. Each of the write amplifiers WA0 to WA27 has a write enable signal W of low level “0”.
When WE3-N is supplied from E0-N (readout H
In this case, the data supplied from the data-in latch cannot be supplied to the memory cells in the corresponding memory block (high impedance state).

Further, write amplifiers WA0 to WA27.
Each of them is a block select signal BS0-N to BS6-N supplied as a part of the control signal CONT.
Each enables or disables writing data into the corresponding memory block. For example, when the block select signal BS0-N of low level "0" is supplied to the write amplifier WA0, the write amplifier WA0 supplies the data from the data-in latch to the memory block MB0, but the block select signal of high level "1". When the signal BS0-N is supplied to the write amplifier WA0, the write amplifier WA0 does not supply the data from the data-in latch to the memory block MB0. The same applies to the write amplifiers WA1 to WA27. The read sense amplifiers SA0 to SA27 are X
The data read from the memory cell selected by the address signal supplied to the system address decoder and the Y system address decoder is amplified and supplied to the data out latch. The data write operation and data read operation are executed according to the internal clock signal generated from the write pulse generation circuit WPG.

Although the write enable signal is supplied to the write amplifier WA in the figure,
The present invention is not limited to this, and the write enable signal may be directly supplied to the write pulse generation circuit WPG to execute the write operation and the read operation of the memory circuit.

FIG. 1 is a circuit diagram showing an embodiment of the output section of the data out latch and the comparison / determination circuit.
In the figure, a specific circuit of one output circuit is shown as a representative among the output signals composed of n + 1 bits as described above. In this embodiment, the output circuit is the ECL
(Emitter coupled logic).

The RAM output circuit (0) is composed of a normal output type and a test type. The output signal of the latch circuit as described later is supplied to the base of the differential transistor Q1. This transistor Q1 and a transistor Q in a differential form
A reference voltage is supplied to the base of 2. Load resistors R1 and R2 are provided at the collectors of the differential transistors Q1 and Q2. The common emitter of the differential transistors Q1 and Q2 is provided with a transistor Q7 as a constant current source. The base of this transistor Q7 has a constant voltage VCS
Is supplied, and an emitter resistor R3 is provided at the emitter to form a constant current.

The collector outputs of the differential transistors Q1 and Q2 are transmitted to the bases of the emitter follower output transistors Q3 and Q4 on the one hand. Load resistors R4, R5 and R6 are provided between the emitters of the transistors Q3 and Q4 and the voltage terminal VTT, and non-inverted (positive) and inverted (negative) are output from the emitters of the transistors Q3 and Q4 as normal outputs. ) Is transmitted to the logic circuit which is the next stage circuit. The output signals of other similar RAM output circuits (1) to (n) are also input to the logic circuit.

In this embodiment, emitter follower transistors Q5 and Q6 for receiving the collector outputs of the differential transistors Q1 and Q2 are provided as a test output circuit. The inverted output N is output from the emitter of the output transistor Q5 corresponding to the collector output of the transistor Q1, and the non-inverted output P is output from the emitter of the output transistor Q6 corresponding to the collector output of the transistor Q2. Similar complementary signals are output from the similar test output circuits of the other RAM output circuits (1) to (n). Among the complementary output signals, corresponding ones are commonly connected to the emitters of the output transistors in order to obtain the logical sum of the non-inverted signal P and the inverted signal N. That is, the non-inverted signal line PL and the inverted signal line NL of the common complementary data line CL are R
AM output circuits (0) to (n) and data in latch WD
The wired OR logic of the non-inverted signal line PL and the inverted signal line NL of each n is respectively adopted.

The expected value taken into the data-in latch WDn is supplied to the gate circuit G1. The gate circuit G1 is composed of a differential circuit including the differential transistors Q1 and Q2, collector resistors R1 and R2, and a constant current source transistor Q7, and a circuit similar to the output transistors Q5 and Q6. Are connected to the memory output and a wired OR configuration.

The wired logic signals of both the non-inverted signal P and the inverted signal N are supplied to the exclusive OR circuit EOR as a match / mismatch circuit. The output signal of the exclusive OR circuit EOR is sent from the external terminal of the semiconductor integrated circuit device LSI as a determination output.

The read data from the RAM is all "0" (low level) and the corresponding expected value is "0".
At this time, n output from the RAM output circuits (0) to (n)
The +1 bit and the expected value are all set to low level. That is, the n + 1-bit data and the expected 1-bit non-inverted signal P are set to low level, and the inverted signal N is set to high level. If all the bits are "0", the wired logic output of the non-inversion side P becomes low level, and the wired logic output of the inversion side N becomes high level. As a result, the exclusive OR circuit EOR outputs a low level (“0”) pass signal because both inputs are at a low level and a high level.

If even one bit does not match, there is a high level on the non-inverted signal side P side which should be set to the low level, and the wired logic output of the non-inverted side P is set to the high level. . Therefore, the exclusive OR circuit EOR is supplied with a high level and outputs a high level (“1”) Fail signal.

The read data from the RAM is all "1" (high level) and the corresponding expected value is "1".
At this time, the n + 1 bits and expected values output from the RAM output circuits (0) to (n) are all set to the high level. That is, the n + 1-bit data and the 1-bit non-inverted signal P of the expected value are set to the high level, and the inverted signal N is set to the low level. If all the bits are "1", the wired logic output of the non-inversion side P becomes high level, and the wired logic output of the inversion side N becomes low level. As a result, the exclusive OR circuit EOR outputs a low-level (“0”) pass signal because both inputs do not match the high level and the low level.

If even one bit does not match, there is a high-level one on the side of the inverted signal N to be brought to the low level, and the wired logic output on the inverted side N is set to the high level. Therefore, the exclusive OR circuit EOR is supplied with a high level and outputs a high level (“1”) fail signal. In Table 1 below,
A truth table of expected values and logic outputs and decision outputs of the non-inverting side P and the inverting side N is shown.

In this embodiment, matching / including the expected value
Since the determination is made as to the disagreement, a highly reliable determination result can be obtained. As described above, the read signals are all “0” or all “1” without comparison with the expected value.
If the pass / fail judgment is made with
Even if there is a defect in which all "0" s or all "1" s are always output due to defective AM address selection, defective read signal path or defective output circuit, etc., it cannot be found.

[0030]

[Table 1]

FIG. 2 shows a circuit diagram of another embodiment of the output portion of the data out latch and the comparison / determination circuit. In the same figure, as in the case of FIG. 1, a specific circuit of one output circuit among the output signals consisting of n + 1 bits is exemplarily shown as a representative.

In this embodiment, the n + 1 bit is divided into two, and each of the divided test output lines has a wired OR logic configuration such as PL0, NL0 and PL1, NL1. It is inputted to the exclusive OR circuits EOR0 and EOR1. Then, the determination output 0 and the determination output 1 are output from the two exclusive OR circuits EOR0 and EOR1.

Expected value inputs 0 and 1 are provided corresponding to the two divisions of the output signal as described above. The expected value inputs 0 and 1 do not mean a signal level such as a logic "0" or a logic "1", but correspond to the two wired OR logics PL0, NL0 and PL1, NL1. There is. By dividing such an output signal into two, output patterns such that one is all "0" and the other is all "1" are collectively determined.

FIG. 7 is a block diagram showing an embodiment of the RAM and the comparison / decision circuit incorporated in the semiconductor integrated circuit device according to the present invention. This embodiment is an overall block diagram corresponding to the embodiment of FIG.

The memory array is divided into memory blocks (or memory mats) MB0 to MB5. The address decoder decodes the address input and forms a select signal for the word line and data line of the memory array. That is, the address decoder includes an X system decoder that forms a word line selection signal and a Y system decoder that forms a data line selection signal. The selection signal formed by the address decoder is supplied to the word line and data line selection switch circuits of the memory array through the driver.

The write amplifier has a data-in latch WD0.
To WDn (n = 5 in the embodiment shown in the drawing), write data is received and writing is performed to one selected memory cell of the memory blocks MB0 to MB5. That is, in the RAM of this embodiment, data writing is performed in units of 6 bits.

The sense amplifier is used for each memory block MB0.
In MB5, the stored information of each selected memory cell is sensed and transmitted to the output circuit. As a result, in the RAM of this embodiment, data reading is performed in units of 6 bits as in the writing operation.

The data out latches DO0-DOn are provided with an output circuit for normal output and a test output circuit.
The output signal passed through the normal output circuit is input as a RAM output to a logic circuit (not shown) or the like. The test output signal is divided into two sets. In this embodiment, adjacent memory blocks are divided into two in order to investigate signal interference between adjacent bits. Memory blocks MB0, MB2 and MB
4 are set as the same group, and a wired OR configuration is made with the expected value input 0. Memory blocks MB1, MB3 and M
B5 is made into the same group, and is made into a wired OR configuration together with the expected value input 1.

The wired OR logic signal of each of the non-inverted signal and the inverted signal divided into the above two groups is supplied to the exclusive OR circuits EOR0 and EOR1. Then, the outputs of the exclusive OR circuits EOR0 and EOR1 are not directly output to the outside as the determination outputs, but are output from one diagnostic output terminal through the OR circuit G3.

FIG. 8 shows a schematic block diagram of an embodiment of a memory circuit RAM to which the present invention is applied.
Each circuit block in the figure is drawn according to the geometrical arrangement on the semiconductor chip. The memory array MA is
It is divided into eight like memory blocks MB0 to MB7. Memory access is performed in units of 8 bits by selecting one memory cell from each of the memory blocks MB0 to MB7. That is, this memory array MA
An X decoder XD is provided at the left end of the. The X decoder XD includes the driver as described above at its output section and selects one word line shared by the memory blocks MB0 to MB7. Below the memory array MA, a sense amplifier SA and a write amplifier WA are arranged. Column switches are provided at the sense amplifier SA, the input section, and the output section of the write amplifier WA, and a selection signal formed by the Y decoder YD is transmitted. Each memory block M
B0 to MB7 have a plurality of data lines, and one data line is selected by the column switch.

FIG. 9 shows a circuit diagram of an embodiment of the memory block shown in FIG. In the figure, two memory blocks corresponding to the memory blocks MB0 and MB1 are exemplarily shown as a representative.

The memory cell is a P-channel type MOSFE.
Two CMOs consisting of T and N channel MOSFETs
It is composed of a latch circuit in which the input and output of the S inverter circuit are cross-connected to each other, and a transmission gate MOSFET formed of an N-channel MOSFET provided between the pair of input / output and the complementary data line. That is,
A static type memory cell having a CMOS structure is used. The gate of the transmission gate MOSFET is the word line W.
Connected to 0. The pair of input / output nodes of the memory cell is
Connected to complementary data lines D00 and / D00. In this specification, an overbar indicating an inversion side data line in the drawing is represented by / (slash).

One memory block MB0 contains D0
There are provided n + 1 pairs of complementary data lines consisting of 0, / D00 to D0n, / D0n. Complementary data lines D00 and / D0
A load MOSFET acting as a resistance element is provided in each of 0 to D0n and / D0n. These complementary data lines D
00, / D00 to D0n, / D0n are made common through a switch MOSFET as a column switch, and are connected to the output terminal of the write amplifier WA0 and the input terminal of the sense amplifier SA0. In the write operation, the write amplifier WA0 is activated, the write data is transmitted to the pair of complementary data lines selected by the Y selection signals Y0 to Yn, and the word line writes the data to the selected memory cell.

In the read operation, the write amplifier W
A0 is set to an output high impedance state, and a signal of a pair of complementary data lines selected by Y selection signals Y0 to Yn is sensed among the complementary data lines to which the read signal from the memory cell is output when the word line is selected. Amplifier SA
It is transmitted to 0. The signal read from the CMOS static memory cell is differentially amplified by the sense amplifier SA0, converted to the ECL level, and transmitted to the output circuit. Conversely, the ECL level write data is
It is converted into a CMOS level by the write amplifier WA0 and transmitted to the complementary data line as the write signal as described above. Since a RAM including such a memory cell having a CMOS structure and a peripheral circuit having ECL compatibility is well known, its detailed description will be omitted.

A memory block MB1 illustrated as another representative and another memory block M not shown.
Also in B2 to MB27, a circuit similar to the above is used to perform writing or reading. In this way, memory access is performed in units of 28 bits as a whole.

Since the cache memory has a short address length, one memory array is divided into memory blocks MB0 to MB7 as shown in FIG. Therefore, it is necessary to test whether there is a defect due to a short circuit between data or crosstalk noise. Therefore, by applying the embodiment of FIG. 7, it is possible to perform a test by using different data for adjacent circuits on the layout. That is, memory blocks MB0, MB2, MB4 and MB
6 as one set, and memory blocks MB1, MB3, MB5
, And MB7 as another set, and expected value inputs 0 and 1 are assigned to each set.

As a result of such grouping, the data line / D0n of the memory block MB0 in the embodiment of FIG.
And the data line D of the memory block MB1 adjacent to it
Data interference between 10, sense amplifiers SA0 and SA1
Interference between the signal lines of the write amplifiers WA0 and WA1 can be examined.

FIG. 4 is a schematic block diagram of another embodiment of the semiconductor integrated circuit device according to the present invention.
In the semiconductor integrated circuit device of this embodiment, a plurality of macro R
AM is installed. In this case, if a comparison / determination circuit is provided in each macro RAM and each determination signal is independently output from the external terminal, the number of external terminals increases. Therefore, in this embodiment, it is output as a chip batch determination output through an OR gate circuit.

That is, in a semiconductor integrated circuit device having a large number of macro RAMs, when a plurality of RAMs are tested at the same time, if any one fail signal is output, a fail signal can be output through the OR gate circuit. it can. In this case, which RAM has a failure can be found by testing the macro RAMs one by one, so there is no problem. This means that in addition to simultaneously testing a plurality of macro RAMs as described above, a test result can be obtained by testing each macro RAM individually. 1 to 3, the portion excluding the logic circuit corresponds to the macro RAM.

FIG. 5 shows a circuit diagram of another embodiment of the present invention. In this embodiment, the data length R is long.
The case applied to AM is shown. That is, the data D held in the flip-flop circuits FF0 to FF27
An example is shown in which memory access is performed in 28-bit units such as 0 to D27.

Also in this embodiment, there are roughly two groups in order to detect the interference of adjacent bits or adjacent circuits. That is, even bits such as D0 to D26 and D1 to D27
Is divided into odd bits like. In this case, D0-D
When 14 outputs such as 26 and one expected value are configured as a wired OR configuration, in consideration of the deterioration of the level margin due to the potential decrease due to the wiring resistance, the first set of D0, D2, D4 and D6 is provided. , D8, D10, D12 and the expected value (write data WD0) held in the flip-flop circuit FFW0, the third set D14, D16 and D18, and D20, D22, D24 and D26. As in the fourth set, the wired logic is divided into four and is supplied to the exclusive OR circuit ENOR0 through the OR gate circuit to obtain the judgment output RAMSQ0. Also for odd-numbered bits, similarly to the above, it is divided into four groups and the wired logic and the OR logic by the gate circuit are taken and supplied to the exclusive OR circuit ENOR1 to output the judgment output RA.
Obtain MSQ1.

In this embodiment, the expected value is for inputting an inverted signal. In response, the output signal corresponding to the expected value has the non-inverted output and the inverted output connected to the wired OR configuration in reverse. The reason for inverting the expected value input in this way is as follows.

If a defect such that the RAM is always written is generated, the data written in the RAM is directly output without being output. That is, since the write input and the expected value are output through the RAM, the pass signal is always formed. On the contrary,
In the method of inputting the inverted signal as the expected value for the write data, the write data is expected to have a defect such that it enters the write state even though the above read operation is instructed. Since the value is inverted, the fail signal is output. As described above, a highly reliable determination result can be obtained by a simple configuration in which the expected value is inverted and input, and the connection is reversed in the wired logic to adjust the level. In the figure, for the sake of clarity, only the output Q of the flip-flop circuit FF20 is coupled to the logic circuit, but the output Q of the other flip-flop circuits FF0 to FF19 and FF21 to FF27 are also shown. Coupled to a logic circuit. Here, since the output Q of each flip-flop circuit is a complementary signal composed of a non-inverted output and an inverted output, it is shown by two lines.

FIG. 6 shows a specific circuit diagram of an embodiment of the data out latch provided in the above memory circuit RAM. The data out latch of this embodiment is E
It is composed of a D-type flip-flop circuit having a CL structure. Complementary read signals (data-in latch holding signal) D and / D from the sense amplifier are supplied to the differential transistor Q8.
And supplied to the base of Q9. Load resistors consisting of load resistors R7 and R8 and R9 and R10 are provided at the collectors of these differential transistors Q8 and Q9. The collector outputs of the differential transistors Q8 and Q9 are directly ECL
Output signals Q and / Q are transmitted to the base of an emitter follower output transistor (not shown).

The load resistors R7 and R8 and R9 and R10
The level-shifted output signal obtained from the connection point of
It is supplied to the bases of the transistors Q3 and Q4. The emitters of the transistors Q3 and Q4 have an emitter resistance R
4, R5 and a resistor R6 common to them are provided and connected to the power supply terminal VTT.

The emitter follower outputs of the transistors Q4 and Q3 are supplied to the bases of differential transistors Q12 and Q13 for feedback input. These transistors Q
The collectors of 12 and Q13 are cross-connected to the collectors of the input differential transistors Q8 and Q9. That is,
The collector outputs of the differential transistors Q12 and Q13 are connected so as to be positively fed back through the transistors Q3 and Q4. The feedback transistors Q12 and Q13
Is provided with a transistor Q10 receiving the set signal S and a transistor Q11 receiving the reset signal R.

To the emitters of the input transistors Q8 and Q9, the collector of the transistor Q14 having the base supplied with the non-inverted clock signal CK is connected. The feedback transistors Q12, Q13 and the set / reset transistors Q10, Q11 have their emitters supplied with the inverted clock signal / CK.
Is provided. Transistors Q14 and Q15 supplied with the clock signals CK and / CK are formed in a differential form,
A constant current source is provided in the common emitter. This constant power supply is composed of a transistor Q16 having a constant voltage VCS applied to its base and its emitter resistor R11.

The latch circuit performs a through / latch operation. That is, when the clock signal CK is at high level, the input differential transistors Q8 and Q9 are enabled,
Signals corresponding to the input signals D and / D are output. On the other hand, when the clock signal CK is set to the low level and / CK is set to the high level, the differential transistors Q10 to Q10 on the feedback side.
When Q13 is valid and the set signal S and the reset signal R are low level, the fetched data is held.
At this time, when the signal S is set to the high level, a signal corresponding to the held data is output instead of the above-mentioned held data. When the signal R is set to the high level, a corresponding signal is output instead of the held data.

In this embodiment, the output signals of the transistors Q3 and Q4 are supplied to the differential transistors Q1 and Q2 as a test output circuit. Differential transistors Q1 and Q
Load resistors R1 and R2 are provided in the collector of No.2.
A constant current source composed of a transistor Q7 and a resistor R3 is provided at the common emitter of the differential transistors Q1 and Q2.

The output of the unit circuit having the ECL structure is output as complementary signals SQ and / SQ for testing through the emitter follower output transistors Q5 and Q6. The emitter load resistors R1 and R2 are connected in one circuit among a plurality of circuits connected in a wired OR configuration. The selective connection of the load resistance is performed by the master slice method.

The operation and effect obtained from the above embodiment are as follows. That is, (1) receiving a read signal output from the built-in RAM in units of multiple bits to form a complementary output signal,
The output signal and the non-inverted signal of the expected value and the inverted signal are input to the respective judgment logic circuits, and the outputs of both judgment logic circuits are compared with the coincidence / non-coincidence circuit to obtain the judgment output. The output signal can be collectively determined together with the expected value in units of a plurality of bits, and moreover, the diagnostic output pin provided in the semiconductor integrated circuit device can be configured with one.

(2) Regarding the signals output in the unit of a plurality of bits, the signals whose signal output paths are physically adjacent to each other are divided into two and output, respectively, and the first expected value and the second expected value are output. By providing the first and second logic circuits and the first and second match / mismatch circuits corresponding to the expected values, it is possible to obtain the effect of being able to obtain the interference determination result of adjacent bits.

(3) By configuring the memory cell of the RAM by the CMOS circuit, making the input / output interface compatible with the ECL circuit, and utilizing the wired logic by utilizing the emitter follower output in the ECL circuit. Since the comparison / determination circuit can be configured substantially only by the exclusive OR circuit, it is possible to obtain a significant simplification of the circuit and a reduction in power consumption.

(4) The output circuit, the logic circuit, and the match / mismatch circuit are provided in the RAM made up of a plurality of RAMs, and the output signals of the match / mismatch circuit made of a plurality of these RAMs are output from one external terminal through the logic circuit. With the configuration for outputting, the effect of reducing the number of diagnostic output terminals can be obtained.

(5) By inputting the inverted value and returning it to the original value on the logic circuit side, the expected value is returned.
It is possible to obtain the effect that it is possible to detect a RAM defect that is always in a written state.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, RA
All of M may have an ECL configuration or a CMOS configuration. In the CMOS configuration, the output circuit for testing has an open drain configuration and is connected by wired logic to simplify the circuit. Alternatively, an OR gate circuit, a NOR gate circuit, an AND gate circuit, or a NAND gate circuit may be used as the circuit for determining all "0" or all "1" of the corresponding complementary signals for testing. The match / mismatch circuit may be any other than the exclusive OR circuit as long as it can detect the match / mismatch.

The RAM may be a semiconductor memory device itself, such as a gate array, which is built in a semiconductor integrated circuit device, or a memory which is accessed in a unit of a plurality of bits such as 8 bits or 16 bits. This invention is a variety of R
It can be widely used for semiconductor integrated circuit devices including AM.

[0068]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a complementary output signal is formed by receiving a read signal output from the built-in RAM in units of a plurality of bits, and the output signal and a non-inverted signal of an expected value and an inverted signal are input to each logic circuit, By comparing the outputs of both logic circuits with the coincidence / non-coincidence circuit to obtain the judgment output, the output signal from the RAM can be collectively judged together with the expected value in units of a plurality of bits, and further, the diagnostic output provided in the semiconductor integrated circuit device. One pin can be configured.

The signals output in the unit of a plurality of bits are divided into two output signals whose signal output paths are physically adjacent to each other, and are output as a first expected value and a second expected value, respectively. Correspondingly, by providing the first and second logic circuits and the first and second match / mismatch circuits, it is possible to obtain the judgment result of the interference of the adjacent bits.

By comparing the memory cell of the RAM with the CMOS circuit, making the input / output interface compatible with the ECL circuit, and utilizing the wired logic by utilizing the emitter follower output in the ECL circuit, the comparison / determination circuit can be Substantially simplification of the circuit and reduction in power consumption are possible, as it can be configured by only an exclusive OR circuit.

A structure in which the output circuit, the logic circuit, and the match / mismatch circuit are provided in the RAM composed of a plurality of pieces, and the output signal of the match / mismatch circuit composed of a plurality of these is output from one external terminal through the logic circuit. As a result, the number of diagnostic output terminals can be reduced.

By inputting an inverted value of the expected value and returning it to the original value on the logic circuit side, it is possible to detect a RAM defect that is always in a written state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an output section of a data out latch and a comparison / determination circuit provided in a memory circuit RAM of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the output portion of the data out latch and the comparison / determination circuit provided in the memory circuit RAM of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is a schematic block diagram showing another embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a specific circuit diagram showing an embodiment of a data out latch provided in the memory circuit RAM of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a block diagram showing an embodiment of a memory circuit RAM of a semiconductor integrated circuit device according to the present invention and a comparison / determination circuit thereof.

FIG. 8 is a schematic block diagram showing an embodiment of a memory circuit RAM to which the present invention is applied.

9 is a circuit diagram showing an embodiment of the memory block of FIG.

FIG. 10 is a partial internal block diagram showing an embodiment of a memory circuit RAM mounted in the semiconductor integrated circuit device according to the present invention.

FIG. 11 is a partial partial internal block diagram showing an embodiment of a memory circuit RAM mounted in the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

LSI ... Semiconductor integrated circuit device, Q1-Q16 ... Transistor, R1-R13 ... Resistor, EOR0-EOR1 ... Exclusive OR circuit, AD0-ADm ... Address latch, WD
0-WDn ... Data in latch, sel ... Selector circuit, ad0-adm ... Address holding circuit, wd0-wd
m ... Data holding circuit, DO0 to DOn ... Data out latch, XD ... X decoder, MA ... Memory array, MB0
~ MB27 ... Memory block, YD ... Y decoder, YS
0-YS27 ... Y switch, WA, WA0-WA27 ...
Write amplifier, SA, SA0 to SA27 ... Sense amplifier. WPG ... Write pulse generation circuit, SEL ... Selector.

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[Procedure amendment]

[Submission date] February 22, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

The write enable signal and the block select signal are externally supplied as a control signal CONT as shown in FIG. The data held in the data-in latch is the corresponding write amplifier WA0-WA.
27 and further to each complementary data line through the selected Y switch. Each of the write amplifiers WA0 to WA27 has a control signal CO.
When the low level "0 " write enable signals WE0-N to WE3-N supplied as part of NT are supplied (write L), the data supplied from the data-in latch is in the corresponding memory block. Can be supplied to the memory cells. Each of the write amplifiers WA0 to WA27 has a write enable signal W of high level "1 ".
When WE3-N is supplied from E0-N (readout H
In this case, the data supplied from the data-in latch cannot be supplied to the memory cells in the corresponding memory block (high impedance state).

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 21/66 W 7630-4M (72) Inventor Kunihiko Yamaguchi 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development In the center

Claims (8)

[Claims] 1. A plurality of memory cells coupled to a plurality of complementary data lines each having an inverted signal line and a non-inverted signal line, and one memory cell is simultaneously selected from each of the plurality of complementary data lines. A semiconductor integrated circuit having a selection circuit and a determination circuit to which data in the memory cells simultaneously selected by the selection circuit are supplied and which determines whether or not the supplied data match each other. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein each of the memory cells simultaneously selected by the selection circuit is connected to one word line. 3. The semiconductor integrated circuit device according to claim 1, wherein the data supplied to the determination circuit includes an inverted / non-inverted signal. 4. The method according to claim 3, further comprising a common complementary signal line having an inverted signal line and a non-inverted signal line, wherein the inverted signal line of each of the plurality of complementary data lines is the common complementary signal line. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is coupled to an inversion signal line, and the non-inversion signal line of each of the plurality of complementary data lines is coupled to the non-inversion signal line of the common complementary signal line. 5. The semiconductor integrated circuit device according to claim 4, wherein the determination circuit is coupled to an inverted signal line and a non-inverted signal line of the common complementary signal line. 6. The determination circuit according to claim 4, further comprising a latch circuit which stores an expected value and is coupled to the common complementary signal line via an inverted signal line and a non-inverted signal line, and the determination circuit is the selection circuit. A semiconductor integrated circuit device, characterized in that it is determined whether or not the data supplied from each of the memory cells simultaneously selected by is matched with the expected value. 7. The method according to claim 6, further comprising a plurality of memory blocks including at least two determination circuits and at least one complementary data line, each memory block being coupled to a determination circuit different from an adjacent memory block. A semiconductor integrated circuit device. 8. The method according to claim 7, further comprising at least two latch circuits for storing expected values, wherein one of the at least two determination circuits is supplied with the expected value from one of the at least two latch circuits. The expected value is supplied from the other of the at least two latch circuits to the other of the at least two determination circuits.