JP2010057006A - Receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiving circuit for obtaining a clock signal, whose phase is matched to input data, stably and with low power consumption. <P>SOLUTION: A receiving circuit includes a control circuit 30, an oscillation circuit 40, a frequency divider circuit 50, a flip-flop circuit, first and second phase comparator circuits and the like wherein, when input data contain signal information, an oscillation frequency of the oscillation circuit 40 is controlled on the basis of results of phase comparison between a clock signal and the input data and if the input data do not contain any signal information, the oscillation frequency is controlled on the basis of the results of phase comparison between a feedback signal obtained by frequency-dividing the clock signal and a reference signal that is varied in a fixed cycle. The oscillation circuit 40 is configured to control the oscillation frequency in accordance with two systems of control signals, to change the oscillation frequency gradually and largely with respect to a change in the control signal of one system and to change the oscillation frequency immediately and small (just a little) with respect to a change in the control signal of the other system. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a receiving circuit for receiving input data, and in particular, in a PLL (Phase Locked Loop) circuit for supplying a clock signal to the receiving circuit, a clock signal for receiving input data changing at high speed. The present invention relates to a technique that is effective when applied to a circuit for adjusting the phase.

  As background art of the present invention, FIG. 1 of Patent Document 1 and FIG. 8 of Patent Document 1, which is a known example thereof, show the result of phase comparison between the output of a voltage controlled oscillator (hereinafter referred to as VCO) and a reference clock during coarse adjustment. A clock / data recovery circuit is disclosed that controls the oscillation frequency of the VCO based on the above and controls the oscillation frequency of the VCO based on the phase comparison result between the output of the VCO and the input data during fine adjustment. Further, FIG. 4 and FIG. 7 of Patent Document 1 show a clock that controls the oscillation frequency of the VCO based on the phase comparison result between the output of the VCO and the input data at the time of coarse adjustment and fine adjustment without using the reference clock. A data recovery circuit is disclosed.

  In addition, in FIG. 5.1.2 of lecture number 5.1 published in Non-Patent Document 1 and in FIG. 5.8.1 of lecture number 5.8, the clock signal generated by the PLL is phase-interpolated. A configuration is described in which a phase is adjusted by a modulator (denoted as Phase Interpolator in lecture number 5.8, and denoted as PI in lecture number 5.1) and supplied to a subsequent circuit. According to these configurations, the PLL circuit that generates the clock signal and the interpolator for adjusting the phase of the clock signal to the phase of the input data are independently controlled, so that the PLL circuit is a periodically changing reference signal. Can be used to oscillate stably.

As another background art of the present invention, Patent Document 2 discloses a clock signal with low jitter even when a power supply voltage fluctuates in a PLL circuit including a phase comparator, a frequency comparator, a voltage controlled oscillator, and the like. A circuit configuration of a voltage-controlled oscillator that can generate the above is shown. Specifically, for a configuration including a ring oscillator and a capacitor connected in parallel to each other, and a MOS transistor that controls the oscillation frequency by controlling the power supply voltage (current), depending on the phase comparison result The second means for controlling the oscillation frequency is provided. This second means is realized by a capacity capable of switching connection / disconnection to / from the ring oscillator, and when this capacity is connected according to the phase comparison result, the oscillation frequency becomes slow as the load increases. The opposite is true for connections.
JP 2003-244115 A JP 2001-257567 A Preliminary collection of International Solid-State Circuits Conference, Lecture number 5.1, Lecture number 5.8, held in February 2008

  By the way, as a result of examination by the inventor regarding the background art described above, the following has been clarified.

  For example, in the configuration described in Patent Document 1, since it is assumed that a general PLL circuit that has been conventionally known is used as described in Paragraph 0007 of Patent Document 1, it changes randomly. It is difficult to lock the phase of the output of the VCO to the phase of the input data. In other words, the control based on the phase comparison error caused by noise, etc. prevents the oscillation frequency from changing greatly, and the control is ensured before the phase shift becomes large with respect to the true oscillation frequency change caused by thermal noise, etc. It is difficult to achieve both.

  Further, in the configuration of FIG. 1 and FIG. 8 of Patent Document 1, the control system used at the time of coarse adjustment and the control system used at the time of fine adjustment are separated, so that the design is relatively easy. Since the frequency changes randomly, the period of control during the fine adjustment becomes irregular, and it is difficult to stably operate the conventional PLL circuit design method known in the art. Further, in the configuration of FIG. 1 and FIG. 8 of this Patent Document 1, since the charge pump and the low pass filter for coarse adjustment and fine adjustment are prepared separately, the occupied area of the circuit and the power consumption increase accordingly. 4 and 7 of Patent Document 1 use the same charge pump and low-pass filter at the time of coarse adjustment and fine adjustment, so that it becomes more difficult to set circuit constants.

  The phase interpolator described in Non-Patent Document 1 is a circuit that needs to constantly flow a steady current, and the power consumption increases by using this circuit.

  The PLL circuit described in Patent Document 2 is premised on being drawn into the phase of the reference signal that periodically changes, and there is no description regarding drawing it into the phase of the input data that changes randomly.

  Therefore, the present invention solves the problems of the background art described above, and its main object is to stably obtain a clock signal whose phase is matched to input data. Furthermore, another object is to obtain a clock signal in phase with input data with low power consumption.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The oscillation frequency of the VCO (oscillation circuit), which is a component of the PLL circuit for supplying the clock signal, is controlled based on the phase comparison result between the clock signal and the input data when the input data includes signal information. When there is no signal information, control is performed based on the result of phase comparison between the feedback signal obtained by dividing the clock signal and the reference signal that changes at a constant period.

  Unlike the general VCO, the VCO is configured such that the oscillation frequency can be controlled by two control signals. The oscillation frequency changes gradually and greatly with respect to the change in the control signal of one system, and the oscillation frequency changes immediately and with a small (slightly) change in response to the change in the control signal of the other system. To do.

  When shifting from the state controlled based on the phase comparison result between the feedback signal and the reference signal to the state controlling based on the phase comparison result between the clock signal and the input data, the control using the above two control signals is performed immediately after the transition. Do. When shifting from the state controlled based on the phase comparison result between the clock signal and the input data to the state controlled based on the phase comparison result between the feedback signal and the reference signal, the phase relationship between the feedback signal and the reference signal is immediately after the transition. Until the inversion, the control by the control signal for changing the oscillation frequency gradually and largely is not performed. It should be noted that the control using the control signal for changing the oscillation frequency immediately and small is always performed.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the control for greatly changing the oscillation frequency of the VCO (oscillation circuit) is performed gradually, it is possible to prevent instability due to noise or the like. Since the control for changing the oscillation frequency of the VCO small (slightly) is performed immediately, it can be controlled before the phase shift due to thermal noise or the like becomes large.

  In addition, since a phase interpolator that requires a steady current is unnecessary, power consumption can be reduced.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in principle limited to a specific number in principle, It is not limited to the specific number, and it may be more or less than the specific number.

  Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In each drawing, the names of components, signals, and the like are shown at the end of the names, for example, the first comparison circuit is the comparison circuit 1 and the first phase comparison result signal is the phase comparison result signal 1. 1 may be illustrated, 2 may be illustrated as 2, and 3 may be illustrated as 3.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used as an example of a transistor, and a MOS (Metal Oxide Semiconductor) transistor is used as an example of the transistor. In each drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding a circle symbol to the gate.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a receiving circuit according to Embodiment 1 of the present invention. The receiving circuit illustrated in FIG. 1 includes a PLL unit 10, a delay circuit 60, flip-flop circuits 70 to 73, a second comparison circuit 80, and the like. The subsequent circuit 90 is a circuit that performs desired data processing using the output data from the receiving circuit, the clock signal, and the like, and determines whether or not there is signal information in the output data as necessary and determines the result. Return to this receiving circuit. The PLL unit 10 is a kind of so-called phase-locked loop, and includes a first comparison circuit 20, a control circuit 30, an oscillation circuit 40, a frequency divider circuit 50, and the like. Details thereof will be described later with reference to FIG.

  The delay circuit 60 is a circuit that delays the oscillation output from the PLL unit 10 and outputs four-phase clock signals φ0 to φ3 at substantially equal intervals. The flip-flop circuits 70 to 73 are configured to capture input data in synchronization with the rising edges of the clock signals φ0 to φ3, respectively. Of these, the outputs of the flip-flop circuits 70 and 72 are transmitted to the subsequent circuit 90 as first and second output data, respectively. In the subsequent circuit 90, some of the clock signals φ0 to φ3 (φ0 and φ2 in FIG. 1) are used as clock signals. The second comparison circuit 80 compares the phase relationship between the input data and the clock signal using the outputs of the flip-flop circuits 70 to 73 and the clock signals φ0 and φ2, and outputs the result as a second phase comparison result signal. To do. Furthermore, the second comparison circuit 80 outputs a signal indicating that there is no signal information in the input data to the first signal information presence / absence display signal when the outputs of the flip-flop circuits 70 to 73 do not change for a predetermined time or more. . Thereafter, when signal information appears again in the input data, the subsequent circuit 90 detects this and outputs it to the second signal information presence / absence display signal. Based on these signal information presence / absence display signals, the PLL unit 10 performs control based on the second phase comparison result output from the second comparison circuit 80 when there is signal information in the input data. When there is no signal information, control is performed based on the first phase comparison result output from the first comparison circuit 20 or the like.

  Second comparison circuit 80 is a logic circuit that operates in synchronization with clock signals φ0 and φ2, and the output of flip-flop circuit 71 differs from the outputs of flip-flop circuits 72 and 73 at the timing of the rising edge of clock signal φ0. When the output of the flip-flop circuit 73 is different from the outputs of the flip-flop circuits 70 and 71 at the timing of the rising edge of the clock signal φ2, the signal indicating the phase comparison result that the phase of the clock signal is earlier than the phase of the input data. Output to the second phase comparison result signal. Further, when the output of the flip-flop circuit 73 is different from the outputs of the flip-flop circuits 72 and 71 at the timing of the rising edge of the clock signal φ0, or the output of the flip-flop circuit 71 at the timing of the rising edge of the clock signal φ2. If the output is different from the outputs of 73 and 73, a signal representing a phase comparison result that the phase of the clock signal is slower than the phase of the input data is output to the second phase comparison result signal. When the outputs of the flip-flop circuits 71, 72, 73 are equal at the timing of the rising edge of the clock signal φ0, or when the outputs of the flip-flop circuits 73, 70, 71 are equal at the timing of the rising edge of the clock signal φ2, This means that the input data has not changed. In that case, the second phase comparison result signal is held at the immediately preceding value. When the outputs of flip-flop circuits 70 and 72 are equal and do not change over a predetermined number of cycles, a signal indicating that there is no signal information in the input data is output to the first signal presence / absence display signal.

  Next, the operation of the receiving circuit shown in FIG. 1 will be described. It is assumed that the PLL unit 10 oscillates at a frequency corresponding to one half of the data rate of input data. Then, the input data changes twice at maximum during one cycle of the clock signals φ0 to φ3. At this time, in order for the input data to be stably taken into the flip-flop circuits 70 and 72, it is desirable that the input data changes at the timing of the rising edges of the clock signals φ1 and φ3. This will be described with reference to FIG.

  FIG. 2 is a waveform diagram showing an example of changes in the clock signals φ0 to φ3 and the input data, and the passage of time is shown in the right direction. As shown in this figure, it is desirable that the input data change in a timing relationship almost simultaneously with the rising edge of the clock signal φ1 or φ3. Since the phases of the clock signals φ0 to φ3 are substantially equal, in this state, the clock signals φ0 and φ2 rise at a time away from the timing at which the input data changes. Therefore, the input data is stably taken into the flip-flop circuits 70 and 72 and is alternately transmitted to the subsequent circuit 90 as the first and second output data alternately.

  If the phase of the clock signals φ0 to φ3 is earlier than this, the values immediately before the input data change are taken into the flip-flop circuits 71 and 73, and if the phase of the clock signals φ0 to φ3 is later than the flip-flop circuits 71 and 73, The value immediately after the input data changes is taken into.

  Therefore, when the output of the flip-flop circuit 70 is different from the output of the flip-flop circuit 73 at the timing of the rising edge of the clock signal φ2, the output of the flip-flop circuit 72 is the output of the flip-flop circuit 71 at the timing of the rising edge of the clock signal φ0. Can be determined that the phases of the clock signals φ0 to φ3 are early. On the contrary, when the output of the flip-flop circuit 70 is different from the output of the flip-flop circuit 71 at the timing of the rising edge of the clock signal φ2, or the output of the flip-flop circuit 72 at the timing of the rising edge of the clock signal φ0. If it is different from the output, it can be determined that the phases of the clock signals φ0 to φ3 are slow. Then, by slightly controlling the oscillation frequency of the PLL unit 10 based on the phase comparison result, the timing relationship between the clock signals φ0 to φ3 and the input data can be maintained in the state shown in FIG. Strictly speaking, by reciprocating between a slightly earlier state and a slightly later state than the state shown in FIG. 2, the timing relationship shown in FIG.

  Incidentally, the input data does not necessarily change at the timing of the rising edges of the clock signals φ1 and φ3. When the input data does not change, the outputs of flip-flop circuits 71 and 73 are both equal to the output of flip-flop circuit 70 or 72, and no phase comparison is performed. In that case, the phase comparison result of the previous cycle is held, and when the input data changes thereafter, the phase comparison in the latest state is performed. When the input data changes, normally the outputs of the flip-flop circuits 71 and 73 are different, so that the phase comparison result in the latest state at that time is always obtained.

  If the timing relationship shown in FIG. 2 is close, the outputs of the flip-flop circuits 71 and 73 may be equal even if the input data changes due to variations in circuit characteristics. However, since this is limited to the case where the timing relationship shown in FIG. 2 is close, there is no problem even if any phase comparison result is output.

  Further, in the standard of normal data communication, it is defined that input data always changes within a predetermined number of cycles when signal information is included in the input data. If the input data does not change beyond this predetermined number of cycles, there is no signal information, and the phase comparison result by the second comparison circuit 80 cannot be obtained. In this case, a signal indicating that there is no signal information in the input data is output to the first signal information presence / absence display signal, and the PLL unit 10 is based on a reference signal that changes at a constant period as in a normal PLL. Be controlled. Even in this case, since the delay circuit 60 and the flip-flop circuits 70 to 73 are operating, the input data is not necessarily captured in a stable timing relationship, but the input data is transmitted to the subsequent circuit 90 through the flip-flop circuits 70 and 72. Is done. If the subsequent circuit 90 detects that the signal information appears again in the input data based on the result, a signal indicating this is output to the second signal information presence / absence display signal, and again the second phase. Control based on the comparison result signal is performed to return to the timing relationship shown in FIG.

  Next, the configuration of the PLL unit 10 will be described. FIG. 3 is a block diagram showing a detailed configuration example of the PLL unit 10 according to the first embodiment of the present invention shown in FIG. The PLL unit 10 shown in FIG. 3 includes a first comparison circuit 20, a control circuit 30, an oscillation circuit 40, a frequency divider circuit 50, and the like. The first comparison circuit 20 includes a first phase comparison circuit 21, a frequency comparison circuit 22, an overtaking detection circuit (phase inversion detection circuit) 23, and the like. The control circuit 30 includes a steady state detection circuit 31, a digital control circuit 32, a charge pump control circuit 33, a charge pump circuit 34, a switching circuit 35, and the like.

  The oscillation circuit 40 receives the digital control signal and the analog control signal, and generates an oscillation output whose oscillation frequency is controlled based on the digital control signal and the analog control signal. The frequency dividing circuit 50 divides the oscillation output generated by the oscillation circuit 40 and outputs a feedback signal. The first phase comparison circuit 21 compares the phases of the reference signal and the feedback signal, and uses the first phase comparison result signal as a comparison result as a steady state detection circuit 31, a digital control circuit 32, and a charge pump control circuit 33. Output to. The frequency comparison circuit 22 compares the frequency of the feedback signal with the signal obtained by inverting the reference signal, and outputs two frequency comparison result signals to the charge pump control circuit 33 as a result. The overtaking detection circuit 23 compares the signal obtained by inverting the reference signal with the signal obtained by inverting the feedback signal, and as a result, indicates whether or not phase overtaking has occurred (whether or not the phase relationship has been reversed). The signal is output to the charge pump control circuit 33. Based on the first and second signal information presence / absence display signals output from the second comparison circuit 80 and the subsequent circuit 90, the switching circuit 35 determines whether there is signal information in the input data at that time. The third signal information presence / absence display signal, which is the result of the accurate determination, is output to the digital control circuit 32 and the charge pump control circuit 33. The steady state detection circuit 31 determines whether or not the PLL unit 10 in FIG. 3 has reached a steady state based on the first phase comparison result signal output from the first phase comparison circuit 21 and the determination. The resulting signal is output to the digital control circuit 32 and the charge pump control circuit 33. The digital control circuit 32 includes a third signal information presence / absence display signal output from the switching circuit 35, a signal output from the steady state detection circuit 31, and a first phase comparison result output from the first phase comparison circuit 21. Based on the signal and the second phase comparison result signal output from the second comparison circuit 80, a 3-bit digital control signal for controlling the oscillation circuit 40 is output. The charge pump control circuit 33 is based on the third signal information presence / absence display signal, the first and second phase comparison result signals, the output of the frequency comparison circuit 22, the output of the overtaking detection circuit 23, and the output of the steady state detection circuit 31. In addition, four control signals are output to the charge pump circuit 34. The charge pump circuit 34 receives the four control signals output from the charge pump control circuit 33, and charges and discharges the charge amount corresponding to each of these control signals to the node of the analog control signal. The steady state detection circuit 31, the charge pump control circuit 33, the charge pump circuit 34, and the like operate in synchronization with a signal obtained by inverting the reference signal.

  Next, an outline of a state change of the PLL unit 10 in FIG. 3 from when the power is turned on until the steady state is reached will be described. Immediately after the power is turned on, the switching circuit 35 is reset and the third signal information presence / absence display signal indicates that there is no signal information. Further, the third signal information presence / absence display signal does not change unless the circuit 90 at the subsequent stage outputs a signal indicating that the second signal information presence / absence display signal includes signal information. Therefore, for a while after the power is turned on, the PLL unit 10 in FIG. 3 is controlled based on the output of the first comparison circuit 20.

  For a while after the power is turned on, the voltage of the analog control signal is significantly different from the steady state, so that the oscillation circuit 40 does not oscillate or oscillates at a frequency significantly different from the target oscillation frequency. For this reason, the frequencies of the reference signal and the feedback signal are greatly different. At this time, the frequency comparison circuit 22 and the overtaking detection circuit 23 frequently output signals indicating that the frequencies are different and signals indicating that the phase overtaking has occurred, and the charge pump control circuit 33 controls the charge pump circuit 34 as a frequency. Control based on the output of the comparison circuit 22 becomes dominant. As a result, the frequency of the feedback signal approaches the frequency of the reference signal.

  When the frequency of the feedback signal substantially matches the frequency of the reference signal, the frequency at which the frequency comparison circuit 22 outputs a signal indicating that the frequency is different decreases. Then, the control of the charge pump circuit 34 by the charge pump control circuit 33 is more dominant in the control based on the first phase comparison result signal. Immediately after the transition to this state, the feedback signal and the reference signal are often out of phase even if the frequency is substantially the same, and one phase is earlier than the other and a longer state is a longer time. Continue to repeat the change that the relationship is sometimes reversed. At this time, the first phase comparison result signal takes the same value for a long time and changes occasionally. The PLL unit 10 is provided with a steady state detection circuit 31. If the first phase comparison result signal takes the same value for a predetermined time (for example, a time corresponding to four cycles of the reference signal), the steady state is not reached. The signal which shows that is output. Based on the signal, the digital control circuit 32 changes the digital control signal, which is the output, in accordance with the first phase comparison result signal for all three bits. Then, the oscillation frequency of the oscillation circuit 40 changes greatly according to the digital control signal for 3 bits. Further, the charge pump control circuit 33 outputs a signal for injecting or discharging a small amount of electric charge to the analog control signal in accordance with the first phase comparison result signal, but the output of the steady state detection circuit 31 has reached the steady state. When it indicates that there is no signal, the above signal is output only once every predetermined number of cycles (for example, 8 cycles) of the reference signal, and neither is output in the other cycles. As a result, the voltage of the analog control signal changes only once every predetermined number of cycles of the reference signal, resulting in a slow change. That is, the control range of the oscillation frequency by the digital control signal is large, and the control of the oscillation frequency by the analog control signal is performed little by little. This is a state in which the analog control signal easily converges although the phase jitter increases.

  Even in this case, the first phase comparison result signal changes occasionally, and immediately after that, the steady state detection circuit 31 outputs a signal indicating that the steady state has been reached. However, when the predetermined time elapses, the signal changes to a signal indicating that the steady state has not been reached again. When the analog control signal converges, the frequency at which the first phase comparison result signal changes increases, and the frequency at which the steady state is reached increases. When the first phase comparison result signal always changes within the predetermined time, the steady state detection circuit 31 always outputs a signal indicating that the steady state has been reached.

  When the output of the steady state detection circuit 31 indicates that it has reached a steady state, the digital control circuit 32 changes only one bit of the output in accordance with the first phase comparison result signal, and other bits. Fixes one to a high level and the other to a low level. Then, the oscillation frequency of the oscillation circuit 40 changes small according to one bit of the digital control signal. In addition, the charge pump control circuit 33 outputs a signal for injecting or discharging a small amount of charge to the analog control signal every cycle in accordance with the first phase comparison result signal. As a result, the analog control signal changes so as to reflect all of the first phase comparison result signal. However, since the first phase comparison result signal frequently changes at this time, both a signal for injecting a small amount of charge into the analog control signal and a signal for releasing it are frequently output and cancel each other out. The voltage does not change abruptly. That is, since the control width of the oscillation frequency by the digital control signal is small, the phase jitter is small, and the analog control signal does not change suddenly and is in a stable state. Thereafter, this state continues until it is detected that signal information appears in the input data of FIG.

  When it is detected that signal information appears in the input data, the result is output to the second signal information presence / absence display signal, and the switching circuit 35 changes the third signal information presence / absence display signal. Then, the digital control circuit 32 and the charge pump control circuit 33 start control based on the second phase comparison result signal. After that, the phase relationship between the clock signal and the input data is controlled so as to approach the state shown in FIG. 2, and the frequencies of the feedback signal and the reference signal remain substantially matched but the phases do not necessarily match. Thereafter, when it is detected that there is no signal information in the input data, the result is output to the first signal information presence / absence display signal, and the switching circuit 35 changes the third signal information presence / absence display signal again. Then, the control is again switched to the control based on the first phase comparison result signal, and the frequency and phase of the feedback signal and the reference signal are substantially matched.

  Next, specific configuration examples of each block configuring the PLL unit 10 illustrated in FIG. 3 will be described in order.

  FIG. 4 is a circuit diagram showing a detailed configuration example of the switching circuit 35 in the PLL unit 10 of FIG. The switching circuit 35 shown in FIG. 4 includes NAND circuits ND40 and ND41. A first signal information presence / absence display signal is input to one input node of ND40, and a second signal information presence / absence display signal is input to one input node of ND41. Further, the output node of ND41 is connected to the other input node of ND40, and the output node of ND40 is connected to the other input node of ND41. Further, a reset signal for resetting immediately after the power is turned on is input to another input node of the ND 40.

  The first signal information presence / absence display signal is normally at a high level but is assumed to be at a low level when it is detected that there is no signal information. The second signal information presence / absence display signal is normally at a high level, but is assumed to be at a low level when it is detected that there is signal information. The reset signal is normally at a high level, but is only at a low level when resetting.

  When the first signal information presence / absence display signal becomes a low level indicating that there is no signal information, the switching circuit 35 outputs a low level indicating that there is no signal information as the third signal information presence / absence display signal. Even when the reset signal is set to the low level, the low level is output as the third signal information presence / absence display signal. When the second signal information presence / absence display signal becomes a low level indicating the presence of signal information, a high level indicating the presence of signal information is output as the third signal information presence / absence display signal. When all the inputs are at the high level, the output when any of the inputs finally becomes the low level is held.

  FIG. 5 is a circuit diagram showing a detailed configuration example of the first phase comparison circuit 21 in the PLL unit 10 of FIG. The first phase comparison circuit 21 shown in FIG. 5 includes a set / reset latch circuit SR50, a NAND circuit ND50, a delay circuit DLY50, inverter circuits IV50 and IV51, and a flip-flop circuit FF50. The SR 50 includes two NAND circuits ND51 and ND52. A reference signal is input to one input node of the ND 51, and a feedback signal is input to one input node of the ND 52. Further, the output node of ND52 is connected to the other input node of ND51, and the output node of ND51 is connected to the other input node of ND52.

  In the ND 50, a reference signal is input to one input node, and a feedback signal is input to the other input node. The output of the ND 50 is used for a clock trigger of the FF 50 through a delay circuit DLY50 including a three-stage inverter circuit here. The input data node of FF 50 is connected to the output node of ND 52 via IV 51. The IV 50 connected to the output node of the ND 51 is provided in order to make the load and the balance with respect to the output of the ND 52 equal. The first phase comparison circuit 21 detects which of the rising edge of the reference signal and the rising edge of the feedback signal appears first by the SR 50, captures and holds the detection result in the FF 50, and indicates the comparison result. Output as the first phase comparison result signal.

  FIG. 6 is a circuit diagram showing a detailed configuration example of the frequency comparison circuit 22 in the PLL unit 10 of FIG. The frequency comparison circuit 22 shown in FIG. 6 includes inverter circuits IV60 and IV61, delay circuits DLY60 and DLY61, AND circuits AD60 and AD61, a set / reset latch circuit SR60, inverter circuits IV62 and IV63, flip-flop circuits FF60, It is comprised by FF61. The SR 60 includes two NOR circuits NR60 and NR61. The output signal A0 of the AD60 is input to one input node of the NR60, and the output signal A1 of the AD61 is input to one input node of the NR61. In addition, an output node of NR61 is connected to the other input node of NR60, and an output node of NR60 is connected to the other input node of NR61.

  A signal obtained by inverting the reference signal is input to IV60, and its output is connected to one input node of AD60 and an input node of DLY60. The output of DLY 60 is connected to the other input node of AD 60. With this configuration, a pulse synchronized with the falling edge of the signal obtained by inverting the reference signal is output to the output A0 of the AD60. Similarly, a feedback signal is input to IV61, and its output is connected to one input node of AD61 and an input node of DLY61. The output of DLY61 is connected to the other input node of AD61. With this configuration, a pulse synchronized with the falling edge of the feedback signal is output to the output A1 of the AD61.

  Since A0 and A1 are input to the set / reset latch circuit SR60, after both pulses output to A0 and A1 have disappeared, it is determined in SR60 which pulse of A0 and A1 has disappeared first. I remember it. The information is input to input data terminals B0 and B1 of FF60 and FF61 via IV62 and IV63. Then, when the next pulse appears on the side where the pulse disappeared first, the FF 60 or FF 61 outputs a low level to the frequency comparison result signal R or the frequency comparison result signal F, and pulses alternately appear on A0 and A1. You can recognize it. When the next pulse appears on the side where the pulse disappears later, the FF 60 or FF 61 outputs a high level to the frequency comparison result signal R or the frequency comparison result signal F, and the pulse on that side continues two or more times continuously. You can recognize it. Therefore, the frequency comparison circuit 22 detects whether the falling edge of the signal obtained by inverting the reference signal, that is, whether the rising edge of the reference signal and the falling edge of the feedback signal appear alternately. If they appear alternately, a low level is output to the frequency comparison result signal R and the frequency comparison result signal F indicating the detection results, and if either one appears more than once, that side A high level is output to the frequency comparison result signal R or the frequency comparison result signal F.

  In the steady state, the PLL unit 10 in FIG. 3 controls the reference signal and the feedback signal so that the frequencies and phases of the reference signal and the feedback signal substantially coincide with each other so that both rising edges are substantially at the same time. Falling edges appear alternately, and a low level is always output to the frequency comparison result signal R and the frequency comparison result signal F.

  In the PLL unit 10 of FIG. 3, the overtaking detection circuit 23 has a half-rotation of the phase difference between the reference signal and the feedback signal after the frequency comparison circuit 22 outputs a high level to the frequency comparison result signal R or the frequency comparison result signal F. This is a circuit provided for detecting that a phase overtaking occurs between the rising edges. This circuit is a circuit having the same configuration as the frequency comparison circuit 22 except that the feedback signal is inverted and input, and detects whether the rising edges of the reference signal and the feedback signal appear alternately. When appearing alternately, the two output signals are both set to a low level, and when one of them appears two or more times continuously, it acts as a circuit for setting the output signal on that side to a high level.

  As the frequencies of the reference signal and the feedback signal approach, the change in the phase difference from the feedback signal per cycle of the reference signal becomes smaller. Here, when either the rising edge of the reference signal or the falling edge of the feedback signal appears twice consecutively, the phase is shifted by almost a half cycle, and the phase on the higher frequency side for a while thereafter. Is delayed. If the charge pump circuit 34 is controlled based on the first phase comparison result signal in this state, control opposite to that desired is applied. To avoid this is the first purpose of providing the overtaking detection circuit 23. When one of the rising edges of the reference signal and the feedback signal appears twice in succession, the phase is almost the same. After that, the rising edge of the reference signal and the falling edge of the feedback signal are next. The phase on the higher frequency side advances until one of them appears twice in succession. If the charge pump circuit 34 is controlled based on the first phase comparison result signal in this state, desired control is applied. Therefore, after any of the outputs of the frequency comparison circuit 22 becomes high level, the control of the charge pump circuit 34 based on the first phase comparison result signal is stopped, and any of the outputs of the overtaking detection circuit 23 is high level. It may be resumed after becoming.

  Further, when the frequencies of the reference signal and the feedback signal become closer, the change in the phase difference from the feedback signal per cycle of the reference signal is further reduced, and the frequency comparison circuit 22 causes the frequency comparison result even if each edge appears alternately. An erroneous detection that outputs a high level to the signal R or the frequency comparison result signal F may occur. The second purpose of providing the overtaking detection circuit 23 is to prevent the influence of this erroneous detection. This erroneous detection occurs when the rising edge of the reference signal and the falling edge of the feedback signal appear at almost the same time, and it occurs continuously for several cycles before and after one cycle in which correct detection is performed. . In the erroneous detection that appears in the first cycle, since the signal on the higher frequency side appears later, the same signal as the correct detection is output as a result. In addition, the reference signal and the feedback are provided between the occurrence of an erroneous detection in a series of cycles including correct detection of one cycle and the occurrence of an erroneous detection in a series of cycles including correct detection of one cycle. The signal phase difference rotates once. Then, at the time of about half rotation during that time, the overtaking detection circuit 23 outputs a high level to any output signal. Therefore, after controlling the charge pump circuit 34 based on the output of the frequency comparison circuit 22, the charge pump circuit based on the output of the frequency comparison circuit 22 until the overtaking detection circuit 23 next sets any output to a high level. It is sufficient that the control 34 is not performed. Thereby, the influence of the erroneous detection of the frequency comparison circuit 22 can be avoided.

  FIG. 7 is a circuit diagram showing a detailed configuration example of the steady state detection circuit 31 in the PLL unit 10 of FIG. The steady state detection circuit 31 shown in FIG. 7 measures a phase inversion detection portion for detecting that the first phase comparison result signal has changed, and an elapsed time after the first phase comparison result signal has changed, to determine a predetermined value. Consists of a timer portion that detects that time has elapsed. Each part includes an inverter circuit IV70, flip-flop circuits FF70 to FF72, OR-NAND composite circuits RD70 and RD71, and NAND circuits ND70 to ND74. The flip-flop circuit FF70 stores the first phase comparison result signal of the previous cycle, and the phase inversion detection part compares the current first phase comparison result signal with the first phase comparison result signal of the previous cycle. When the two are different, it is determined that the first phase comparison result signal has changed, and a signal indicating this is output to the timer portion. The timer part is constituted by a 2-bit counter constituted by flip-flop circuits FF71 and FF72. This 2-bit counter counts the number of pulses of the signal obtained by inverting the reference signal, but when it detects that the first phase comparison result signal has changed, the count value is reset to 0 in the next cycle. While the first phase comparison result signal does not change, the count value advances by one count. When the count value reaches 3, a low level is output to the steady state detection result signal, and thereafter the count value is fixed. That is, the steady state detection circuit 31 outputs a low level to the steady state detection result signal when the first phase comparison result signal has not changed over four cycles or more, and the first phase comparison result signal is 3 When it changes within a cycle, it acts as a circuit that outputs a high level to the steady state detection result signal.

  FIG. 8 is a circuit diagram showing a detailed configuration example of the digital control circuit 32 in the PLL unit 10 of FIG. The digital control circuit 32 shown in FIG. 8 includes inverter circuits IV80 to IV82, NAND circuits ND80 to ND83, and a NOR circuit NR80.

  The digital control circuit 32 shown in FIG. 8 is affected by the second phase comparison result signal when the third signal information presence / absence display signal indicates a low level, that is, there is no signal information in the input data of FIG. First, each bit of the digital control signal is determined only by the first phase comparison result signal and the steady state detection result signal. When the steady state detection result signal is at a low level, that is, not in a steady state, the same signal as the first phase comparison result signal is output for all three bits of the digital control signal. When the steady state detection result signal indicates a high level, that is, in a steady state, the same signal as the first phase comparison result signal is output to only one bit of the digital control signal, and the other two bits Output low level and high level respectively.

  When the third signal information presence / absence display signal is at a high level, that is, when the input data in FIG. 1 has signal information, the first phase comparison result signal and the steady state detection result signal are not affected. The digital control signal is determined only by the two phase comparison result signals. At this time, the same signal as the second phase comparison result signal is output to only one bit of the digital control signal, and the low level and the high level are output to the other two bits, respectively.

  FIG. 9 is a circuit diagram showing a detailed configuration example of the charge pump control circuit 33 in the PLL unit 10 of FIG. The charge pump control circuit 33 shown in FIG. 9 includes a counter circuit CNT90, inverter circuits IV90 to IV98, NAND circuits ND90 to ND93, NOR circuits NR90 to NR94, AND circuit AD90, and AND-NOR composite circuits DR90 to DR91. And flip-flop circuits FF90 to FF95 and a set / reset latch circuit SR90. The counter circuit CNT90 is a circuit that counts the number of pulses of a signal obtained by inverting the reference signal. The counter circuit CNT90 is reset to 0 at the next pulse that has reached the maximum count value, and further repeats the counting operation. Here, a case where a 3-bit counter is used and reset every 8 counts will be described as an example. The set / reset latch circuit SR90 includes NOR circuits NR95 and NR96. The output of the NOR circuit NR96 is connected to one input of the NOR circuit NR95, and the output of the NOR circuit NR95 is connected to one input of the NOR circuit NR96. The other input of the NOR circuit NR95 is connected with a third signal information presence / absence display signal, a control signal for greatly increasing the oscillation frequency, and a control signal for greatly decreasing the oscillation frequency. The output of the overtaking detection circuit 23 is connected to the other input of the NOR circuit NR96.

  When the third signal information presence / absence display signal indicates a low level, that is, there is no signal information in the input data in FIG. 1, the output of the charge pump control circuit 33 in FIG. 9 affects the influence of the second phase comparison result signal. Instead, it is determined by the first phase comparison result signal, the steady state detection result signal, and the frequency comparison result signal. After any of the control signals that greatly increase or decrease the oscillation frequency is set to the high level, the internal signal ENBL1 is set to the low level thereafter until any of the outputs of the overtaking detection circuit 23 becomes the high level. In the meantime, all four outputs are fixed at a low level. When any of the outputs of the overtaking detection circuit 23 becomes high level, the internal signal ENBL1 is set to high level. Here, if the steady state detection result signal is at a high level, the internal signal ENBL2 is always at a low level, and either a control signal for decreasing the oscillation frequency or a control signal for decreasing the oscillation frequency based on the first phase comparison result signal is output. Cycle output. If the steady state detection result signal is low level, the internal signal ENBL2 becomes low level every 8 cycles of the reference signal, and a control signal for increasing or decreasing the oscillation frequency based on the first phase comparison result signal. Either one is output every 8 cycles. When either the frequency comparison result signal R or the frequency comparison result signal F becomes high level, either the control signal for greatly increasing the oscillation frequency or the control signal for greatly decreasing the oscillation frequency is set to high level. Then, the internal signal ENBL1 is set to the low level until any of the outputs of the overtaking detection circuit 23 becomes the high level thereafter, and all four outputs are fixed to the low level during that time. Therefore, only the frequency comparison result signal that appears first after the output of the overtaking detection circuit 23 becomes high level is reflected in the control signal that greatly increases or decreases the oscillation frequency. The part constituted by the flip-flop circuits FF90 and FF91, the NOR circuits NR91 and NR92, and the inverter circuits IV94 and IV95 extends the pulse width of the frequency comparison result signal R and the frequency comparison result signal F by one cycle of the reference signal to oscillate. It is provided in order to ensure that a control signal for greatly increasing or decreasing the frequency is output.

  When the third signal information presence / absence display signal indicates a high level, that is, the input data in FIG. 1 has signal information, the output of the charge pump control circuit 33 in FIG. 9 is influenced by the first phase comparison result signal and the like. And is determined only by the second phase comparison result signal. In this case, control is performed once every 8 cycles of the reference signal. That is, the frequency of control of the charge pump circuit 34 based on the second phase comparison result signal is lower than the frequency of control of the charge pump circuit 34 based on the first phase comparison result signal in the steady state. When the input data does not change, the value of the previous cycle is held in the second phase comparison result signal. Therefore, if the charge pump circuit 34 is controlled frequently, excessive control may be applied. Therefore, the frequency of control is reduced to prevent the oscillation frequency from becoming unstable. When it is necessary to change the frequency of control based on the second phase comparison result signal and the frequency of control based on the first phase comparison result signal when not in a steady state, the counter circuits CNT90 having different numbers of bits are used. AD90 will be prepared.

  When the third signal information presence / absence display signal is at a high level, the internal signal ENBL1 is set at a low level. Therefore, even if the third signal information presence / absence display signal thereafter becomes low level, control by the first phase comparison result signal or the like is not started until one of the outputs of the overtaking detection circuit 23 thereafter becomes high level. This is because the reference signal and the feedback signal are not always in phase with each other immediately after the third signal information presence / absence display signal becomes low level, so that the reverse control of the desired signal is prevented. This is a function provided in. Immediately after one of the outputs of the overtaking detection circuit 23 becomes high level, the phase of the reference signal and the feedback signal substantially coincide with each other, and control by the first phase comparison result signal or the like is started from this point. When the third signal information presence / absence display signal changes from the low level to the high level, there is no particular problem even if the control by the second phase comparison result signal is started immediately after the change.

  FIG. 10 is a circuit diagram showing a detailed configuration example of the charge pump circuit 34 in the PLL unit 10 of FIG. The charge pump circuit 34 of FIG. 10 includes PMOS transistors Tp100 to Tp102 and NMOS transistors Tn102 to Tn100 between the high potential side power supply Vdd and the low potential side power supply Vss. Here, the first analog control signal is output from the output node corresponding to the drains of Tp102 and Tn102.

  A PMOS transistor Tp103 is connected between the output node of the second analog control signal and Vdd, and two NMOS transistors Tn103 and Tn104 are connected in parallel between the output node of the second analog control signal and Vss. Connected to. The first pulse signal PLS1 (normal rotation signal via the inverter circuits IV105 and 106) is input to the gate of Tp101. The first pulse signal PLS1 (inverted signal through the inverter circuit IV107) is input to the gate of Tn101. On the other hand, the second pulse signal PLS2 (normal rotation signal through the inverter circuits IV103 and 104) is input to the gate of Tp100. The second pulse signal PLS2 (inverted signal through the inverter circuit IV108) is input to the gate of Tn100.

  The PLS1 is a signal obtained by delaying a signal obtained by inverting the reference signal by a delay circuit DLY100 constituted by a two-stage inverter circuit, and further inverted by a delay circuit DLY101 constituted by a four-stage inverter circuit and an inverter circuit IV102. The delayed signal is generated by calculating with the NAND circuit ND102. In this case, PLS1 is a low pulse signal having a pulse width corresponding to five stages of inverter circuits. The PLS2 calculates the output of the delay circuit DLY100 and the signal inverted and delayed by the delay circuit DLY101 constituted by a four-stage inverter circuit and the delay circuit DLY102 constituted by the three-stage inverter circuit by the NAND circuit ND103. Further, the output is generated by inverting and delaying the output by a delay circuit DLY103 constituted by, for example, a three-stage inverter circuit. In this case, PLS2 becomes a high pulse signal having a pulse width equivalent to seven stages of inverter circuits, and becomes a pulse signal that rises after the delay time of DLY103 from the fall of PLS1. That is, the delay time of the DLY 103 is a time during which a current flows between Vdd and the output node of the first analog control signal or between the output node of the first analog control signal and Vss.

  A result obtained by operating the signal obtained by inverting the oscillation stop signal via the inverter circuit IV100 and a control signal for slightly increasing the oscillation frequency by the NAND circuit ND101 is input to the gate of Tp102, and the oscillation frequency is input to the gate of Tn102. A control signal that is slightly lowered is input. Therefore, Tp102 is turned on when the oscillation stop signal is at a low level (inactive) and the control signal for slightly increasing the oscillation frequency is at a high level. On the other hand, Tn102 is turned on when the control signal for slightly lowering the oscillation frequency becomes high level. When one of Tp102 and Tn102 is turned on, a current having a very short time width corresponding to the delay time of DLY103 is output to the terminal of the first analog control signal.

  A result obtained by calculating a signal obtained by inverting the oscillation stop signal and a control signal for greatly increasing the oscillation frequency by the NAND circuit ND100 is input to the gate of Tp103, and a control signal for greatly decreasing the oscillation frequency is input to the gate of Tn103. The Therefore, Tp103 is turned on when the oscillation stop signal is at the low level (inactive) and the control signal for greatly increasing the oscillation frequency is at the high level. On the other hand, Tn103 is turned on when the control signal for greatly reducing the oscillation frequency becomes high level. When Tp103 or Tn103 is turned on, a current having a time width corresponding to the pulse width of the control signal (that is, one cycle of the reference signal) that greatly increases or decreases the oscillation frequency is output to the terminal of the second analog control signal. Will be. Since this time is considerably longer than the delay time of the DLY 103, the control width by the control signal that greatly increases and decreases the oscillation frequency is considerably larger than the control width by the control signal that slightly increases and decreases the oscillation frequency.

  Note that the oscillation stop signal is provided to stop the oscillation of the oscillation circuit by using the second analog control signal as the low potential side power source Vss, for example, at the time of testing or the like. When the oscillation stop signal becomes a high level, Tp102 and Tp103 are driven off via ND100 and ND101, and Tn104 is driven on via inverter circuits IV100 and 101, so that the second analog A control signal is connected to Vss. Further, the first and second analog control signals are separated to reduce the parasitic capacitance attached to the node of the first analog control signal, but are connected to each other through a resistor in the oscillation circuit 40. .

  FIG. 11 is a circuit diagram showing a detailed configuration example of the oscillation circuit 40 in the PLL unit 10 of FIG. The oscillation circuit 40 of FIG. 11 includes a digital controller portion, a ring oscillator portion, a buffer portion, a level shifter portion, and an analog controller portion. The ring oscillator part is configured by odd-numbered (in this case, five stages) CMOS inverter circuits IV110 to IV114 connected between the high-potential-side power supply node Vdd and the second low-potential-side power supply node Vss2. The output node of IV 114 at the fifth stage is fed back to the input node of IV 110 at the first stage via resistors R4 and R5 connected in series, and oscillation operation is performed by this ring structure.

  The digital controller portion of the oscillation circuit 40 of FIG. 11 is configured by PMOS transistors Tp110 to Tp112 that are provided in parallel with the resistors R4 and R5 and each bit of the digital control signal is connected to the gate electrode. However, Tp110 is provided in parallel with only R4, whereas Tp111 and Tp112 are both provided in parallel with both R4 and R5. When all of the PMOS transistors Tp110 to Tp112 are in the cut-off state, the output node of the IV114 and the input node of the IV110 are connected with the resistance value of the sum of the resistors R4 and R5, but some of the PMOS transistors Tp110 to Tp112 are connected. When the conductive state is established, the portion corresponding to the resistance value of the PMOS transistor is connected in parallel, the resistance value of the feedback circuit is lowered, and the oscillation frequency is increased. The change in the oscillation frequency due to this is the control width by the digital control signal. When the digital control signal is changed simultaneously for all three bits, the control range of the oscillation frequency is increased because the conduction state or the cutoff state of Tp110 to Tp112 is controlled simultaneously. When only one bit of the digital control signal changes and the other bits are fixed at a low level and a high level, the oscillation frequency is controlled by one PMOS transistor, and the control width is small. Become. In particular, if one of them becomes Tp110, the change width of the resistance value of the feedback circuit can be reduced, and the control width of the oscillation frequency can be reduced. As a result, even if Tp110 to Tp112 are all designed to be the same size, which is the minimum size that can be created by semiconductor technology, the control width of the oscillation frequency when only one bit of the digital control signal is changed is 3 bits. Both can be made smaller than one third of the control width of the oscillation frequency when they are changed simultaneously.

  The buffer portion is composed of, for example, four-stage CMOS inverter circuits IV115 to IV118 connected between Vdd and Vss2, and the output node (IV110 to 114) of the ring oscillator portion is connected to the input node of IV115 as the first stage. Output node). The output node of IV115 is connected to the input nodes of IV116 and IV117, and the output node of IV117 is connected to the input node of IV118. The output nodes of IV116 and IV118 are connected to the level shifter portion as the output of the buffer portion. This buffer portion is provided to reduce the load on the output node of the ring oscillator portion.

  The level shifter portion is connected between Vdd and the first low potential side power supply node Vss, for example, a differential amplifier circuit composed of PMOS transistors Tp115 and Tp116 and NMOS transistors Tn111 and Tn112, and two stages connected to the output node. CMOS inverter circuits IV11a and IV11b. Tp115 and Tp116 operate as a differential pair. The gate of Tp115 is connected to the output node of IV116 in the buffer portion, and the gate of Tp116 is connected to the output node of IV118 in the buffer portion. Tn111 and Tn112 constitute a current mirror circuit and are connected to the drains of Tp115 and Tp116, respectively, thereby functioning as a load current source of the differential amplifier circuit. The drain of Tp116 is connected to the input node of the first-stage CMOS inverter circuit IV11a, and an oscillation output is obtained from the second-stage CMOS inverter circuit IV11b.

  This level shifter portion is provided to convert an oscillation signal that swings between Vdd and Vss2 into an oscillation signal that swings with the full amplitude between Vdd and Vss. In addition to the above configuration, the level shifter portion of FIG. 11 further includes PMOS transistors Tp113 and Tp114, an NMOS transistor Tn113, and an inverter circuit IV119 for receiving an oscillation stop signal and fixing the oscillation output to a low level. ing. When the oscillation stop signal becomes a high level, a low level is applied to the gates of Tp113 and Tp114 via IV119, and Vdd is applied to the gates of Tp115 and Tp116 via this turned on Tp113 and Tp114. The Further, the high level of the oscillation stop signal is also applied to the gate of Tn113, and the input node of IV11a is fixed to the low level via this turned on Tn113.

  The analog controller portion is configured to include a resistor R3 in addition to the NMOS transistor Tn110 and the low-pass filter composed of resistors R1, R2 and a capacitor C2 connected to the gate of Tn110. Tn110 has a drain connected to Vss2 and a source connected to Vss via a resistor R3. In addition, an analog control signal is input to the gate of Tn110 via the low-pass filter described above. One of the analog control signals is input via the resistor R1, and the other is input via the resistor R2. A signal input from any terminal charges and discharges the capacitor C2 and gradually changes the voltage applied to the gate of Tn110. The resistor R3 is provided in order to suppress fluctuation of the current flowing through the Tn 110 when voltage fluctuation occurs between Vss2 and Vss.

  The above is the detail of each element which comprises the PLL part 10 of FIG. Note that the frequency dividing circuit 50 constituting the PLL unit 10 in FIG. 3 is a normal frequency dividing circuit that divides the oscillation output by a predetermined frequency dividing ratio, and therefore description thereof is omitted.

  FIG. 12 is a circuit diagram showing a detailed configuration example of the delay circuit 60 in the receiving circuit of FIG. The delay circuit 60 in FIG. 12 includes inverter circuits DC120 to DC129 that can control the delay time, normal inverter circuits IV120 to IV12g, a set / reset latch circuit SR120, and a high-potential-side power supply Vdd and a low-potential-side power supply Vss. PMOS transistors Tp120, Tp121 and NMOS transistors Tn121, Tn120, and a low-pass filter including a resistor R6 and a capacitor C3. The SR 120 includes NAND circuits ND120 and ND121.

  The oscillation output from the PLL unit 10 is connected to the input terminal of the DC 120, and the DC 120 to DC 129 are connected to their respective outputs and inputs sequentially. A common control signal CNTL is connected to terminals for controlling the delay times of DC120 to DC129. DC120 to DC128 have the same load, and their delay times are substantially matched. The input terminals of IV120 to IV123 are connected to the even-numbered connection points of DC120 to DC129, respectively, and clock signals φ0 to φ3 are output from the output terminals of IV120 to IV123. Input terminals of IV124 to IV128 are connected to odd-numbered connection points of DC120 to DC129, respectively. Here, control is performed using the control signal CNTL so that the phases of the output waveforms of the IV 124 and the IV 128 substantially coincide with each other. Then, since the delay time of eight stages of DC121 to DC128 substantially coincides with the cycle of the oscillation output, the clock signals φ0 to φ3 having a delay time difference of two stages of DC122 to DC127 are substantially equal intervals of four-phase clocks. Become.

  In order to match the phases of the output waveforms of IV124 and IV128, the following connections are made. The outputs of IV124 and IV128 are connected to one input of each of ND120 and ND121, and the output of ND121 and ND120 are connected to the other input of each of ND120 and ND121. Further, the outputs of ND120 and ND121 are connected to the gates of Tp120 and Tn120 via a desired number of inverters so that Tp120 is conductive when the output of ND120 is low and Tn120 is conductive when the output of ND121 is low. To. Furthermore, the outputs of IV124 and IV128 are connected to the gates of Tn121 and Tp121 via inverters of a desired number of stages so that Tn121 is conductive when the output of IV124 is high and Tp121 is conductive when the output of IV128 is high. To. Further, the connection point between the drains of Tp121 and Tn121 is connected to the control signal CNTL via a low-pass filter composed of a resistor R6 and a capacitor C3.

  Then, when the phase of the output waveform of IV128 is earlier than the phase of the output waveform of IV124, ND121 outputs a low level and Tn120 conducts for about half a cycle from the rise of the output waveform of IV128. Shortly thereafter, the output waveform of the IV 124 rises and makes the Tn 121 conductive, so that the voltage of the control signal CNTL decreases slightly and the delay time of DC120 to DC129 increases slightly. During this time, the output of the ND 120 remains at a high level and the Tp 120 remains cut off. As a result, the phase of the output waveform of IV128 slightly approaches the phase of the output waveform of IV124. Conversely, when the phase of the output waveform of IV128 is later than the phase of the output waveform of IV124, ND120 outputs a low level and Tp120 conducts for about half a cycle from the rise of the output waveform of IV124. Shortly thereafter, the output waveform of IV128 rises to make Tp121 conductive, so that the voltage of the control signal CNTL rises slightly and the delay time of DC120 to DC129 is slightly reduced. During this time, the output of the ND 121 remains at a high level and Tn 120 remains cut off. As a result, the phase of the output waveform of IV128 advances slightly and approaches the phase of the output waveform of IV124. As a result, control is performed so that the phases of the output waveforms of IV124 and IV128 substantially coincide.

  FIG. 13 is a circuit diagram showing a detailed configuration example of one of the inverter circuits DC120 to DC129 (for example, DC120) capable of controlling the delay time in the delay circuit 60 of FIG. The inverter circuit DC120 of FIG. 13 includes a PMOS transistor Tp130 and NMOS transistors Tn130 and Tn131 connected between the high potential side power supply Vdd and the low potential side power supply Vss, and an NMOS transistor Tn132 connected in parallel to the NMOS transistor Tn131. Is done. Tp130 and Tn130 constitute an inverter. While Vdd is connected to the gate electrode of Tn131, the control signal CNTL is connected to the gate electrode of Tn132. Therefore, the delay time can be controlled by controlling the current flowing through the inverter constituted by Tp130 and Tn130 by the voltage of the control signal CNTL.

  FIG. 14 is a circuit diagram showing a detailed configuration example of the second comparison circuit 80 in the receiving circuit of FIG. The second comparison circuit 80 includes a second phase comparison circuit 81 that compares the phases of the clock signal and the input data, and a portion that detects that there is no signal information in the input data. The portion that detects that there is no signal information in the input data is configured by an exclusive OR circuit XR140, a counter circuit CNT140, and a NAND circuit ND140. The second phase comparison circuit 81 includes exclusive OR circuits XR141 to XR144, flip-flop circuits FF140 to FF143, NAND circuits ND141 to ND144, and a set / reset latch circuit SR140. The set / reset latch circuit SR140 includes NAND circuits ND145 and ND146.

  The counter circuit CNT140, which is a component of the second comparison circuit 80, will be described here as an 8-bit counter. This counter is incremented every time a clock pulse is received while the reset signal is at a low level. When the count value reaches 255, that is, full count, it is reset at the next clock pulse and starts counting again. . Further, when the reset signal becomes high level, it is reset at that moment, and after the reset signal becomes low level, counting is newly started. Then, since the XR 140 outputs a low level when the outputs of the flip-flop circuits 70 and 72 are equal, the count value increases every cycle of the clock signal φ2. If the input data does not change over 255 cycles, the XR 140 continues to output a low level during that period, so that the count value reaches a full count, and a low level is output to the first signal information presence / absence display signal. If the input data changes even once before that, the XR 140 outputs a high level at the moment when the flip-flop circuit 70 or 72 takes in the signal, the counter is reset, and counting starts again from 0. That is, when the input data changes within a predetermined time, the first signal information presence / absence display signal is fixed at a high level, and when the input data does not change over a predetermined time, the first signal information presence / absence display signal is low. Can be configured to output levels.

  Further, the second phase comparison circuit 81 sets the output of the XR 141 to the high level when the output of the flip-flop circuit 73 is different from the output of the flip-flop circuit 70, and the output of the flip-flop circuit 71 becomes the output of the flip-flop circuit 70. If they are different, the output of the XR 142 is set to the high level. The result is taken into the FF 140 and FF 141 in synchronization with the rising edge of the clock signal φ2, and further transmitted to the SR 140 while the clock signal φ2 is at the high level. Since the clock signal φ0 is at the low level while the clock signal φ2 is at the high level, the outputs of the ND143 and ND144 are at the high level during this period. As a result, if the output of the flip-flop circuit 73 is different from the output of the flip-flop circuit 70, the second phase comparison result signal outputs a high level indicating the phase comparison result that the phase of the clock signal is earlier than the phase of the input data. Is done. If the output of the flip-flop circuit 71 is different from the output of the flip-flop circuit 70, a low level representing the phase comparison result that the phase of the clock signal is slower than the phase of the input data is output to the second phase comparison result signal. When the outputs of the flip-flop circuits 73, 70, 71 are all equal, the immediately preceding second phase comparison result signal is held as it is. Similarly, the comparison results of the outputs of flip-flop circuits 71, 72, and 73 by XR143 and XR144 are transmitted to SR140 in synchronization with the rising edge of clock signal φ0, and the result is reflected in the second phase comparison result signal. .

  As described above, by using the receiving circuit according to the first embodiment, it is possible to stably obtain a clock signal whose phase is matched to input data. That is, since the control for greatly changing the oscillation frequency of the oscillation circuit 40 is performed gradually, it is possible to prevent instability due to noise or the like. Furthermore, since the control for changing the oscillation frequency of the oscillation circuit 40 to be small (slightly) is performed immediately, it can be controlled before the phase shift due to thermal noise or the like becomes large.

  Further, since the PLL unit 10 used in the receiving circuit of the first embodiment does not include a circuit that requires particularly large power consumption compared to a normal PLL circuit, a clock signal whose phase is matched to input data is reduced. It can be obtained with power consumption. That is, since a phase interpolator that requires a steady current is not necessary, power consumption can be reduced.

(Embodiment 2)
In the first embodiment described above, the configuration in the case where the threshold values of the flip-flop circuits 70 to 73 are fixed has been described. In the second embodiment, a configuration in which the threshold value of the flip-flop circuit is variable will be described.

  In the cycle immediately after the input data changes from the low level to the high level, the voltage of the node of the input data may be lower than in the case where the input data is also the high level in the previous cycle. Similarly, in the cycle immediately after the input data changes from the high level to the low level, the voltage at the node of the input data may be higher than in the previous cycle when the input data is at the low level. This is a phenomenon that occurs because the time for charging / discharging the voltage of the node of the input data is insufficient in the time corresponding to the data rate, and charging / discharging is not in time in the cycle immediately after the change. When this input data is taken into the flip-flop circuits 70 to 73 with a fixed threshold value, when the data rate is high, the charge / discharge time is insufficient in the cycle immediately after the change, and erroneous data may be taken in. The second embodiment is configured to improve this. When the input data of the previous cycle is low level, the threshold value of the flip-flop circuit is lowered, and the input data of the previous cycle is high. If it is at the level, the threshold value of the flip-flop circuit is increased.

  FIG. 15 is a circuit diagram showing a configuration example of a flip-flop group 70 ′ provided in place of the flip-flop circuits 70 to 73 in the second embodiment. The circuit of the flip-flop group 70 'is configured by inverter circuits IV150 and IV151 having different threshold values, flip-flop circuits FF150 to FF157, and selector circuits SL150 to SL155.

  The inverter circuits IV150 and IV151 have different threshold values by changing the balance of the sizes of the PMOS transistor and the NMOS transistor constituting the inverter circuits IV150 and IV151. By adding the outputs to the odd-numbered and even-numbered FF150 to FF157, respectively, the odd-numbered and even-numbered FF150 to FF157 have different thresholds with respect to the input data. This is taken into each flip-flop circuit in synchronization with the clock signals φ0 to φ3, respectively. Then, when the data is fetched into the FF 150 and FF 151 in synchronization with the clock signal φ0, the input data of the immediately preceding cycle is stored in the FF 154 or FF 155 which is fetched in synchronization with the clock signal φ2. Therefore, the selector circuit SL150 selects the output of either FF150 or FF151 using the information, and outputs the selected signal S-100 in synchronization with the clock signal φ0 of that cycle. Similarly, the selector circuit SL153 selects the output of the FF 154 and FF 155 fetched in synchronization with the clock signal φ2 by using the signal S-100 which is input data of the immediately preceding cycle, and is synchronized with the clock signal φ2 of the cycle. The signal S-102 taken in is output.

  When the signal acquired in synchronization with the clock signals φ1 and φ3 is used for comparison with the signal S-100 acquired in synchronization with the clock signal φ0, the signal S-102 acquired in synchronization with the clock signal φ2 is used. Use to select and output as S-1010 and S-1030. When used for comparison with the signal S-102 captured in synchronization with the clock signal φ2, the signal S-100 captured in synchronization with the clock signal φ0 is selected and output as S-1012 and S-1032. To do.

  FIG. 16 is a circuit diagram showing a configuration example of the second comparison circuit 80 'used in the second embodiment. The second comparison circuit 80 'has substantially the same configuration as the second comparison circuit 80 shown in FIG. 14, but the signals input to the exclusive OR circuits XR141 to XR144 are fed to the flip-flop group 70 shown in FIG. The signal is changed to the output signal.

  As described above, by using the receiving circuit of the second embodiment, it is possible to obtain the same effect as that of the first embodiment described above, and further change the threshold value of the flip-flop circuit according to the input data in the immediately preceding cycle. However, the present invention can also be applied to a case where the data rate is higher than that of the receiving circuit shown in the first embodiment.

(Other embodiments)
In the first and second embodiments described above, the case where the four-phase clocks φ0 to φ3 having a frequency corresponding to one half of the data rate of the input data is used has been described, but this corresponds to one third of the data rate. Use a 6-phase clock with a frequency, use an 8-phase clock with a frequency corresponding to ¼ of the data rate, or a 2 × N-phase clock with a frequency generally corresponding to 1 / N of the data rate. Can also be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiments, a MOS transistor is used as a transistor, but it is of course possible to replace it with a bipolar transistor. In FIG. 11 and the like, a transistor is provided on the low potential power supply side and the oscillation frequency is controlled by the gate potential. Similarly, a transistor is provided on the high potential power supply side and the oscillation frequency is controlled by the gate potential. It is also possible.

  The receiving circuit of the present invention is a technique that is particularly useful when applied to a high-speed signal receiving circuit and a clock signal supply unit in a semiconductor integrated circuit device, and is not limited to this, and receives a high-speed or high-accuracy signal or a clock signal. It can be widely applied to various integrated circuit devices that are required to be supplied.

It is a block diagram which shows the structural example of the receiving circuit by Embodiment 1 of this invention. FIG. 2 is a waveform diagram showing an example of operation waveforms of main signals of the receiving circuit of FIG. 1. FIG. 2 is a block diagram illustrating a detailed configuration example of the PLL unit in the receiving circuit of FIG. 1. FIG. 4 is a circuit diagram illustrating a detailed configuration example of the switching circuit in the PLL unit of FIG. 3. FIG. 4 is a circuit diagram showing a detailed configuration example of the first phase comparison circuit in the PLL section of FIG. 3. FIG. 4 is a circuit diagram illustrating a detailed configuration example of the frequency comparison circuit in the PLL unit of FIG. 3. FIG. 4 is a circuit diagram illustrating a detailed configuration example of a steady state detection circuit in the PLL unit of FIG. 3. FIG. 4 is a circuit diagram showing a detailed configuration example of the digital control circuit in the PLL unit of FIG. 3. FIG. 4 is a circuit diagram showing a detailed configuration example of the charge pump control circuit in the PLL section of FIG. 3. FIG. 4 is a circuit diagram showing a detailed configuration example of the charge pump circuit in the PLL section of FIG. 3. FIG. 4 is a circuit diagram illustrating a detailed configuration example of the oscillation circuit in the PLL unit of FIG. 3. FIG. 2 is a circuit diagram showing a detailed configuration example of the delay circuit in the receiving circuit of FIG. 1. FIG. 13 is a circuit diagram showing a detailed configuration example of an inverter circuit capable of controlling the delay time in the delay circuit of FIG. 12. FIG. 3 is a circuit diagram showing a detailed configuration example of a second comparison circuit in the receiving circuit of FIG. 1. FIG. 10 is a circuit diagram showing a detailed configuration example of the flip-flop group in the receiving circuit according to the second embodiment of the present invention. FIG. 6 is a circuit diagram showing a detailed configuration example of a second comparison circuit in a receiving circuit according to a second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 PLL part 20 1st comparison circuit 21 1st phase comparison circuit 22 Frequency comparison circuit 23 Passing detection circuit 30 Control circuit 31 Steady state detection circuit 32 Digital control circuit 33 Charge pump control circuit 34 Charge pump circuit 35 Switching circuit 40 Oscillation Circuit 50 Frequency Divider 60 Delay Circuit 70-73 Flip-Flop Circuit 70 'Flip-Flop Group 80 Second Comparison Circuit 80' Second Comparison Circuit 81 Second Phase Comparison Circuit 90 Subsequent Circuit AD AND Circuit C Capacitance CNT Counter Circuit DC Inverter circuit capable of controlling delay time DLY delay circuit DR AND-NOR composite circuit FF flip-flop circuit IV inverter circuit ND NAND circuit NR NOR circuit R resistor RD OR-NAND composite circuit SL selector circuit SR Set reset Latch circuit Tn NMOS transistor Tp PMOS transistor Vdd high-potential power source Vss low potential side power source φ clock signal

Claims (11)

An oscillation circuit whose oscillation frequency is controlled by a control signal, a frequency dividing circuit that divides the output of the oscillation circuit and outputs a feedback signal, a reference signal that changes at a constant period, and a phase of the feedback signal are compared. A first phase comparison circuit; a flip-flop circuit that takes in externally supplied input data in synchronism with the output of the oscillation circuit; a timing at which the output of the oscillation circuit is applied to the flip-flop circuit; and the input data A second phase comparison circuit for comparing a timing relationship applied to the flip-flop circuit; and a control circuit for controlling an oscillation frequency of the oscillation circuit based on outputs of the first and second phase comparison circuits. ,
When the input data includes signal information, the control circuit controls the oscillation frequency of the oscillation circuit based on the output of the second phase comparison circuit, and when the input data does not include signal information, the first phase comparison. In the receiving circuit configured so that the control circuit controls the oscillation frequency of the oscillation circuit based on the output of the circuit,
The control signal for controlling the oscillation frequency of the oscillation circuit is composed of two control signals, and when the control signal of one of the two control signals is changed, the oscillation frequency of the oscillation circuit is The oscillation frequency of the oscillation circuit is configured to change slightly immediately when the control signal of the other system of the two systems of control signals is changed gradually and greatly. Receiver circuit. The receiving circuit according to claim 1,
When shifting from the state of controlling the oscillation frequency of the oscillation circuit based on the output of the first phase comparison circuit to the state of controlling the oscillation frequency of the oscillation circuit based on the output of the second phase comparison circuit Changes the control signal of the one system periodically and gradually based on the output of the second phase comparison circuit immediately after the transition,
When shifting from the state of controlling the oscillation frequency of the oscillation circuit based on the output of the second phase comparison circuit to the state of controlling the oscillation frequency of the oscillation circuit based on the output of the first phase comparison circuit Does not change the control signal of the one system immediately after the transition until the output of the first phase comparison circuit changes, and then periodically after the output of the first phase comparison circuit changes. And gradually and gradually changing the control signal of the one system based on the output of the first phase comparison circuit,
A receiving circuit configured to always and immediately reflect the output of the first or second phase comparison circuit in the control signal of the other system. The receiving circuit according to claim 1 or 2,
When the oscillation frequency of the oscillation circuit is controlled based on the output of the second phase comparison circuit, and when the oscillation frequency of the oscillation circuit is controlled based on the output of the first phase comparison circuit; A receiving circuit, characterized in that the frequency of changing the control signal of one of the systems is low compared. The receiving circuit according to any one of claims 1 to 3,
If the output of the flip-flop circuit has changed within a predetermined time, it is determined that the input data includes signal information, and control is performed based on the output of the second phase comparison circuit. If the output has not changed over a predetermined time, it is determined that there is no signal information in the input data, and control based on the output of the first phase comparison circuit is performed. circuit. The receiving circuit according to any one of claims 1 to 4,
In a subsequent circuit that performs signal processing based on the output of the flip-flop circuit, it is determined whether or not the input data includes signal information, and based on the output of either the first or second phase comparison circuit A receiving circuit configured to switch whether to control an oscillation frequency of an oscillation circuit based on a determination result of the subsequent circuit. In the receiving circuit according to any one of claims 1 to 5,
The flip-flop circuit is composed of two types of flip-flop circuits having different thresholds for the input data, and a selector circuit that selects the outputs of the two types of flip-flop circuits and outputs them as the outputs of the flip-flop circuits. When the output of the flip-flop circuit in a cycle is at a high level, one of the two types of flip-flop circuits is used as the output of the flip-flop circuit, and the output of the flip-flop circuit in the immediately preceding cycle is low. A receiver circuit configured to use the other output of the two types of flip-flop circuits as an output of the flip-flop circuit when the level is a level. The receiving circuit according to any one of claims 1 to 6,
There is provided a delay circuit that delays the output of the oscillation circuit and outputs at least three-phase clock signals having different timings, and the flip-flop circuit captures the input data in synchronization with each of the three-phase clock signals. Of flip-flop circuit,
If only the flip-flop circuit that takes in the input data in synchronization with the clock signal of the earliest phase among the three flip-flop circuits outputs a value different from the other two flip-flop circuits, the oscillation When the output phase of the circuit is early, the second phase comparison circuit determines that only the flip-flop circuit that captures the input data in synchronization with the clock signal having the slowest phase among the three flip-flop circuits is the other. A receiving circuit, wherein the second phase comparison circuit determines that the phase of the output of the oscillation circuit is late when a value different from two flip-flop circuits is output. The receiving circuit according to claim 7, wherein
The delay circuit is composed of a delay circuit that delays the output of the oscillation circuit and outputs a clock signal of even phase of four or more phases at substantially equal timing,
The flip-flop circuit includes the three flip-flop circuits, and includes a plurality of flip-flop circuits that capture the input data in synchronization with each of the even-phase clock signals.
The clock signal having the earliest phase among the three flip-flop circuits that capture the input data in synchronization with the even-numbered and even-numbered odd-numbered three-phase clock signals corresponding to the even-numbered clock signals. If only the flip-flop circuit that captures the input data in synchronization with the output of the other two flip-flop circuits outputs a value different from that of the other two flip-flop circuits, the phase of the output of the oscillation circuit is early and the second phase comparison circuit And only the flip-flop circuit that takes in the input data in synchronization with the clock signal having the latest phase among the three flip-flop circuits outputs a value different from the other two flip-flop circuits. The receiving circuit is configured such that the second phase comparison circuit determines that the phase of the output of the oscillation circuit is late. The receiving circuit according to claim 7 or 8,
A receiving circuit characterized in that when all of the three flip-flop circuits output the same value, the second phase comparison circuit outputs the same determination result as that of the immediately preceding cycle. . The receiving circuit according to any one of claims 1 to 9,
A frequency comparison circuit that compares the frequency of the reference signal and the feedback signal, and a phase inversion detection circuit that detects that the phase relationship between the reference signal and the feedback signal is inverted, and there is no signal information of the input data. When the frequency comparison circuit detects that the frequency of either the reference signal or the feedback signal is high, the control signal of the one system is not detected until the phase inversion detection circuit detects phase inversion thereafter. A receiving circuit configured to stop a change. The receiving circuit according to claim 10, wherein
When the frequency comparison circuit detects that there is no signal information of the input data and the frequency of either the reference signal or the feedback signal is high, the control signal of the one system is greatly changed, and then the phase inversion is performed. A receiving circuit configured to stop the change of the control signal of the one system until the detection circuit detects phase inversion.

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