CN217643317U

CN217643317U - Adjustable pulse width clock generator and data arithmetic unit

Info

Publication number: CN217643317U
Application number: CN202221265673.6U
Authority: CN
Inventors: 不公告发明人
Original assignee: Beijing Yuanqi Advanced Microelectronics Co ltd
Current assignee: Hangzhou Yuanhe Technology Co ltd
Priority date: 2022-05-23
Filing date: 2022-05-23
Publication date: 2022-10-21
Anticipated expiration: 2032-05-23

Abstract

The utility model provides an adjustable pulse width clock generator and data arithmetic unit, adjustable pulse width clock generator includes the signal generation module and surely follows implementation module, the input and the clock source of signal generation module are connected, and receive the clock source signal that the clock source sent, the signal generation module carries out logic processing to clock source signal and surely follows the signal in order to generate, and will cut along signal from output, cut along the rising edge that implementation module generated pulse clock signal according to clock source signal, and carry out logic processing to clock source signal according to cutting along the signal in clock source signal's high level duration, with the falling edge that generates pulse clock signal, pulse clock signal is from cutting along the output of implementation module and exporting. After the pulse clock signal generated by the adjustable pulse width clock generator is input into the latch circuit needing clock signal level triggering, the holding time required by the input data signal input into the latch circuit can be reduced.

Description

Adjustable pulse width clock generator and data arithmetic unit

Technical Field

The utility model relates to a semiconductor device technical field especially relates to an adjustable pulse width clock generator and data arithmetic unit.

Background

The clock circuit is an oscillation circuit which generates accurate movement like a clock, and generally consists of a crystal oscillator, a crystal oscillator control chip and a capacitor. Clock circuits are widely used, such as clock circuits of computers, clock circuits of electronic watches, etc., and the clock circuits for generating clocks can also be generally called tunable pulse width clock generators.

In some latch circuits, a clock signal is required to be triggered when latching data, and if the level of an input clock signal is kept at a high level for a long time, an input data signal to be latched must be kept stable for a long holding time.

Since it is relatively troublesome to keep the input data signal stable for a long time, an adjustable pulse width clock generator capable of converting the clock signal input to the latch circuit into a pulse clock signal with a smaller high level duration is provided to reduce the holding time required for the input data signal input to the latch circuit, and meet the requirement of the latch circuit for normally storing data.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide an adjustable pulse width clock generator and data arithmetic unit to at least partially solve the above problems.

According to a first aspect of embodiments of the present application, there is provided an adjustable pulse width clock generator, comprising: the signal generating module comprises an input end and an output end, generates an edge-cutting signal according to the clock source signal, and outputs the edge-cutting signal from the output end of the signal generating module;

the system comprises an edge-cutting implementation module, wherein the edge-cutting implementation module comprises a first input end, a second input end and an output end, the first input end of the edge-cutting implementation module is connected with the clock source signal, the second input end of the edge-cutting implementation module is connected with the output end of the signal generation module, the edge-cutting implementation module generates a rising edge of a pulse clock signal according to the rising edge of the clock source signal, the edge-cutting implementation module performs logic processing on the clock source signal according to the edge-cutting signal within the high-level duration time of the clock source signal to generate a falling edge of the pulse clock signal, and the pulse clock signal is output from the output end of the edge-cutting implementation module.

In an optional implementation manner, the signal generation module includes cascaded odd-numbered inverters, where the odd-numbered inverters are configured to perform M times of phase inversion processing on the clock source signal to generate the edge-cut signal in phase inversion with the clock source signal, an input end of the signal generation module is an input end of a first-level inverter of the odd-numbered inverters, and an output end of the signal generation module is an output end of a last-level inverter of the odd-numbered inverters.

In an optional embodiment, the signal generation module includes 3 cascaded inverters, and each of the inverters includes a PMOS transistor and an NMOS transistor.

In an alternative embodiment, the cutting edge implementation module comprises: and a NAND gate circuit.

In an optional embodiment, the adjustable pulse width clock generator further comprises: and the output module is used for generating L paths of pulse signals according to the pulse clock signals, wherein L is an integer greater than or equal to 1.

In an optional embodiment, the adjustable pulse width clock generator further comprises: the output module comprises cascaded H-level inverters, the H-level inverters sequentially invert the pulse clock signal, the output signal of each level of inverter is used as a path of pulse signal, and H is an integer greater than or equal to 1.

In an optional implementation manner, the edge-cut implementing module is further configured to feed back the pulse clock signal to the signal generating module, so that the signal generating module generates an edge-cut signal according to the clock source signal.

In an optional embodiment, the tunable pulse width clock generator further comprises: the feedback module, the feedback module includes input and output, the input of feedback module is connected cut the output of implementing the module, the output of feedback module further couples to signal generation module, cut the edge implementing module and pass through the feedback module will pulse clock signal feeds back to signal generation module, so that signal generation module basis the pulse clock signal is right clock source signal carries out logic processing in order to generate cut the edge signal.

According to a second aspect of the embodiments of the present application, there is further provided a data arithmetic unit, which includes a control circuit, an arithmetic circuit and a clock circuit, which are interconnected, where the clock circuit is the adjustable pulse width clock generator provided in the first aspect.

According to a third aspect of embodiments of the present application, there is further provided a chip, which includes at least one data operation unit provided in the second aspect.

The adjustable pulse width clock generator provided by the embodiment of the application generates the edge-cutting signal according to the clock source signal and outputs the edge-cutting signal from the output end of the signal generation module, the edge-cutting implementation module can generate the rising edge of the pulse clock signal according to the rising edge of the clock source signal, and the edge-cutting implementation module carries out logic processing on the clock source signal according to the edge-cutting signal within the high-level duration time of the clock source signal so as to generate the falling edge of the pulse clock signal, and the pulse clock signal is output from the output end of the edge-cutting implementation module. Therefore, the falling edge of the pulse clock signal generated by the adjustable pulse width clock generator in this embodiment is faster than the falling edge of the clock source signal, that is, the duration of the high level of the pulse clock signal in this embodiment is shorter than the duration of the high level of the clock source signal, so that after the pulse clock signal is input to the latch circuit requiring level triggering of the clock signal, the holding time required by the input data signal input to the latch circuit can be reduced, and the requirement of the latch circuit for normally storing data can be met.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 shows a schematic structure diagram of an adjustable pulse width clock generator in this embodiment.

Fig. 2 shows a schematic structure diagram of another tunable pulse width clock generator in this embodiment.

FIG. 3 shows a timing diagram of one inverter in the present embodiment;

fig. 4 shows a specific circuit structure diagram of an optional adjustable pulse width clock generator in this embodiment.

Fig. 5 shows a schematic structural diagram of a data arithmetic unit provided in the embodiment of the present application.

Fig. 6 shows a schematic structural diagram of a chip provided in an embodiment of the present application.

Description of the reference numerals:

1. a signal generation module; 2. an edge cutting implementation module; 3. a feedback module; 4. an output module; 500. a data operation unit; 501. a control circuit; 502. an arithmetic circuit; 503. a clock circuit; 600. a chip; 601. a control unit;

CLK, a clock source signal; CKP, pulse clock signal; CKN, a first pulse signal; FB. An input of a feedback module; x, the output end of the signal generation module; OUT, an output end of the jumping unit; s1, an output end of a first inverter; s2, an output end of the second inverter; A. an output terminal of the sixth inverter;

q1 and a first PMOS tube; q2 and a second PMOS tube; q3 and a third PMOS tube; q4 and a fourth PMOS tube; q5 and a fifth PMOS tube; q6 and a sixth PMOS tube; q7 and a seventh PMOS tube; q8 and an eighth NMOS tube; q9 and a ninth NMOS tube; q10 and a tenth NMOS tube; q11 and an eleventh NMOS tube; q12 and a twelfth NMOS tube; q13 and a thirteenth NMOS tube; q14 and a fourteenth NMOS tube; q15 and a fifteenth PMOS tube; q16 and a sixteenth NMOS tube; q17 and a seventeenth PMOS tube; q18 and an eighteenth NMOS tube; q19 and a nineteenth PMOS tube; q20 and a twentieth NMOS transistor.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and that no limitation on the embodiments of the application is intended. It should be further noted that, for the convenience of description, only the portions related to the embodiments of the present application are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 1, an adjustable pulse width clock generator in this embodiment is shown, which includes a signal generating module 1, where the signal generating module 1 includes an input end and an output end, the input end of the signal generating module 1 is connected to a clock source, and receives a clock source signal sent by the clock source, and generates an edge-cut signal according to the clock source signal CLK, for example, performs logic processing on the clock source signal CLK to generate an edge-cut signal, and outputs the edge-cut signal from the output end of the signal generating module 1;

an edge-cut implementation module 2, where the edge-cut implementation module 2 includes a first input end, a second input end, and an output end, the first input end of the edge-cut implementation module 2 is connected to the clock source signal, the second input end of the edge-cut implementation module 2 is connected to the output end of the signal generation module 1, the edge-cut implementation module 2 generates a rising edge of a pulse clock signal CKP according to the rising edge of the clock source signal CLK, and the edge-cut implementation module 2 performs logic processing on the clock source signal CLK according to the edge-cut signal within a high-level duration of the clock source signal CLK to generate a falling edge of the pulse clock signal CKP, and the pulse clock signal CKP is output from the output end of the edge-cut implementation module 2.

The adjustable pulse width clock generator provided by the embodiment of the application generates the edge-cutting signal according to the clock source signal and outputs the edge-cutting signal from the output end of the signal generation module, the edge-cutting implementation module can generate the rising edge of the pulse clock signal according to the rising edge of the clock source signal, and the edge-cutting implementation module performs logic processing on the clock source signal according to the edge-cutting signal within the high-level duration of the clock source signal so as to generate the falling edge of the pulse clock signal, and the pulse clock signal is output from the output end of the edge-cutting implementation module. Therefore, the falling edge of the pulse clock signal generated by the adjustable pulse width clock generator in this embodiment is faster than the falling edge of the clock source signal, that is, the duration of the high level of the pulse clock signal in this embodiment is shorter than the duration of the high level of the clock source signal, so that after the pulse clock signal is input to the latch circuit requiring level triggering of the clock signal, the holding time required by the input data signal input to the latch circuit can be reduced, and the requirement of the latch circuit for normally storing data can be met.

It can be understood that the input end of the signal generating module 1 is connected to the clock source, specifically, the input end of the signal generating module 1 is connected to the output end of the clock source, so that the clock source can output the clock source signal to the signal generating module 1. The first input end of the edge-switching implementation module 2 is connected to the clock source signal, which means that the first input end of the edge-switching implementation module 2 is connected to the output end of the clock source, so that the clock source can output the clock source signal to the edge-switching implementation module 2.

In the embodiment of the present application, the clock source signal (CLK) is a periodic signal, generally with a fixed frequency, and the signal is generally a combination of high level and/or low level, which is sent from the clock source. In a digital logic circuit, the high level is 1 and the low level is 0. In addition, the change from high level to low level may be generally referred to as a falling edge, and the change from low level to high level may be generally referred to as a rising edge.

It can be understood that, when the adjustable pulse width clock generator provided in this embodiment is not used, the clock source signal CLK is directly input into the latch circuit to trigger the latch circuit, and when the adjustable pulse width clock generator provided in this embodiment is used, the clock source signal CLK is first input into the adjustable pulse width clock generator in this embodiment, and after the adjustable pulse width clock generator in this embodiment generates the pulse clock signal CKP, the pulse clock signal CKP is input into the latch circuit to trigger the latch circuit.

For example, when the adjustable pulse width clock generator in this embodiment is used, the output terminal of the edge-cut implementing module 2 may be connected to the clock input terminal of a latch circuit, and the pulse clock signal CKP may be input to the latch circuit.

Specifically, in the adjustable pulse width clock generator of this embodiment, the clock source signal may be input to the signal generating module 1, and the clock source signal is converted by the signal generating module to generate the edge-cut signal.

It is noted that the edge-cut signal is also a digital signal, i.e. also a combination of high and/or low levels.

In one embodiment, the signal generating module 1 includes cascaded odd-numbered inverters, where the odd-numbered inverters are configured to perform M times of phase inversion processing on the clock source signal to generate the edge-cut signal in phase inversion with the clock source signal, an input end of the signal generating module 1 is an input end of a first-level inverter of the odd-numbered inverters, and an output end of the signal generating module 1 is an output end of a last-level inverter of the odd-numbered inverters.

The inverter in this embodiment may invert the logic level of a signal input to the inverter once, that is, invert the signal, that is, invert the high level 1 to the low level 0 or invert the low level 0 to the high level 1. The inverter in this embodiment may be any circuit structure, and only needs to be able to perform inverting on the logic level of the signal, and as an example, the inverter may be a TTL not gate, and may also be another circuit structure (for example, an integrated inverter module), which is not limited in this application.

In addition, the odd-numbered inverters may be composed of an odd number of inverters with the same structure, or may be a combination of inverters with different structures, and the present embodiment is not limited thereto.

In an alternative embodiment, the inverter is composed of two enhancement type MOS tubes, and the inversion processing of the input signal can be completed through the on and off of the two MOS tubes. In a transistor, a MOS transistor generally includes a PMOS transistor and an NMOS transistor, and the structures of the PMOS transistor and the NMOS transistor are different, so that the on and off conditions of the PMOS transistor and the NMOS transistor are different.

Specifically, the single inverter in this embodiment may include a PMOS transistor and an NMOS transistor, for example, a gate of the PMOS transistor is connected to a gate of the NMOS transistor, a source of the PMOS transistor is connected to a power supply, a drain of the PMOS transistor is connected to a drain of the NMOS transistor, and a source of the NMOS transistor is grounded, and an electrical signal may be simultaneously input from the gates of the PMOS transistor and the NMOS transistor, so that one of the signals is turned on, and an inverted signal is output at an output end of the inverter.

In this circuit structure, the PMOS transistor is turned on when the gate-source voltage is smaller than a certain value, and the NMOS transistor is turned on when the gate-source voltage is greater than a certain value, so that the PMOS transistor is turned on at a low level and the NMOS transistor is turned on at a high level corresponding to a high-low logic level. Therefore, if the electrical signal is at a low level, the PMOS transistor is turned on, and the NMOS transistor is turned off, the electrical signal can be input from the gate of the PMOS, the power source pulls up the level of the drain of the PMOS to complete the inversion processing of the low level, and at this time, the high level can be output from the drain of the PMOS transistor; assuming that the electrical signal is at a high level, the NMOS transistor is turned on, and the PMOS transistor is turned off, the electrical signal can be input from the gate of the NMOS, and since the source of the NMOS is grounded, the level of the drain of the NMOS is pulled low to complete the inversion processing of the high level, and at this time, the low level can be output from the drain of the NMOS transistor. If the electrical signal has a rising edge or a falling edge, the corresponding inversion processing can be performed in the same manner as the above-mentioned turning on and off manner, for example, as shown in fig. 3, one period of the electrical signal input to the inverter is t2, and a high level is obtained from time 0 to t1, and a low level is obtained from time t1 to t2, then in the inverted signal, the NMOS is turned on to output a low level from time 0 to t1, and the PMOS is turned on to output a high level from time t1 to t 2.

Preferably, the signal generating module 1 in this embodiment includes 3 cascaded inverters, and each of the inverters includes a PMOS transistor and an NMOS transistor.

Specifically, referring to fig. 4, when N is 3, the signal generating module 1 includes a first inverter, a second inverter, and a third inverter, where the signal generating module 1 at least includes a first PMOS transistor Q1, a third PMOS transistor Q3, a fourth PMOS transistor Q4, an eighth NMOS transistor Q8, an eleventh NMOS transistor Q11, and a twelfth NMOS transistor Q12; the first PMOS transistor Q1 and the eighth NMOS transistor Q8 form the first phase inverter, the third PMOS transistor Q3 and the eleventh NMOS transistor Q11 form the second phase inverter, and the fourth PMOS transistor Q4 and the twelfth NMOS transistor Q12 form the third phase inverter; the clock source signal CLK is input from the input end of the first inverter, and after being subjected to the step-by-step inversion processing by the first inverter, the second inverter and the third inverter, edge-cutting signals are generated and output from the output end of the third inverter.

The grid electrode of the first PMOS tube Q1 is connected with CLK, the source electrode is connected with a power supply, and the drain electrode is connected with the drain electrode of the eighth NMOS tube Q8; the grid electrode of the third PMOS tube Q3 is connected with the drain electrodes of Q1 and Q8, the source electrode is connected with the drain electrode of Q2, and the source electrode is connected with the drain electrode of Q11; the grid electrode of the fourth PMOS pipe Q4 is connected with the drain electrodes of the Q3 and the Q11, the source electrode of the fourth PMOS pipe Q4 is connected with the power supply, and the drain electrode of the Q4 is connected with the drain electrode of the Q12; the grid electrode of the eighth NMOS tube Q8 is connected with CLK, the source electrode is connected with Q9, and the drain electrode is connected with the drain electrode of Q1; the grid electrode of the eleventh NMOS tube Q11 is connected with the drain electrodes of the Q1 and the Q8, the source electrode is connected with the ground, and the drain electrode is connected with the drain electrode of the Q3; the twelfth NMOS transistor Q12 has a gate connected to the drains of Q3 and Q11, a source connected to ground, and a drain connected to the drain of Q4.

In this embodiment, the edge-cut signal may be input to the edge-cut implementation module 2 and utilized by the edge-cut implementation module 2, in addition, the clock source inputs the same clock source signal as the clock source signal of the input signal generation module 1 from the first output end of the edge-cut implementation module 2 to the edge-cut implementation module 2, and the edge-cut implementation module 2 performs logic processing on the clock source signal CLK again according to the edge-cut signal to generate the required pulse clock signal CKP.

Specifically, the edge-cut implementing module 2 may generate a rising edge of the pulse clock signal CKP according to the rising edge of the clock source signal CLK, and the edge-cut implementing module 2 performs logic processing on the clock source signal CLK according to the edge-cut signal within the high level duration of the clock source signal CLK, thereby generating a falling edge of the pulse clock signal CKP.

In this embodiment, the internal structure and the circuit structure of the edge-cut implementation module 2 are not limited, and only the function of performing logic processing on the clock source signal CLK needs to be completed.

In one embodiment, the cutting edge implementation module 2 includes: and a NAND gate circuit. The edge-cut implementing module 2 can logically process the pulse clock signal through a nand gate circuit.

Specifically, the edge-cut implementing module 2 may be configured to perform logic operation on a signal logically processed by the nand gate circuit, and perform further logic operation on the signal after the logic processing by the nand gate circuit by using another circuit structure of the edge-cut implementing module 2 to generate a rising edge of the pulse clock signal, and perform logic operation on the pulse clock signal and the edge-cut signal by using the nand gate circuit to generate a falling edge of the pulse clock signal, where, in an optional circuit structure, referring to fig. 4, the pulse clock signal CKP is output from an output end of the edge-cut implementing module 2, the edge-cut implementing module 2 includes a transition unit and a fourth inverter, the transition unit includes a sixth PMOS transistor Q6, a seventh PMOS transistor Q7, a thirteenth NMOS transistor Q13, and a fourteenth NMOS transistor Q14, where a gate of the sixth PMOS transistor Q6 is connected to a gate of the thirteenth NMOS transistor Q13 to form a first input end of the transition unit, an output end of the clock source is connected to the first input end of the transition unit, a source of the sixth PMOS transistor Q6 is connected to the power supply, a drain of the sixth PMOS transistor Q6 is connected to a gate of the thirteenth NMOS transistor Q13, a drain of the fourteenth NMOS transistor Q14 is connected to a source of the second NMOS transistor Q7, and a drain of the second NMOS transistor Q14 is connected to a source of the second NMOS transistor Q7; and the drain electrode of the seventh PMOS tube Q7, the drain electrode of the sixth PMOS tube Q6 and the drain electrode of the thirteenth NMOS tube Q13 are connected to form the output end OUT of the hopping unit. The transition unit is used for generating an inverted signal of the pulse clock signal CKP according to the edge-cutting signal and the clock source signal CLK.

The fourth phase inverter comprises a fifteenth PMOS tube Q15 and a sixteenth NMOS tube Q16, the grid electrode of the fifteenth PMOS tube Q15 is connected with the grid electrode of the sixteenth NMOS tube Q16 to form the input end of the fourth phase inverter, the source electrode of the fifteenth PMOS tube Q15 is connected with the power supply, the drain electrode of the fifteenth PMOS tube Q15 is connected with the drain electrode of the sixteenth NMOS tube Q16 to form the output end of the fourth phase inverter, and the source electrode of the sixteenth NMOS tube Q16 is grounded; the input end of the fourth inverter is connected with the output end OUT of the jumping unit;

a first input terminal of the jumping unit is used as a first input terminal of the edge-cut implementing module 2, a second input terminal of the jumping unit is used as a second input terminal of the edge-cut implementing module 2, and an output terminal of the fourth inverter is used as an output terminal of the edge-cut implementing module 2.

Therefore, the fourth inverter is configured to invert the inverted signal of the pulse clock signal generated by the transition unit, and finally generate the pulse clock signal CKP, and the pulse clock signal CKP is output from the output terminal of the fourth inverter.

Specifically, in the above specific circuit structure, the edge-cut implementing module 2 is the nand gate circuit, which is formed by a sixth PMOS transistor Q6, a thirteenth NMOS transistor Q13, a seventh PMOS transistor Q7 and a fourteenth NMOS transistor Q14, wherein the sixth PMOS transistor Q6 and the thirteenth NMOS transistor Q13 can invert the high level of the clock source signal CLK input to the inverter, the edge-cut signal is input from the output terminal X of the signal generating module 1 to the second input terminal of the edge-cut implementing module 2, that is, the fourteenth NMOS transistor Q14 and the seventh PMOS transistor Q7 are input at the same time, and two MOS transistors in the edge-cut implementing module 2 are turned on or off.

In order to enable the signal generating module 1 to correctly generate the edge-cut signal according to the timing sequence of the pulse clock signal CKP, in one embodiment, optionally, the edge-cut implementing module 2 is further configured to feed back the pulse clock signal CKP to the signal generating module 1 so that the signal generating module 1 generates the edge-cut signal according to the clock source signal CLK.

Thus, the pulse clock signal CKP at the previous moment generated by the edge-cutting implementing module 2 can affect the edge-cutting signal at the next moment, so that the signal generating module can adjust the edge-cutting signal according to the pulse clock signal when generating the edge-cutting signal.

In this embodiment, the specific way in which the edge-cut implementing module 2 feeds back the signal to the signal generating module 1 is not limited, for example, a path of the pulse clock signal CKP generated by the edge-cut implementing module 2 may be led out and input to the input end of the signal generating module 1, or a path of the pulse clock signal CKP may be led out and input to the input end of a specific circuit element or circuit structure of the signal generating module 1, so as to control the behavior of the circuit element or circuit structure (for example, to turn on or off the circuit), so as to implement the function of signal feedback, and to generate the edge-cut signal correctly with a crucial influence.

Optionally, referring to fig. 2, the adjustable pulse width clock generator further includes: a feedback module 3, the feedback module 3 includes an input end and an output end, the input end of the feedback module 3 is connected to the output end of the edge-cut implementing module 2, the output end of the feedback module 3 is further coupled to the signal generating module 1, the edge-cut implementing module 2 feeds back the pulse clock signal CKP to the signal generating module 1 through the feedback module 3, so that the signal generating module 1 performs logic processing on the clock source signal CLK according to the pulse clock signal CKP to generate the edge-cut signal.

Specifically, referring to a specific circuit configuration, the feedback module 3 includes: a ninth NMOS transistor Q9, a fifth PMOS transistor Q5, a tenth NMOS transistor Q10, and a second PMOS transistor Q2, wherein a gate of the ninth NMOS transistor Q9 is connected to an output terminal of the edge-cut implementation module 2, a gate of the ninth NMOS transistor Q9 is connected to a gate of the fifth PMOS transistor Q5 and a gate of the tenth NMOS transistor Q10, a gate of the fifth PMOS transistor Q5 is connected to a gate of the tenth NMOS transistor Q10, a source of the fifth PMOS transistor Q5 is connected to a power supply, a source of the tenth NMOS transistor Q10 is grounded, a drain of the fifth PMOS transistor Q5 is connected to a drain of the tenth NMOS transistor Q10, a drain of the fifth PMOS transistor Q5 and a drain of the tenth NMOS transistor Q10 are connected to a gate of the second PMOS transistor, and a source of the second PMOS transistor is electrically connected to the power supply; the drain electrode of the second PMOS tube is connected with the source electrode of a third PMOS tube Q3; the drain electrode of the ninth NMOS transistor Q9 is connected to the source electrode of the eighth NMOS transistor Q8, and the source electrode of the ninth NMOS transistor Q9 is grounded.

In a preferred embodiment, referring to fig. 4, the edge-cutting implementing module 2 may further include a sixth inverter, where the sixth inverter includes a nineteenth PMOS transistor and a twentieth NMOS transistor, a gate of the nineteenth PMOS transistor Q15 is connected to a gate of the twentieth NMOS transistor Q16 and forms an input terminal of the sixth inverter, a source of the nineteenth PMOS transistor Q15 is connected to the power supply, a drain of the nineteenth PMOS transistor Q15 is connected to a drain of the twentieth NMOS transistor Q16 and forms an output terminal of the sixth inverter, a source of the twentieth NMOS transistor Q16 is grounded, an output terminal a of the sixth inverter is connected to the input terminal of the signal delaying module 12, and an input terminal of the sixth inverter is connected to the output terminal OUT of the jumping unit.

The output of the sixth inverter may be used as the further output of the clip edge implementing block 2. It should be noted that although the sixth inverter is not the same inverter as the fourth inverter, since the output terminal of the transition unit outputs the inverted signal of the pulse clock signal, the output terminal of the sixth inverter actually outputs the same pulse clock signal CKP as the output terminal of the fourth inverter. Moreover, since the pulse clock signal CKP output from the output terminal of the fourth inverter may be directly input to other external circuits, the pulse clock signal fed back by the feedback module 3 may be interfered by the external circuit when the pulse clock signal CKP directly output from the output terminal of the fourth inverter enters the feedback module 3, and the sixth inverter of the edge-cut implementation module 2 may prevent the signal fed back by the feedback module 3 from being interfered by the external circuit, and may also play a role of feeding back the pulse clock signal CKP to the signal generation module 1.

In one embodiment, referring to fig. 2, the adjustable pulse width clock generator in this embodiment further includes an output module 4, where the output module 4 is configured to generate L paths of pulse signals according to the pulse clock signal, where L is an integer greater than or equal to 1.

At least one path of pulse signal is output through the output module 4 according to the pulse clock signal CKP and then input into different circuits, so that the obtained pulse clock signal CKP can be better utilized.

In this embodiment, the specific structure of the output module 4 is not limited, and it may be a circuit module that processes the pulse clock signal again to obtain a required pulse signal, or may be a circuit module that directly outputs the pulse clock signal as a pulse signal to a circuit that requires the pulse clock signal.

In one preferred embodiment, the output module 4 includes cascaded H-level inverters, the H-level inverters sequentially perform inversion processing on the pulse clock signal, an output signal of each level of inverter is used as a path of pulse signal, where H is an integer greater than or equal to 1.

In this embodiment, H may be less than or equal to L, and when H is equal to L, the H-path pulse signal generated by the H-level inverter is the L-path pulse signal; when H is smaller than L, it indicates that there may be a circuit structure in the output module 4 capable of generating other paths of pulse signals, or that the single-stage inverter may generate more than one path of pulse signals. In this regard, the present embodiment is not particularly limited.

If H is equal to 1, the output module 4 only has a first-stage inverter, and the output pulse signal is a path of pulse signal which is in inverse phase with the pulse clock signal; if H is greater than 1, the output module 4 has at least two inverters, and the output pulse signals are at least two paths, where the pulse signals output by the odd-numbered inverters are pulse signals inverted from the pulse clock signals, and the pulse signals output by the even-numbered inverters are pulse signals identical to the pulse clock signals. This enables the output module 4 to output pulse signals of different phases, which can further meet different practical requirements.

The phase inverter of the output module 4 in this embodiment is not particularly limited in this embodiment, and may have any circuit structure, as long as it can perform phase inversion processing on a logic level of a signal.

In one of the circuit configurations, the inverter has the same configuration as the inverter in the signal flipping module 11 described above. Specifically, referring to fig. 4, where H is equal to 1, the output module 4 includes a fifth inverter, the fifth inverter includes a seventeenth PMOS transistor Q17 and an eighteenth NMOS transistor Q18, a gate of the seventeenth PMOS transistor Q17 is connected to a gate of the eighteenth NMOS transistor Q18 and forms an input end of the fifth inverter, a source of the seventeenth PMOS transistor Q17 is connected to a power supply, a drain of the seventeenth PMOS transistor Q17 is electrically connected to a drain of the eighteenth NMOS transistor Q18 and forms an output end of the fifth inverter, and a source of the eighteenth NMOS transistor Q18 is grounded; the input end of the fifth inverter is connected with the output end of the edge cutting implementation module 2.

The pulse clock signal CKP output by the edge-cut implementing module 2 is input from the input end of the fifth inverter, the first pulse signal CKN is a signal that is inverted from the pulse clock signal CKP, and the first pulse signal CKN is output from the output end of the fifth inverter.

In this specific circuit structure, the pulse clock signal CKP is output from the output terminal of the edge-cut implementing module 2, and a pulse signal with an inverted phase is output according to the pulse clock signal CKP, so that different practical requirements can be fully satisfied. Obviously, if more paths of the first pulse signal CKN are needed in actual use, only the lead wire needs to be performed at the output end of the fifth inverter, and if more paths of the pulse clock signal CKP are needed, only the lead wire needs to be performed at the output end of the fourth inverter, so that additional electronic elements are not needed to form more multi-stage inverters, the requirement is met, and the cost is saved.

It is understood that, further, the sixth inverter in the aforementioned alternative embodiment can also prevent the pulse clock signal CKP from being directly transmitted from the output terminal of the fourth inverter to the feedback module 3 to interfere with the first pulse signal CKN output by the fifth inverter of the output module.

A specific complete circuit structure of the tunable pulse width clock generator in the embodiment of the present application is described below, and it should be understood that it is not a limitation to the embodiment of the present application, and specifically, the tunable pulse width clock generator includes: the device comprises a signal generation module 1, an edge cutting implementation module 2, a feedback module 3 and an output module 4;

the signal generation module 1 comprises a first phase inverter, a second phase inverter and a third phase inverter, wherein the first phase inverter comprises a first PMOS (P-channel metal oxide semiconductor) tube Q1 and an eighth NMOS (N-channel metal oxide semiconductor) tube Q8, the second phase inverter comprises a third PMOS tube Q3 and an eleventh NMOS tube Q11, and the third phase inverter comprises a fourth PMOS tube Q4 and a twelfth NMOS tube Q12; the grid electrode of the first PMOS tube Q1 is connected with the grid electrode of the eighth NMOS tube Q8 to form the input end of the first phase inverter, the drain electrode of the first PMOS tube Q1 is connected with the drain electrode of the eighth NMOS tube Q8 to form the output end S1 of the first phase inverter, and the source electrode of the first PMOS tube Q1 is connected with a power supply; the grid electrode of the third PMOS tube is connected with the grid electrode of an eleventh NMOS tube and forms the input end of the second phase inverter, the drain electrode of the third PMOS tube is connected with the drain electrode of the eleventh NMOS tube and forms the output end S2 of the second phase inverter, and the source electrode of the eleventh NMOS tube is grounded; the grid electrode of the fourth PMOS tube Q4 is connected with the grid electrode of the twelfth NMOS tube Q12 to form the input end of the third phase inverter, the source electrode of the fourth PMOS tube Q4 is connected with the power supply, the drain electrode of the fourth PMOS tube Q4 is connected with the drain electrode of the twelfth NMOS tube Q12 to form the output end of the third phase inverter, and the source electrode of the twelfth NMOS tube Q12 is grounded; the input end of the first phase inverter is used as the input end of the signal generation module 1, the output end of the third phase inverter is used as the output end X of the signal generation module, and the input end of the signal generation module 1 is connected with the output end of the clock source;

the edge-cutting implementing module 2 comprises a trip unit and a fourth inverter, the trip unit comprises a nand gate circuit, the trip unit comprises a sixth PMOS transistor Q6, a seventh PMOS transistor Q7, a thirteenth NMOS transistor Q13 and a fourteenth NMOS transistor Q14, wherein a gate of the sixth PMOS transistor Q6 is connected with a gate of the thirteenth NMOS transistor Q13 and forms a first input end of the trip unit, an output end of the clock source is connected with the first input end of the trip unit, a source of the sixth PMOS transistor Q6 is connected with a power supply, a drain of the sixth PMOS transistor Q6 is connected with a drain of the thirteenth NMOS transistor Q13, a source of the thirteenth NMOS transistor Q13 is connected with a drain of the fourteenth NMOS transistor Q14, a source of the fourteenth NMOS transistor Q14 is grounded, a gate of the fourteenth NMOS transistor Q14 is connected with a gate of the seventh PMOS transistor Q7 and forms a second input end of the trip unit, a second input end of the trip unit is connected with an output end X of the signal generating module 1, and a source of the seventh PMOS transistor Q7 is connected with a power supply; the drain electrode of the seventh PMOS tube Q7, the drain electrode of the sixth PMOS tube Q6 and the drain electrode of the thirteenth NMOS tube Q13 are connected to form an output end OUT of the hopping unit; the fourth inverter comprises a fifteenth PMOS (p-channel metal oxide semiconductor) transistor Q15 and a sixteenth NMOS (n-channel metal oxide semiconductor) transistor Q16, a grid electrode of the fifteenth PMOS transistor Q15 is connected with a grid electrode of the sixteenth NMOS transistor Q16 to form an input end of the fourth inverter, a source electrode of the fifteenth PMOS transistor Q15 is connected with a power supply, a drain electrode of the fifteenth PMOS transistor Q15 is connected with a drain electrode of the sixteenth NMOS transistor Q16 to form an output end of the fourth inverter, and a source electrode of the sixteenth NMOS transistor Q16 is grounded; the input end of the fourth inverter is connected with the output end OUT of the jumping unit;

wherein, the first input terminal of the jumping unit is used as the first input terminal of the edge-cut implementing module, the second input terminal of the jumping unit is used as the second input terminal of the edge-cut implementing module, and the output terminal of the fourth inverter is used as the output terminal of the edge-cut implementing module 2;

the edge-cutting implementation module 2 further comprises a sixth phase inverter, the sixth phase inverter comprises a nineteenth PMOS transistor and a twentieth NMOS transistor, a gate of the nineteenth PMOS transistor Q15 is connected with a gate of the twentieth NMOS transistor Q16 to form an input terminal of the sixth phase inverter, a source of the nineteenth PMOS transistor Q15 is connected with a power supply, a drain of the nineteenth PMOS transistor Q15 is connected with a drain of the twentieth NMOS transistor Q16 to form an output terminal a of the sixth phase inverter, a source of the twentieth NMOS transistor Q16 is grounded, an output terminal a of the sixth phase inverter is connected with an input terminal FB of the feedback module, and an input terminal of the sixth phase inverter is connected with an output terminal OUT of the hopping unit; the output end A of the sixth inverter is used as the other output end of the edge-cutting implementation module 2;

the feedback module 3 includes a ninth NMOS transistor Q9, a fifth PMOS transistor Q5, a tenth NMOS transistor Q10 and a second PMOS transistor Q2, wherein a gate of the ninth NMOS transistor Q9 is connected to an output a of the sixth inverter as an input FB of the feedback module, the gate of the ninth NMOS transistor Q9 is further connected to a gate of the fifth PMOS transistor Q5 and a gate of the tenth NMOS transistor Q10, the gate of the fifth PMOS transistor Q5 is connected to a gate of the tenth NMOS transistor Q10, the source of the fifth PMOS transistor Q5 is connected to a power supply, the source of the tenth NMOS transistor Q10 is grounded, the drain of the fifth PMOS transistor Q5 is connected to a drain of the tenth NMOS transistor Q10, the drain of the fifth PMOS transistor Q5 and the drain of the tenth NMOS transistor Q10 are connected to a gate of the second PMOS transistor Q2, and the source of the second PMOS transistor Q2 is electrically connected to the power supply; the drain electrode of the second PMOS tube Q2 is connected with the source electrode of the third PMOS tube Q3; the drain electrode of the ninth NMOS tube Q9 is connected with the source electrode of the eighth NMOS tube Q8, and the source electrode of the ninth NMOS tube Q9 is grounded;

the output module 4 comprises a fifth phase inverter, and the fifth phase inverter comprises a seventeenth PMOS transistor Q17 and an eighteenth NMOS transistor Q18; the grid electrode of the seventeenth PMOS tube Q17 is connected with the grid electrode of the eighteenth NMOS tube Q18 to form the input end of the fifth phase inverter, the source electrode of the seventeenth PMOS tube Q17 is connected with a power supply, the drain electrode of the seventeenth PMOS tube Q17 is connected with the drain electrode of the eighteenth NMOS tube Q18 to form the output end of the fifth phase inverter, and the source electrode of the eighteenth NMOS tube Q18 is grounded; and the input end of the fifth inverter is connected with the output end of the fourth inverter.

The following is a detailed description of the specific operation and principle of the tunable pulse width clock generator in this embodiment, with reference to the above-described whole specific circuit structure of the tunable pulse width clock generator in fig. 4, and it should be understood that the present invention is not limited thereto.

For the convenience of viewing, the PMOS transistors, the NMOS transistors, the input terminals, and the output terminals are replaced by only their reference numbers, for example, "Q1" represents "the first PMOS transistor Q1", and "Q8" represents "the eighth NMOS transistor Q8", and so on, and the shapes "XXX =0, XXX =1" represents that a certain point in the circuit or a certain signal has a low level, a high level, and so on.

In this circuit, a clock source sends a clock source signal CLK to a signal generation module 1, the clock source signal CLK is a periodic signal, and before a next clock cycle is triggered after a clock cycle is finished, the clock source signal CLK is at a low level, that is, CLK =0. At this time, the clock source signal CLK is divided into two paths and respectively input to the signal generating module 1 and the edge-cutting implementing module 2 from the input terminal of the signal generating module 1 and the first input terminal of the edge-cutting implementing module 2. The low level of the clock source signal CLK in the first path is transmitted to the gates of Q1 and Q8 in the first inverter, so that Q1 is turned on, the level of the output terminal S1 of the first inverter is pulled high, S1=1, further Q11 is turned on, the output terminal S2 of the second inverter outputs the low level, S2=0, then Q4 is turned on, and the low level is inverted to the high level by the third inverter, so that X =1, thereby turning on Q14 in the edge-cutting implementation module 2 and turning off Q7; the low level of the clock source signal CLK of the second path is input to the input end of the edge-cutting implementing module 2, so that Q6 is turned on, Q13 is turned off, so that the level of OUT is pulled high by the power supply, OUT =1, and Q20 in the sixth inverter is turned on, so that the output end a =0 of the sixth inverter (as can be seen from the foregoing, the signal output at point a is the same as CKP), Q9 in the feedback module 3 is turned off, Q10 is turned off, Q5 is turned on, and Q2 is turned off, and the circuit reaches a stable state, at this time, the output of the OUT end is always high level 1, so that CKP output by the output end of the fourth inverter is always low level 0, CKN output by the output end of the fifth inverter is always high level 1, and until the rising edge of the clock source CLK below comes.

When the rising edge of the clock source signal CLK comes, Q13 in the edge-cut implementing block 2 is turned on, Q6 is turned off, so that OUT is pulled low, OUT comes on the falling edge, Q15 in the fourth inverter is turned on, Q16 is turned off, and therefore CKP comes on the rising edge. Thus, the edge-cut implementation module 2 performs logic processing based on the clock source signal CLK to generate a rising edge of the pulse clock signal CKP.

During the high level duration of the clock source signal CLK, since Q19 of the sixth inverter is turned on, a rising edge occurs at a point a, then the signal of CKP is input from the output terminal a of the sixth inverter to the input terminal FB of the feedback module 3, i.e., the gate of Q9, then Q9 is turned on, Q10 is turned on, Q5 is turned off, and Q2 is turned on, so that the first inverter, the second inverter, and the third inverter in the signal generating module 1 can normally operate, and then the rising edge of CLK input to the input terminal of the signal generating module 1 turns on Q8, Q1 is turned off, the output terminal S1 of the first inverter is pulled low, S1=0, further Q3 is turned on, Q11 is turned off, the output terminal S2 of the second inverter is pulled high, S2=1, further Q12 is turned on, and Q4 is turned off, so that the output terminal X of the signal generating module 1 is at a low level, i.e., X =0.X =0 is input to the second input terminal of the cut-edge implementing module 2, so that Q14 in the jumping unit in the cut-edge implementing module 2 is turned off, Q7 is turned on, and since CLK =1 is input to the first input terminal of the cut-edge implementing module 2, Q6 is turned off, and Q13 is turned on, so that the level of the output terminal OUT of the jumping unit is pulled high by the power supply connected to the drain of Q7, that is, the OUT rising edge, so that CKP is brought to the falling edge, CKN is brought to the rising edge, and therefore the pulse clock signal CKP is brought to the falling edge. Thus, the edge-cut implementing module 2 performs logic processing on the clock source signal CLK according to the edge-cut signal during the high level duration of the clock source signal CLK to generate the falling edge of the pulse clock signal CKP.

After the falling edge of the pulse clock signal CKP, the clock source signal CLK is still at the high level for the duration. When OUT =1, Q19 is turned off, Q20 is turned on, and the sixth inverter output a is at a low level, that is, a =0, and further FB =0, Q9 is turned off, Q5 is turned on, Q10 is turned off, and Q2 is turned off in the feedback block 3, so that when CLK =1 is input from the input terminal of the signal generation block 1 at this time, Q1 is turned off and Q8 is turned on, but since Q9 is turned off, S1 floats, and the previous low level state is dynamically stored by the node capacitance, S1=0, further, Q3 is turned on and Q11 is turned off in the second inverter, but since Q2 is turned off, S2 floats, and since the previous high level state is dynamically stored by the node capacitance, S2=1, further, Q12 is turned on and Q4 is turned off in the third inverter, and X =0. Thus, the following steps are the same as the previous steps: x =0 is input to the second input terminal of the edge-cutting implementing module 2, so that Q14 in the jumping unit in the edge-cutting implementing module 2 is turned off, Q7 is turned on, and since CLK =1 is input to the first input terminal of the edge-cutting implementing module 2, Q6 is turned off, and Q13 is turned on, so that the level of the output terminal OUT of the jumping unit is pulled up by the power supply connected to the drain of Q7, that is, OUT =1, CKP =0, and CKN =1. Thus, during the remaining high duration of CLK, the low state of CKP is maintained steadily until the falling edge of CLK arrives.

When a falling edge of a clock source signal CLK comes, inputting a signal generating module 1 to enable Q1 in a first phase inverter to be switched on, Q8 to be switched off, S1 to meet a rising edge to enable Q3 in a second phase inverter to be switched off, Q11 to be switched on, S2 to meet a falling edge to enable Q4 in a third phase inverter to be switched on, Q12 to be switched off, an output end X of the signal generating module 1 to meet a rising edge, and a cutting edge signal of the rising edge is input to a second input end of a cutting edge implementing module 2 to enable Q14 in the cutting edge implementing module to be switched on and Q7 to be switched off; the CLK falling edge inputs the first input of the edge-cut implementation block, turning Q6 on and Q13 off, so OUT =1, CKP =0 and ckn =1. Therefore, at the falling edge of CLK, the pulse clock signal CKP still maintains the low level state, and the state of the clock source signal being at low level before the next clock cycle is triggered at the end of one clock cycle will be repeated in the following CLK low level duration, that is, the state of CLK =0", so that CKP will be at low level 0 until the rising edge of the next CLK comes.

In summary, the signal generating module 1 of the adjustable pulse width clock generator can generate a cut edge signal according to the clock source signal CLK and output the cut edge signal from the output end of the signal generating module 1, the cut edge implementing module 2 can generate a rising edge of the pulse clock signal CKP according to the rising edge of the clock source signal CLK, and the cut edge implementing module 2 performs logic processing on the clock source signal CLK according to the cut edge signal within the high level duration of the clock source signal CLK to generate a falling edge of the pulse clock signal CKP, and the pulse clock signal CKP is output from the output end of the cut edge implementing module 2.

In this specific circuit structure, the pulse clock signal CKP is equivalent to that after the rising edge comes, the fed back pulse clock signal CKP can almost reach the signal generating module 1 at the next moment, so that the pulse clock signal CKP can come to the falling edge at the next moment after the rising edge comes, and the high level state of the pulse clock signal CKP actually lasts for only a moment.

Therefore, according to the adjustable pulse width clock generator provided by the embodiment of the application, because the adjustable pulse width clock generator generates the edge-cut signal according to the clock source signal and outputs the edge-cut signal from the output end of the signal generation module, the edge-cut implementation module can generate the rising edge of the pulse clock signal according to the rising edge of the clock source signal, and the edge-cut implementation module performs logic processing on the clock source signal according to the edge-cut signal within the high-level duration of the clock source signal to generate the falling edge of the pulse clock signal, and the pulse clock signal is output from the output end of the edge-cut implementation module. Therefore, the falling edge of the pulse clock signal generated by the adjustable pulse width clock generator in this embodiment is faster than the falling edge of the clock source signal, that is, the duration of the high level of the pulse clock signal in this embodiment is shorter than the duration of the high level of the clock source signal, so that after the pulse clock signal is input to the latch circuit requiring level triggering of the clock signal, the holding time required by the input data signal input to the latch circuit can be reduced, and the requirement of the latch circuit for normally storing data can be met.

The adjustable pulse width clock generator provided in the embodiment of the present application may be used as a customized standard unit, for example, may be used as a clock signal generator to provide a clock pulse signal for a scene requiring a pulse signal, such as: an adjustable pulse width clock generator which can be used as a pulse latch, a staggered adjustable pulse width clock generator of a shift register, a multi-way non-overlapping adjustable pulse width clock generator and the like. For another example: the clock generator can be used as a clock generating unit in a CPU/CPU and is used for generating a clock pulse signal in a super-large scale calculation scene; the clock generating unit can also be used as a clock generating unit in an AI (Artificial Intelligence) chip and is used for generating clock pulse signals under a high-density computing scene; the clock generator can also be used as a System-level clock generating unit such as an SOC (System on Chip)/FPGA (Field Programmable Gate Array) and the like, and is used for generating a clock pulse signal in a low-power-consumption calculation and other scenes.

A second aspect of the embodiment of the present application further provides a data operation unit, and fig. 5 is a schematic structural diagram of the data operation unit in the embodiment of the present application. As shown in fig. 5, the data operation unit 500 includes a control circuit 501, an operation circuit 502, and a plurality of clock circuits 503. The control circuit 501 controls the clock circuit 503 so that the clock circuit 503 generates a clock pulse signal, and the arithmetic circuit 502 performs arithmetic processing on data based on the clock pulse signal. The clock circuit 503 is an adjustable pulse width clock generator in any of the above embodiments.

The third aspect of the embodiment of the present application further provides a chip, and fig. 6 is a schematic structural diagram of the chip in the embodiment of the present application. As shown in fig. 6, the chip 600 includes a control unit 601, and one or more data operation units 500. The control unit 601 inputs data to the data operation unit 500 and processes the data output from the data operation unit 500.

The expressions "first", "second", "first" or "second" used in various embodiments of the present disclosure may modify various components regardless of order and/or importance, but these expressions do not limit the respective components. The above description is only configured for the purpose of distinguishing elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

When an element (e.g., a first element) is referred to as being "operably or communicatively coupled" or "connected" (operably or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the element is directly connected to the other element or the element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), no element (e.g., a third element) is interposed therebetween.

The foregoing description is only exemplary of the preferred embodiments of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, and other embodiments in which the above-mentioned features or their equivalents are combined arbitrarily without departing from the spirit of the present invention are also encompassed. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. An adjustable pulse width clock generator, comprising:

the signal generating module comprises an input end and an output end, and generates an edge-cutting signal according to a clock source signal and outputs the edge-cutting signal from the output end of the signal generating module;

2. The clock generator according to claim 1, wherein the signal generating module comprises cascaded odd-numbered inverters, the odd-numbered inverters are configured to perform M times of phase inversion processing on the clock source signal to generate the edge-cut signal in phase inversion with the clock source signal, an input terminal of the signal generating module is an input terminal of a first-level inverter of the odd-numbered inverters, an output terminal of the signal generating module is an output terminal of a last-level inverter of the odd-numbered inverters, and M is an odd number.

3. The tunable pulse width clock generator of claim 2, wherein the signal generation module comprises 3 cascaded inverters, and each of the inverters comprises a PMOS transistor and an NMOS transistor.

4. The tunable pulse width clock generator of claim 1, wherein the edge-cut implementation module comprises: and a NAND gate circuit.

5. The tunable pulse width clock generator of claim 1, further comprising: and the output module is used for generating L paths of pulse signals according to the pulse clock signals, wherein L is an integer greater than or equal to 1.

6. The tunable pulse width clock generator of claim 5, further comprising: the output module comprises cascaded H-level inverters, the H-level inverters sequentially perform phase inversion processing on the pulse clock signals, an output signal of each level of inverter is used as a path of pulse signal, and H is an integer greater than or equal to 1.

7. The tunable pulse width clock generator of any one of claims 1-6, wherein the edge-cut implementation module is further configured to feed back the pulse clock signal to the signal generation module so that the signal generation module generates an edge-cut signal according to the clock source signal.

8. The adjustable pulse width clock generator of claim 7, further comprising: the feedback module, the feedback module includes input and output, the input of feedback module is connected cut the output of implementing the module, the output of feedback module further couples to signal generation module, cut the edge implementing module and pass through the feedback module will pulse clock signal feeds back to signal generation module, so that signal generation module basis the pulse clock signal is right clock source signal carries out logic processing in order to generate cut the edge signal.

9. A data arithmetic unit comprising interconnected control circuitry, arithmetic circuitry and clock circuitry, the clock circuitry being an adjustable pulse width clock generator as claimed in any one of claims 1 to 8.