CN117155352A - Clock signal bandwidth regulating circuit and clock signal bandwidth regulating method - Google Patents
Clock signal bandwidth regulating circuit and clock signal bandwidth regulating method Download PDFInfo
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- CN117155352A CN117155352A CN202311353494.7A CN202311353494A CN117155352A CN 117155352 A CN117155352 A CN 117155352A CN 202311353494 A CN202311353494 A CN 202311353494A CN 117155352 A CN117155352 A CN 117155352A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The invention provides a clock signal bandwidth regulating circuit and a clock signal bandwidth regulating method, comprising the following steps: the device comprises a first clock signal generation module, a second clock signal generation module, a feedback module and an output module; the first clock generation module is used for inverting and delaying the clock signal to obtain a first clock signal, and regulating and controlling the bandwidth of the first clock signal based on the level control signal output by the feedback module; the second clock generation module inverts the first clock signal to obtain a second clock signal; the feedback module obtains a level control signal based on the bandwidth control signal, the first clock signal and the second clock signal; setting a clock signal bandwidth regulating circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of a bandwidth control signal; the output module is connected with the second clock signal and outputs the second clock signal. The invention further realizes the switching of the narrow bandwidth modulation and the wide bandwidth modulation of the clock signal by setting the bandwidth control signal, and solves the problem that the conventional bandwidth regulating circuit is single in regulation.
Description
Technical Field
The present invention relates to the field of periodic signal generation, and in particular, to a clock signal bandwidth control circuit and a clock signal bandwidth control method.
Background
In the application of a numerical control device and a microprocessor, the equipment often needs to perform calculation or operation according to a preset sequence, which requires that a control part of the equipment not only can correctly send out various control signals, but also requires that the control signals have a certain sequence in time, namely, output time sequence pulse signals, so as to realize the coordinated action of all parts of the equipment. A method of performing timing control using a pulse signal is generally adopted.
The existing pulse clock generation circuit is all to obtain pulse signals through conversion of input clock signals, and the pulse signals can be directly output to subsequent devices. However, the existing pulse clock generation circuit only has one working mode (namely, only pulse signals can be generated), and when the subsequent devices need to use clock signals with larger bandwidths, the pulse clock generation circuit cannot provide corresponding signals with larger bandwidths, and the problem of single used mode exists.
Based on the above, the invention provides a new clock signal bandwidth regulating circuit, which is used for solving the problem that the existing pulse clock generating circuit only has one working mode.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a clock signal bandwidth adjusting circuit and a clock signal bandwidth adjusting method, which are used for solving the problem of single usage scenario of a pulse clock generating circuit in the prior art.
To achieve the above and other related objects, the present application provides a clock signal bandwidth adjusting circuit, comprising:
the device comprises a first clock signal generation module, a second clock signal generation module, a feedback module and an output module;
the first clock generation module is connected with the output end of the feedback module, receives a clock signal, is used for inverting and delaying the clock signal to obtain a first clock signal, and regulates and controls the bandwidth of the first clock signal based on a level control signal output by the feedback module;
The second clock generation module receives the first clock signal and is used for inverting the first clock signal to obtain a second clock signal;
the feedback module receives a bandwidth control signal, the first clock signal and the second clock signal respectively, and sets the clock signal bandwidth regulation circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal; in the wide bandwidth mode, a second clock signal in the feedback module is disabled, and then a level control signal which is in phase opposition to the first clock signal is output so as to maintain the bandwidth of the first clock signal; in the narrow bandwidth mode, a second clock signal in the feedback module is effective, delays the second clock signal, and outputs a level control signal which is opposite to the first clock signal within a preset time of a rising edge of the delayed second clock signal so as to shorten the bandwidth of the first clock signal;
the output module is connected with the second clock signal and outputs the second clock signal.
Optionally, the second clock signal generating module includes a first nand gate and a delay signal generating unit; the delay signal generating unit is connected with the first clock signal and the delay switch signal, and delays the first clock signal and obtains a delay signal when the delay switch signal is effective; when the delay switch signal is invalid, the delay signal is invalid; the input end of the first NAND gate receives the first clock signal and the output signal of the delay signal generating unit respectively, and the second clock signal is obtained based on the signal output by the delay signal generating unit.
Optionally, the delay signal generating unit includes a second inverter and a second nand gate; the input end of the second inverter is connected with the first clock signal; the first input end of the second NAND gate is connected with the output end of the second inverter, the second input end of the second NAND gate is connected with a delay switch signal, the output end of the second NAND gate is connected with the first NAND gate, and the delay signal is output when the delay switch signal is effective.
Optionally, the feedback module includes a third inverter, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a third nand gate; the input end of the third inverter is connected with the bandwidth control signal, and the output end of the third inverter is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth PMOS tube; the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the second clock signal, and the drain electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube; the source electrode of the fifth PMOS tube is connected with a power supply voltage, the grid electrode of the fifth PMOS tube is connected with the second clock signal, and the drain electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube; the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube; the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube; the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube; the source electrode of the fourth PMOS tube is connected with the power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the first input end of the third NAND gate; and a second input end of the third NAND gate is connected with the first clock signal, and an output end of the third NAND gate is used as an output end of the feedback module.
Optionally, the feedback module further comprises a first bandwidth adjusting unit; the first bandwidth adjusting unit is arranged between the source electrode of the fifth PMOS tube and the power supply voltage; the first bandwidth adjusting unit is connected with a first bandwidth adjusting signal, and the switching time of the level control signal is adjusted and controlled based on the first bandwidth adjusting signal.
Optionally, the feedback module further includes a second bandwidth adjusting unit; the second bandwidth adjusting unit is connected between the drain electrode of the fifth NMOS tube and the reference ground; the second bandwidth adjusting unit is connected with a second bandwidth adjusting signal and adjusts and controls the switching time of the level control signal based on the second bandwidth adjusting signal.
Optionally, the first bandwidth adjusting unit includes a seventh PMOS tube and an eighth PMOS tube, and/or the second bandwidth adjusting unit includes an eighth NMOS tube; in the first bandwidth adjusting unit, a source electrode of the seventh PMOS transistor and a source electrode of the eighth PMOS transistor are both connected to the power supply voltage, and a drain electrode of the seventh PMOS transistor and a drain electrode of the eighth PMOS transistor are both connected to the source electrode of the fifth PMOS transistor; the grid electrode of the seventh PMOS tube is connected with high-level voltage; and the grid electrode of the eighth PMOS tube is connected with a first bandwidth regulating and controlling signal.
Optionally, in the second bandwidth adjusting unit, a source electrode of the eighth NMOS transistor is grounded, a gate electrode of the eighth NMOS transistor is connected to the second bandwidth adjusting signal, and a drain electrode of the eighth NMOS transistor is connected to a drain electrode of the fifth NMOS transistor.
Optionally, the first clock generation module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first inverter; the input end of the first inverter is connected with the clock signal; the source electrode of the first NMOS tube is grounded, the grid electrode is connected with the clock signal, and the drain electrode is used as the output end of the first clock generation module; the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the clock signal, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube; the source electrode of the second PMOS tube is connected with a power supply voltage, and the grid electrode of the second PMOS tube is connected with the output end of the first inverter; the source electrode of the third PMOS tube is connected with a power supply voltage, the grid electrode of the third PMOS tube is connected with the level control signal, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube; the source electrode of the second NMOS tube is grounded, the grid electrode is connected with the output end of the first inverter, and the drain electrode is connected with the source electrode of the third NMOS tube; and the grid electrode of the third NMOS tube is connected with the level control signal, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube.
Optionally, the output module includes a fourth inverter; and the input end of the fourth inverter is connected with the second clock signal, and the output end of the fourth inverter is used as the output end of the output module.
To achieve the above and other related objects, the present invention provides a method for regulating bandwidth of a clock signal, which is implemented based on the above clock signal bandwidth regulating circuit, including:
providing a clock signal for the clock signal bandwidth modulation circuit, and inverting and delaying the clock signal to obtain a first clock signal;
inverting the first clock signal to obtain a second clock signal;
setting the clock signal bandwidth modulation circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal; in the wide bandwidth mode, the second clock signal input into the feedback module is invalid, and then a level control signal which is opposite to the first clock signal is output; in the narrow bandwidth mode, delaying a second clock signal input into the feedback module and outputting a level control signal inverted from the first clock signal within a preset time of a rising edge of the delayed second clock signal;
Regulating and controlling the bandwidth of the first clock signal based on the level control signal, and outputting the second clock signal which is in phase opposition to the first clock signal; in the wide bandwidth mode, the bandwidth time of the first clock signal is equal to the bandwidth time of the clock signal; in the narrow bandwidth mode, the bandwidth time of the first clock signal is equal to the preset time; the preset time is smaller than the bandwidth duration of the clock signal.
Optionally, when the second clock signal is obtained based on the inversion of the first clock signal, the clock signal bandwidth regulation method further includes: and providing a delay switch signal, and delaying and inverting the first clock signal to obtain a second clock signal when the delay switch signal is effective.
As described above, the clock signal bandwidth adjusting circuit and the clock signal bandwidth adjusting method of the present invention have the following beneficial effects:
1. according to the clock signal bandwidth regulating circuit and the clock signal bandwidth regulating method, the bandwidth control signal is set, so that the switching of the narrow bandwidth modulation and the wide bandwidth modulation of the clock signal is realized, and the use scene of the clock signal generating circuit is richer.
2. According to the clock signal bandwidth regulating circuit and the clock signal bandwidth regulating method, the delay switch signal is arranged, so that the high level and the low level of the delay switch signal can be directly changed in the subsequent use process, and the output signal of the clock signal bandwidth regulating circuit is directly delayed.
3. According to the clock signal bandwidth regulating circuit and the clock signal bandwidth regulating method, the first bandwidth regulating signal and the second bandwidth regulating signal are arranged, and the high level and the low level of the two signals can be directly changed in the subsequent use process, so that the bandwidth of the clock signal bandwidth regulating circuit when the clock signal bandwidth regulating circuit outputs a narrow bandwidth signal can be further regulated.
4. The clock signal bandwidth regulating circuit and the clock signal bandwidth regulating method have the advantages of simple structure, simplicity and convenience, and good popularization and application.
Drawings
Fig. 1 is a schematic block diagram of a clock signal bandwidth adjusting circuit according to the present invention.
Fig. 2 is a schematic diagram of a clock signal bandwidth adjusting circuit according to the present embodiment.
Fig. 3 is a timing diagram illustrating the present invention in a narrow bandwidth mode.
Fig. 4 is a timing simulation diagram of the present invention in a wide bandwidth mode.
Description of element reference numerals
1. Clock signal bandwidth regulating circuit
11. First clock signal generating module
12. Second clock signal generating module
121. Delay signal generating unit
13. Feedback module
131. First bandwidth adjusting unit
132. Second bandwidth adjusting unit
14. Output module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a clock signal bandwidth adjusting circuit 1, comprising: a first clock signal generation module 11, a second clock signal generation module 12, a feedback module 13 and an output module 14.
As shown in fig. 1, the first clock generating module 11 is connected to the output end of the feedback module 13, and receives a clock signal clk, and is configured to invert and delay the clock signal clk to obtain a first clock signal clkb, and regulate and control the bandwidth of the first clock signal clkb based on a level control signal bk2 output by the feedback module 13.
Specifically, as shown IN fig. 1 and 2, the first clock generation module 11 includes a first PMOS pipe PM1, a second PMOS pipe PM2, a third PMOS pipe PM3, a first NMOS pipe NM1, a second NMOS pipe NM2, a third NMOS pipe NM3, and a first inverter IN1; the input end of the first inverter IN1 is connected to the clock signal clk, and the output end of the first inverter IN1 is connected to the gate of the second PMOS tube PM2 and the gate of the second NMOS tube NM2, respectively. Since the first inverter IN1 generates a certain delay IN the process of inverting the clock signal clk, after a certain time comes from the falling edge of the clock signal (from high level to low level), the output signal of the first inverter IN1 generates a rising edge (from low level to high level), and when the falling edge of the clock signal comes, the second PMOS tube PM2 is turned on and switched to the second NMOS tube NM 2. The source electrode of the first NMOS transistor NM1 is grounded, the gate electrode is connected to the clock signal clk, and the drain electrode is used as the output end (outputting the first clock signal clkb) of the first clock generation module 11; the source electrode of the first PMOS tube PM1 is connected with the drain electrode of the second PMOS tube PM2, the grid electrode is connected with the clock signal clk, and the drain electrode is connected with the drain electrode of the first NMOS tube NM 1; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage vdd, and the grid electrode of the second PMOS tube PM2 is connected with the output end of the first inverter IN1; the source electrode of the third PMOS tube PM3 is connected with the power supply voltage vdd, the grid electrode of the third PMOS tube PM3 is connected with the level control signal bk2, and the drain electrode of the third PMOS tube PM2 is connected with the drain electrode of the second PMOS tube PM 2; the source electrode of the second NMOS tube NM2 is grounded, the grid electrode is connected with the output end of the first inverter IN1, and the drain electrode is connected with the source electrode of the third NMOS tube NM 3; and the grid electrode of the third NMOS tube NM3 is connected with the level control signal bk2, and the drain electrode of the third NMOS tube NM1 is connected with the drain electrode of the first NMOS tube NM 1. The third PMOS transistor PM3 and the third NMOS transistor NM3 form a pair of inverters controlled by the level control signal bk 2: when the level control signal bk2 is at a high level, the third NMOS transistor NM3 is turned on and the third PMOS transistor PM3 is turned off, so as to drive the potential of the first clock signal clkb to be pulled down; when the level control signal bk2 is at a low level, the third NMOS transistor NM3 is turned off and the third PMOS transistor PM3 is turned on, so as to drive the potential of the first clock signal clkb to be raised. Therefore, the third PMOS PM3 and the third NMOS NM3 can be controlled to control the potential of the first clock signal clkb by controlling the level control signal bk 2.
As shown in fig. 1, the second clock generation module 12 receives the first clock signal clkb, and is configured to invert the first clock signal clkb to obtain a second clock signal lclkb.
Specifically, as shown in fig. 1 and 2, the second clock generation module 12 includes a first NAND gate NAND1 and a delay signal generation unit 121; the delay signal generating unit 121 is connected to the first clock signal clkb and the delay switch signal clk_dly, and when the delay switch signal clk_dly is valid, the delay signal generating unit 121 delays the first clock signal clkb and obtains a delay signal dly; when the delay switch signal is invalid, the delay signal dly is invalid; the input end of the first NAND gate NAND1 receives the first clock signal clkb and the output signal of the delay signal generating unit 121, and obtains the second clock signal lclkb based on the signal output by the delay signal generating unit. In this embodiment, the delay switch signal clk_dly is active high. When the delay switch signal clk_dly is at a low level, the delay signal generating unit 121 is not involved in the logic calculation of the first NAND gate NAND1, and the first NAND gate NAND1 directly inverts the first clock signal clkb to obtain a second clock signal lclkb; when the delay switch signal clk_dly is at a high level, the delay signal dly generated by the delay signal generating unit 121 participates in logic calculation of the first NAND gate NAND1, and delays and inverts the first clock signal clkb to obtain a second clock signal lclkb. The delay time of the second clock signal is controlled by a delay signal dly connected to the first NAND gate NAND 1.
As an example, the delay signal generating unit 121 includes a second inverter IN2 and a second NAND gate NAND2; the input end of the second inverter IN2 is connected with the first clock signal clkb; the first input end of the second NAND gate NAND2 is connected with the output end of the second inverter IN2, the second input end of the second NAND gate NAND2 is connected with the delay switch signal clk_dly, the output end of the second NAND gate NAND1 is connected with the first NAND gate NAND1, and the delay switch signal clk_dly is output when the delay switch signal clk_dly is effective. In the present embodiment, the second input terminal of the second NAND gate NAND2 is set to the delay switch signal clk_dly, when the delay switch signal clk_dly maintains a low level, the logic operation value of the second NAND gate NAND2 (i.e., the delay signal clk_dly) is forcedly set to "1" by the delay switch signal clk_dly, and the delay signal dly of the first NAND gate NAND1 due to the reception of a high level is inverted by the first clock signal clkb through the first NAND gate NAND 1; IN this embodiment, when the delay switch signal clk_dly maintains a high level, the logic operation value (i.e., the delay signal dly) of the second NAND gate NAND2 is not forced to be "1" by the delay switch signal clk_dly, but needs to participate IN the logic operation, and the first clock signal clkb is input to the second input end of the first NAND gate NAND1 through the second inverter IN2 and the second NAND gate NAND2, which is equivalent to that the first clock signal clkb is delayed and flipped twice; the first input end of the first NAND gate NAND1 is connected with a first clock signal clkb, the second input end of the first NAND gate NAND1 is connected with the first clock signal clkb which is delayed and turned over twice, and the second clock signal lclkb obtained through logic operation is equivalent to being obtained by delaying and turning over the first clock signal clkb.
In this embodiment, the delay switch signal clk_dly can regulate the delay signal generating unit 121, so as to delay and invert the first clock signal clkb. Therefore, the second clock signal lclkb can be obtained by adjusting the number of delay logic gates participating in the first NAND gate NAND1 in the delay signal generating unit 121, and further delaying and inverting the first clock signal clkb. IN practice, a multistage inverter may be directly added between the second inverter IN2 and the second NAND gate NAND2, thereby increasing the delay time of the delay signal generating unit 121.
As shown in fig. 1, the feedback module 13 receives a bandwidth control signal dff_mode, the first clock signal clkb and the second clock signal lclkb, and sets the clock signal bandwidth regulation circuit 1 to a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal dff_mode; in the wide bandwidth mode, the second clock signal lclkb in the feedback module 13 is disabled, so as to output a level control signal inverted to the first clock signal clkb, so as to maintain the bandwidth of the first clock signal clkb; in the narrow bandwidth mode, the second clock signal lclkb in the feedback module 13 is effective, delays the second clock signal lclkb, and outputs a level control signal inverted from the first clock signal lclb within a preset time of a rising edge of the delayed second clock signal lclk, so as to shorten the bandwidth of the first clock signal clkb.
Specifically, as shown IN fig. 1 and 2, IN the present embodiment, the feedback module 13 includes a third inverter IN3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a third NAND gate NAND3; the input end of the third inverter IN3 is connected to the bandwidth control signal dff_mode (the bandwidth control signal dff_mode is valid at a low level), and the output end of the third inverter IN3 is connected to the gate of the fourth NMOS transistor NM4, the gate of the fifth NMOS transistor NM5, and the gate of the fourth PMOS transistor PM4, respectively; when the bandwidth control signal dff_mode is at a low level, the fourth NMOS tube NM4 is turned on, the fifth NMOS tube NM5 is turned on, and the fourth NMOS tube NM4 is turned off; when the bandwidth control signal dff_mode is at a high level, the fourth NMOS tube NM4 is closed, the fifth NMOS tube NM5 is closed, and the fourth PMOS tube PM4 is turned on; the source electrode of the fourth NMOS tube NM4 is grounded, and the drain electrode is connected with the source electrode of the sixth NMOS tube NM 6; the grid electrode of the sixth NMOS tube NM6 is connected with the second clock signal lclkb, and the drain electrode of the sixth NMOS tube NM7 is connected with the grid electrode of the seventh NMOS tube NM 7; the source electrode of the fifth PMOS tube is connected with a power supply voltage vdd, the grid electrode of the fifth PMOS tube is connected with the second clock signal lclkb, and the drain electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube NM 7; therefore, the sixth NMOS transistor NM6 and the fifth PMOS transistor PM5 form a pair of inverters, and the gates each receive the second clock signal lclkb and output the first inverted signal bk0 at the drain, where the first inverted signal bk0 is opposite to the second clock signal lclkb. The source electrode of the fifth NMOS tube NM5 is grounded, and the drain electrode is connected with the source electrode of the seventh NMOS tube NM 7; the drain electrode of the seventh NMOS tube NM7 is connected with the drain electrode of the sixth PMOS tube PM 6; the source electrode of the sixth PMOS tube PM6 is connected with the power supply voltage vdd, the grid electrode of the sixth PMOS tube PM6 is connected with the grid electrode of the seventh NMOS tube NM7, and the drain electrode of the sixth PMOS tube PM4 is connected with the drain electrode of the fourth PMOS tube PM 4; therefore, the sixth PMOS PM6 and the seventh NMOS NM7 form a pair of inverters, and the first inverted signal bk0 received by the gate outputs a second inverted signal bk1, where the inverted signal bk0 is inverted from the second inverted signal bk 1. The source electrode of the fourth PMOS tube PM4 is connected with the power supply voltage vdd, and the drain electrode is connected with the first input end (namely, the second inverted signal bk 1) of the third NAND gate NAND3; the second input end of the third NAND gate NAND3 is connected to the first clock signal clkb, and the output end is used as the output end (i.e. the level control signal bk 2) of the feedback module 13.
In this embodiment, when the fourth NMOS transistor NM4 is turned on and the fifth NMOS transistor NM5 is turned on, the sixth PMOS transistor PM6 and the fifth PMOS transistor PM5 can sense the level of the second clock signal lclkb, so that the bandwidth control signal dff_mode is set to be effective at a low level, so that the clock signal bandwidth regulating circuit 1 is in a narrow bandwidth mode.
Specifically, as shown in fig. 2, the feedback module 13 further includes a first bandwidth adjusting unit 131; the first bandwidth adjusting unit 131 is disposed between the source of the fifth PMOS PM5 and the supply voltage vdd; the first bandwidth adjusting unit 131 is connected to a first bandwidth adjusting signal PW1, and adjusts the switching time of the level control signal based on the first bandwidth adjusting signal PW 1. In this embodiment, in the narrow bandwidth mode, the first bandwidth adjusting signal PW1 may be set to further increase the time for the fifth PMOS PM5 to sense the second clock signal lclkb, thereby adjusting the logic switching time of the level control signal bk 2.
As an example, in the first bandwidth adjusting unit 131, the source of the seventh PMOS transistor PM7 and the source of the eighth PMOS transistor PM8 are both connected to the supply voltage vdd, and the drain of the seventh PMOS transistor PM7 and the drain of the eighth PMOS transistor PM8 are both connected to the source of the fifth PMOS transistor PM 5; the gate of the seventh PMOS PM7 is connected to a high level voltage (in this embodiment, a voltage is directly connected to make the seventh PMOS always on); the gate of the eighth PMOS transistor PM8 is connected to the first bandwidth adjusting signal PW1, and when the first bandwidth adjusting signal PW1 is low, the speed of the first inverted signal bk0 changing to high level can be increased when the fourth PMOS transistor is turned on, so that the logic switching time of the second inverted signal bk1 and the level control signal bk2 is increased. Therefore, by adjusting the first bandwidth adjusting signal PW1, the bandwidth of the first clock signal clkb generated in the narrow bandwidth mode can be adjusted.
Specifically, as shown in fig. 2, the feedback module 13 further includes a second bandwidth adjusting unit 132; the second bandwidth adjusting unit 132 is connected between the drain of the fifth NMOS transistor NM5 and the reference ground; the second bandwidth adjusting unit 132 is connected to a second bandwidth adjusting signal PW2, and adjusts the switching time of the level control signal based on the second bandwidth adjusting signal PW 2. In this embodiment, in the narrow bandwidth mode, the second bandwidth adjusting signal PW2 may be set to further increase the time for the seventh NMOS NM7 to sense the first inversion signal bk0, thereby adjusting the logic switching time of the level control signal bk 2.
As an example, the second bandwidth adjusting unit 132 includes an eighth NMOS transistor NM8; in the second bandwidth adjusting unit 132, the source of the eighth NMOS transistor NM8 is grounded, the gate is connected to the second bandwidth adjusting signal PW2, and the drain is connected to the drain of the fifth NMOS transistor NM 5. When the second bandwidth adjusting signal PW2 is active high, the speed of the second inverted signal bk1 changing to low level can be increased when the sixth NMOS transistor NM6 is turned on, so that the logic switching time of the level control signal bk2 is increased. Therefore, by adjusting the second bandwidth adjusting signal PW2, the bandwidth of the first clock signal clkb generated in the narrow bandwidth mode is adjusted.
It should be noted that, the sizes of the MOS transistors in the first bandwidth adjusting unit 131 and the second bandwidth adjusting unit 132 may be adjusted as required, so as to regulate the logic switching speed of the level control signal bk 2.
As shown in fig. 1, the output module 14 is connected to the second clock signal lclkb and outputs the second clock signal lclkb.
Specifically, as shown IN fig. 1 and 2, the output module 14 includes a fourth inverter IN4; the input end of the fourth inverter IN4 is connected to the second clock signal lclkb, and the output end is used as the output end of the output module 14.
IN the narrow bandwidth mode, the fourth inverter IN4 of the present embodiment outputs a positive pulse signal; if a negative pulse signal needs to be applied, an inverter may be further provided after the fourth inverter IN 4. In practice, any inverting device can be set for the clock signal after bandwidth modulation according to actual needs, and level inversion is performed so as to be suitable for subsequent circuits, which is not limited by the present invention.
The working principle of the clock signal bandwidth adjusting and controlling circuit 1 of the present invention will be further described with reference to fig. 3 to 4:
as shown in fig. 3, the waveform diagram of each clock signal is shown when the bandwidth control signal dff_mod is low (narrow bandwidth mode), the delay switch signal clk_dly is low (the delay signal generating unit 121 does not start the delay), and the delay switch signal clk_dly is high (the delay signal generating unit 121 starts the delay).
When the delay switch signal clk_dly is at a low level, the first PMOS tube PM1 is turned on when the clock signal clk has a falling edge (from a high level to a low level); the first inverter IN1 toggles the clock signal clk, but due to a certain delay time, the rising edge of the clock signal clk toggles after the first inverter IN1 outputs a low level for a period of time. Therefore, when the clock signal clk has a falling edge, the first PMOS transistor PM1 and the second PMOS transistor PM2 are both turned on, and the first clock signal clkb is pulled up to a high level. The delay switch signal clk_dly is at a low level, the delay signal generating unit 121 does not start delay, and the first clock signal clkb is only inverted through the first NAND gate NAND1, resulting in the second clock signal lclkb still at a low level. The feedback module 13 captures a first clock signal clkb and a second clock signal lclkb. Because the bandwidth control signal dff_mod is at a low level, the fourth NMOS transistor NM4 is turned on, the fifth NMOS transistor NM5 is turned on, and the sixth PMOS transistor is turned off after passing through the third inverter IN 3. Meanwhile, the second clock signal lclkb is at a low level, and the fifth PMOS transistor PM5 and the seventh PMOS transistor PM7 are turned on, so that the first inversion signal bk0 is pulled up to a high level. Thereafter, the seventh NMOS transistor NM7, the fifth PMOS transistor NM5, and the eighth NMOS transistor are turned on by the first inversion signal bk0 of the high level, the second inversion signal bk1 is pulled down to the low level, and then the level control signal is pulled up to the high level through the third NAND gate NAND 3. At this moment, the first inverter IN1 has risen to a high level, the second NMOS transistor NM2 is turned on, and the third NMOS transistor NM2 is turned on, so that the first clock signal clkb is pulled down to a low level, and the third clock signal lclk is outputted as a positive pulse signal through the fourth inverter IN 4.
As can be seen from the timing chart shown in fig. 3, when the first bandwidth adjusting signal PW1 is at a low level and the second bandwidth adjusting signal PW2 is at a high level, the third clock lclk has a bandwidth of 41.2ps; when the first bandwidth regulating signal PW1 is at a high level and the second bandwidth regulating signal PW2 is at a low level, the third clock signal lclk has a bandwidth of 52.2ps; when the first bandwidth regulating signal PW1 is low and the second bandwidth regulating signal PW2 is low, the third clock lclk has a bandwidth of 43.3ps; when the first bandwidth adjusting signal PW1 is at a high level and the second bandwidth adjusting signal PW2 is at a high level, the third clock signal lclk has a bandwidth of 49.9ps. Therefore, the first bandwidth adjusting signal PW1 is set to be low level and the second bandwidth adjusting signal PW2 is set to be low level as required, so as to adjust the bandwidth of the positive pulse signal.
The operation flow of the clock signal bandwidth adjusting circuit 1 is identical to that of the delay switch signal clk_dly and the delay switch signal clk_dly, except that when the delay switch signal clk_dly is at a high level, the delay signal generating unit 121 participates in logic operation, thereby causing time delay of the second clock signal lclkb. When the delay switch signal clk_dly is at a high level, the delay between the clock signal and the first clock signal clkb is 25.76ps, so that different scenarios can be applied by adjusting the delay switch signal clk_dly.
As can be seen from the timing chart shown in fig. 3, when the delay switch signal clk_dly is at a high level, the first bandwidth adjusting signal PW1 is at a low level and the second bandwidth adjusting signal PW2 is at a high level, the third clock signal lclk has a bandwidth of 40.7ps; when the first bandwidth regulating signal PW1 is at a high level and the second bandwidth regulating signal PW2 is at a low level, the third clock signal lclk has a bandwidth of 52.1ps; when the first bandwidth regulating signal PW1 is low and the second bandwidth regulating signal PW2 is low, the third clock lclk has a bandwidth of 42.9ps; when the first bandwidth adjusting signal PW1 is at a high level and the second bandwidth adjusting signal PW2 is at a high level, the third clock signal lclk has a bandwidth of 49.8ps. Therefore, the first bandwidth adjusting signal PW1 is still required to be set to a low level and the second bandwidth adjusting signal PW2 is still required to adjust the bandwidth of the positive pulse signal.
As shown in fig. 4, the waveform diagram of each clock signal when the delay switch signal clk_dly is at a high level (delay signal generation unit 121 starts delay) is a waveform diagram when the bandwidth control signal dff_mod is at a high level (wide pulse mode). Since the bandwidth control signal dff_mod is at a high level, the output end of the third inverter IN3 outputs a low level signal, the fourth NMOS transistor is turned off, the fifth NMOS transistor NM5 is turned off, the fourth PMOS transistor PM4 is turned on, the second inversion signal bk1 is forcibly set to "1" (at a high level), and the second clock signal lclkb input signal does not act on the second inversion signal bk 1. At the third NAND gate NAND3, the second inversion signal bk1 and the first clock signal clkb are logically calculated, so that the logic control time of the pull-up and pull-down of the third NMOS transistor NM3 and the third PMOS transistor PM3 is directly controlled by the first clock signal clkb, so as to maintain the bandwidth of the first clock signal. Therefore, by the bandwidth control signal dff_mod being high, the signal bandwidth of the first clock signal clkb is unchanged and still follows the bandwidth of the clock signal clk.
As can be seen from the timing chart shown in fig. 4, the width of the third clock signal lclk and the width of the clock signal clk are substantially identical, which is 491ps. Since the second clock signal lclkb input does not act in the feedback block 13 at this time, setting the first bandwidth adjusting signal PW1 low and the second bandwidth adjusting signal PW2 do not change the bandwidth of the third clock signal lclk.
The invention also provides a clock signal bandwidth regulation method, which is realized based on the clock signal bandwidth regulation circuit and comprises the following steps:
s1, providing a clock signal for the clock signal bandwidth modulation circuit 1, and inverting and delaying the clock signal to obtain a first clock signal clkb.
S2, obtaining a second clock signal lclkb based on the inversion of the first clock signal clkb.
Specifically, a delay switch signal clk_dly is provided, and when the delay switch signal clk_dly is active (active low in the present embodiment), the first clock signal clkb is delayed and inverted to obtain the second clock signal lclkb.
S3, setting the clock signal bandwidth modulation circuit 1 to be in a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal; in the wide bandwidth mode, the second clock signal lclkb input to the feedback module 13 is deactivated, and a level control signal inverted from the first clock signal clkb is output; in the narrow bandwidth mode, the second clock signal input into the feedback module 13 is delayed and a level control signal inverted from the first clock signal clkb is output for a preset time of a rising edge of the delayed second clock signal.
It should be noted that, the preset time of the delay depends on the delay of the devices in the feedback unit 13, and the size of the devices participating in the delay in the feedback unit 13 can be adjusted based on the need to adjust and control the time.
Specifically, in this embodiment, the clock signal bandwidth adjusting method further includes providing a first bandwidth adjusting signal PW1 and a second bandwidth adjusting signal PW2, and when the broadband control signal dff_mode is at a low level (in a narrow bandwidth mode), adjusting the switching time of the level control signal bk2 based on the first bandwidth adjusting signal PW1 and/or the second bandwidth adjusting signal PW2, thereby adjusting the bandwidth of the first clock signal clkb.
S4, regulating and controlling the bandwidth of the first clock signal clkb based on the level control signal bk2, and further outputting the second clock signal lclkb which is opposite to the first clock signal clkb; in the wide bandwidth mode, the bandwidth time of the first clock signal clkb is equal to the bandwidth time of the clock signal; in the narrow bandwidth mode, the bandwidth time of the first clock signal clkb is equal to the preset time; the preset time is smaller than the bandwidth duration of the clock signal.
In summary, the present invention provides a clock signal bandwidth adjusting circuit and a clock signal bandwidth adjusting method, including: the device comprises a first clock signal generation module, a second clock signal generation module, a feedback module and an output module; the first clock generation module is used for inverting and delaying the clock signal to obtain a first clock signal, and regulating and controlling the bandwidth of the first clock signal based on the level control signal output by the feedback module; the second clock generation module inverts the first clock signal to obtain a second clock signal; the feedback module obtains a level control signal based on the bandwidth control signal, the first clock signal and the second clock signal; setting a clock signal bandwidth regulating circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of a bandwidth control signal; the output module is connected with the second clock signal and outputs the second clock signal. The invention further realizes the switching of the narrow bandwidth modulation and the wide bandwidth modulation of the clock signal by setting the bandwidth control signal, and solves the problem that the conventional bandwidth regulating circuit is single in regulation. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A clock signal bandwidth regulating circuit, the clock signal bandwidth regulating circuit comprising at least: the device comprises a first clock signal generation module, a second clock signal generation module, a feedback module and an output module;
the first clock generation module is connected with the output end of the feedback module, receives a clock signal, is used for inverting and delaying the clock signal to obtain a first clock signal, and regulates and controls the bandwidth of the first clock signal based on a level control signal output by the feedback module;
the second clock generation module receives the first clock signal and is used for inverting the first clock signal to obtain a second clock signal;
the feedback module receives a bandwidth control signal, the first clock signal and the second clock signal respectively, and sets the clock signal bandwidth regulation circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal; in the wide bandwidth mode, a second clock signal in the feedback module is disabled, and then a level control signal which is in phase opposition to the first clock signal is output so as to maintain the bandwidth of the first clock signal; in the narrow bandwidth mode, a second clock signal in the feedback module is effective, delays the second clock signal, and outputs a level control signal which is opposite to the first clock signal within a preset time of a rising edge of the delayed second clock signal so as to shorten the bandwidth of the first clock signal;
The output module is connected with the second clock signal and outputs the second clock signal.
2. The clock signal bandwidth regulating circuit of claim 1, wherein: the second clock signal generation module comprises a first NAND gate and a delay signal generation unit;
the delay signal generating unit is connected with the first clock signal and the delay switch signal, and delays the first clock signal and obtains a delay signal when the delay switch signal is effective; when the delay switch signal is invalid, the delay signal is invalid;
the input end of the first NAND gate receives the first clock signal and the output signal of the delay signal generating unit respectively, and the second clock signal is obtained based on the signal output by the delay signal generating unit.
3. The clock signal bandwidth regulating circuit of claim 2, wherein: the delay signal generating unit comprises a second inverter and a second NAND gate;
the input end of the second inverter is connected with the first clock signal;
the first input end of the second NAND gate is connected with the output end of the second inverter, the second input end of the second NAND gate is connected with a delay switch signal, the output end of the second NAND gate is connected with the first NAND gate, and the delay signal is output when the delay switch signal is effective.
4. The clock signal bandwidth regulating circuit of claim 1, wherein: the feedback module comprises a third inverter, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube and a third NAND gate;
the input end of the third inverter is connected with the bandwidth control signal, and the output end of the third inverter is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth PMOS tube;
the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the sixth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the second clock signal, and the drain electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube;
the source electrode of the fifth PMOS tube is connected with a power supply voltage, the grid electrode of the fifth PMOS tube is connected with the second clock signal, and the drain electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube;
the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube;
the drain electrode of the seventh NMOS tube is connected with the drain electrode of the sixth PMOS tube;
the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube;
The source electrode of the fourth PMOS tube is connected with the power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the first input end of the third NAND gate;
and a second input end of the third NAND gate is connected with the first clock signal, and an output end of the third NAND gate is used as an output end of the feedback module.
5. The clock signal bandwidth regulating circuit of claim 4, wherein: the feedback module further comprises a first bandwidth adjusting unit and/or a second bandwidth adjusting unit;
the first bandwidth adjusting unit is arranged between the source electrode of the fifth PMOS tube and the power supply voltage;
the first bandwidth adjusting unit is connected with a first bandwidth adjusting signal, and the switching time of the level control signal is adjusted and controlled based on the first bandwidth adjusting signal;
and/or the number of the groups of groups,
the second bandwidth adjusting unit is connected between the drain electrode of the fifth NMOS tube and the reference ground;
the second bandwidth adjusting unit is connected with a second bandwidth adjusting signal and adjusts and controls the switching time of the level control signal based on the second bandwidth adjusting signal.
6. The clock signal bandwidth regulating circuit of claim 5, wherein: the first bandwidth adjusting unit comprises a seventh PMOS tube and an eighth PMOS tube, and/or the second bandwidth adjusting unit comprises an eighth NMOS tube;
In the first bandwidth adjusting unit, a source electrode of the seventh PMOS transistor and a source electrode of the eighth PMOS transistor are both connected to the power supply voltage, and a drain electrode of the seventh PMOS transistor and a drain electrode of the eighth PMOS transistor are both connected to the source electrode of the fifth PMOS transistor;
the grid electrode of the seventh PMOS tube is connected with high-level voltage; the grid electrode of the eighth PMOS tube is connected with a first bandwidth regulation signal;
and/or the number of the groups of groups,
in the second bandwidth adjusting unit, the source electrode of the eighth NMOS tube is grounded, the grid electrode is connected with the second bandwidth adjusting signal, and the drain electrode is connected with the drain electrode of the fifth NMOS tube.
7. The clock signal bandwidth regulating circuit of claim 1, wherein: the first clock generation module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a first inverter;
the input end of the first inverter is connected with the clock signal;
the source electrode of the first NMOS tube is grounded, the grid electrode is connected with the clock signal, and the drain electrode is used as the output end of the first clock generation module;
the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the clock signal, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube;
The source electrode of the second PMOS tube is connected with a power supply voltage, and the grid electrode of the second PMOS tube is connected with the output end of the first inverter;
the source electrode of the third PMOS tube is connected with a power supply voltage, the grid electrode of the third PMOS tube is connected with the level control signal, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube;
the source electrode of the second NMOS tube is grounded, the grid electrode is connected with the output end of the first inverter, and the drain electrode is connected with the source electrode of the third NMOS tube;
and the grid electrode of the third NMOS tube is connected with the level control signal, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube.
8. The clock signal bandwidth regulating circuit of claim 1, wherein: the output module includes a fourth inverter;
and the input end of the fourth inverter is connected with the second clock signal, and the output end of the fourth inverter is used as the output end of the output module.
9. A clock signal bandwidth regulation method implemented based on the clock signal bandwidth regulation circuit according to any one of claims 1 to 8, wherein the clock signal bandwidth regulation method comprises:
providing a clock signal for the clock signal bandwidth modulation circuit, and inverting and delaying the clock signal to obtain a first clock signal;
inverting the first clock signal to obtain a second clock signal;
Setting the clock signal bandwidth modulation circuit to be in a narrow bandwidth mode or a wide bandwidth mode under the action of the bandwidth control signal; in the wide bandwidth mode, the second clock signal input into the feedback module is invalid, and then a level control signal which is opposite to the first clock signal is output; in the narrow bandwidth mode, delaying a second clock signal input into the feedback module and outputting a level control signal inverted from the first clock signal within a preset time of a rising edge of the delayed second clock signal;
regulating and controlling the bandwidth of the first clock signal based on the level control signal, and outputting the second clock signal which is in phase opposition to the first clock signal; in the wide bandwidth mode, the bandwidth time of the first clock signal is equal to the bandwidth time of the clock signal; in the narrow bandwidth mode, the bandwidth time of the first clock signal is equal to the preset time; the preset time is smaller than the bandwidth duration of the clock signal.
10. The method for regulating and controlling the bandwidth of a clock signal according to claim 9, wherein: when the second clock signal is obtained based on the inversion of the first clock signal, the clock signal bandwidth regulation method further comprises the following steps:
And providing a delay switch signal, and delaying and inverting the first clock signal to obtain a second clock signal when the delay switch signal is effective.
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