CN103066953A - Continuous pulse generator - Google Patents
Continuous pulse generator Download PDFInfo
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- CN103066953A CN103066953A CN 201210580111 CN201210580111A CN103066953A CN 103066953 A CN103066953 A CN 103066953A CN 201210580111 CN201210580111 CN 201210580111 CN 201210580111 A CN201210580111 A CN 201210580111A CN 103066953 A CN103066953 A CN 103066953A
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Abstract
The invention relates to the technical field of semiconductors, in particular to a continuous pulse generator. The continuous pulse generator comprises a drive-changeable inverter and an inverter chain which is formed by an even number of inverter units which are in series connection. The drive-changeable inverter comprises inverter units, a P-channel metal oxide semiconductor (PMOS) array and an N-channel metal oxide semiconductor (NMOS) array. An overturning and discriminating electrical level of the continuous pulse generator can be adjusted through adjusting the number of metal oxide semiconductor (MOS) transistors in the PMOS array and the NMOS array, the MOS transistors are joined up with an input end of each inverter unit in the drive-changeable inverter, and therefore the purpose of controlling and adjusting a duty ratio of output pulse signals is achieved. The continuous pulse generator is simple in circuit structure, compatible with the existing complementary metal-oxide-semiconductor transistor (CMOS) semiconductor technology, and flexible and convenient to adjust pulse width to achieve optimal transmission signal bandwidths. The continuous pulse generator can provide impulse sequences with controllable frequencies and different pulse widths and adjust transmission signal bandwidths to obtain high-quality signals, thereby enabling a modulation system to be more flexible. The continuous pulse generator can be widely used in the field of wireless communication.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the pulse generator technology.
Background technology
Ultra broadband (Ultra Wideband, UWB) be a kind of with short pulse (0.1nm ~ 1.5ns) transmit, the high wireless communication technology of the bandwidth ratio ratio of centre frequency (radio frequency bandwidth with), it with traffic rate height, good concealment, do not take new frequency spectrum resource three advantages, rise in twentieth century end, and in the field acquisition extensive use such as military, civilian.Compare with arrowband technology such as traditional bluetooth, WLAN, the UWB technology has transmission rate height (hundreds of Mbit/s), strong anti-interference performance, low in energy consumption, the characteristics such as security performance is good, is mainly used in the fields such as indoor communications, high-speed wireless LAN, radar.The FCC of US Federal Communication Committee regulation, civilian UWB spectral range is 3.1 ~ 10.6GHz, and two kinds of patterns are arranged: multiband TD/FDMA and direct frequency band DS-SS.The mode that produces the UWB local oscillation signal has two kinds: Orthodoxy Frequency Division Multiplex OFDM-UWB and impulse radio IR-UWB.Therefore not tolerance frequency skew of OFDM-UWB needs to use the frequency synthesis technique based on phase-locked loop; And in theory tolerance frequency skew of IR-UWB, IEEE 802.15.4a standard adopts IR-UWB, owing to adopt the burst transfer mode, greatly reduces system power dissipation, is applied to short distance, low power consumption wireless network.
The IR-UWB technology directly transmits and receives pulse communication, utilizes nanosecond to picosecond to get the burst pulse the transmission of data, has the transmission rate height, ability of anti-multipath is strong, fail safe good and the plurality of advantages such as accurate stationkeeping ability.And in the IR-UWB technology, need pulse generator to produce to satisfy the continuous impulse waveform of circuit working requirement, thereby pulse generator is one of its important parts.
In this technical field, three the key technical indexes weighing the UWB pulse generator are: impulse output amplitude, pulse repetition frequency, impulse waveform.In the prior art, the method that produces IR-UWB work required pulse is a lot, and tradition becomes the primary method that people pay close attention to based on the pulse generator of triode avalanche effect with its advantage that is easy to realize.Pass through at present the methods such as multitube series, parallel, Marx matrix to the continuous Improvement of this quasi-tradition pulse generator, obtain certain progress, the key technical indexes can reach: pulse amplitude is 8.25V, pulse repetition frequency 50MHz, impulse waveform are mainly the approximate Gaussian arteries and veins, but with the UWB technical standard also there are larger gap in the requirement of the Emission Mask condition paired pulses waveform of high pulse repetition frequency 480MHz and FCC.
And along with the development of semiconductor technology, the circuit that is used at present producing the UWB pulse in the prior art mostly is greatly the high-speed electronic components of all solid state type, such as photoelectric device and high-speed electronic components etc.The IR-UWB method that required continuous impulse produces of working roughly can be divided into two classes: photoelectric method and electronic method.Photoelectric method can obtain ps(10
-12S) the UWB pulse of level width, and high conformity is that class methods of using future are arranged most, but still locates at present conceptual phase.Electronic method utilizes the optimum breakdown characteristics of the reverse snowslide of semiconductor PN and high-speed figure combinational logic circuit to produce the following UWB pulse of 1ns, because its circuit structure is simply studied widely and used.
Electronic method of the prior art mainly can divide again three kinds: the first is to utilize the warfare of high-speed cmos logic gates to produce the UWB pulse, this mode can produce approximate each rank differential Gaussian pulse, but output pulse amplitude is low, is generally hundreds of mV, and the circuit static power consumption is larger; The second is that traditional avalanche breakdown conducting control capacitance discharge based on BJT forms the UWB pulse.This class pulse generator output pulse amplitude is large, the circuit static power consumption approaches zero, pulse duration is little and easy control, but generally can only produce the approximate Gaussian pulse, the frequency spectrum DC component is large, needs just can meet FCC Emission Mask standard through strict Waveform shaping; The third is to utilize various high-speed electronic components, sows integrated circuits such as field effect transistor logical circuit etc. such as tunnel diode, step recovery diode, pulsed-discharge tube, arsenic.
In addition, also occurred utilizing the competition of digital circuit-risk principle to produce the UWB ultra-narrow pulse in the prior art, the UWB pulse-generator circuit of design as depicted in figs. 1 and 2.Fig. 1 is for carrying out XOR with one tunnel clock signal and same clock signal through being input to XOR gate behind the delay line.According to the XOR gate logical relation, only when the rising edge of clock signal and trailing edge, two incoming levels are just different, this moment gate circuit output logic high level " 1 ", two incoming levels are identical At All Other Times, gate circuit output logic low level " 0 ".The amount of delay of adjusting delay line just can change the phase difference of two input signals, and the output width is subjected to amount of delay control high level pulse.Obtain the UWB pulse by simple control to the delay line amount of delay, again by processing of circuit such as shaping pulse, amplifications, obtain the satisfactory pulse signals of index such as pulse duration, amplitude.
According to the AND circuit logic, when two inputs all are logic high, the output high level.As shown in Figure 2, clock signal be input to inverter and with an input of door, because the delay of inverter and circuit self, when the rising edge output of clock signal, the logic high of utmost point short time appears simultaneously with two inputs of door, namely with pulse of door output, and all the other times because always have one to be logic level with door two inputs, thereby output all is logic low.In the circuit design process, driving source should be selected the as far as possible clock signal of weak point of rising time, guarantees the accurate control of retardation, and the resistance matching problem between the chip also needs to cause enough attention.The limitation of this method is the realization of high speed logic, the control of accurate phase delay and control and the raising of pulse amplitude, and simultaneously, the price of this high-speed chip reaches the extremely level of using, and also needs some times.
Yet according to foregoing description as can be known, the method for the conventional generation IR-UWB pulse of adopting is by the performance of device own, according to set communication requirement design in the prior art, and pulse duration is determined according to the pulse-generator circuit structure.In the IR-UWB wireless communication technology, its signal modulation system mainly is that modulate paired pulses amplitude and the position of pulse on time shaft, and the regulating impulse width can change the bandwidth of signal transmission.Under these circumstances, demand for the IR-UWB communication system, need to adjust flexibly pulse duration conveniently to reach optimum signal transmission bandwidth, Given this, can seem particularly important according to the continuous impulse generator of the required bandwidth free adjustment of signal transmission pulse duration.
Summary of the invention
Technology to be solved by this invention is, a continuous impulse generator is provided, can be according to the required bandwidth free adjustment of signal transmission pulse duration.
For solving the problems of the technologies described above, the invention provides a continuous impulse generator, comprise the oscillator feedback control loop, described oscillator feedback control loop comprises that the variable inverter of driving and even number of inverters units in series form chain of inverters; The variable inverter of described driving comprises: inverter module; The PMOS array is connected between the inverter module output of working power and the variable inverter of described driving; The NMOS array is connected between the inverter module output and ground of the variable inverter of described driving.
As optional technical scheme, the variable inverter of described driving also comprises: the second current source that the first current source that the PMOS transistor forms and nmos pass transistor form; Described inverter module is the CMOS inverter module, comprise a PMOS transistor and the first nmos pass transistor, a described PMOS transistor be connected the source electrode of nmos pass transistor and connect respectively the first current source and the second current source, grid links together as the input of described inverter module, and drain electrode links together as the output of described inverter module.
Further, comprise 2 or 4 inverter modules in the chain of inverters that the even number of inverters units in series forms, and each inverter module characteristic size equates all with driving force.
Further, described continuous impulse generator also comprises frequency control module, and described frequency control module comprises two outputs, connects respectively described first, second current source grid, is used for regulating the frequency of continuous impulse generator.
As optional technical scheme, described PMOS array comprises n PMOS transistor, and wherein n 〉=1 and n are integer; The transistorized source electrode of described each PMOS all connects working power, and drain electrode all connects the variable inverter output of described driving, and grid all connects respectively the input of working power and the variable inverter of described driving by two switches.
Further, the transistorized channel length of each PMOS equates with the transistorized channel length of a PMOS in the variable inverter of described driving in the described PMOS array; PMOS transistor M in the described PMOS array
PiChannel width be in the variable inverter of described driving a PMOS transistor channel width 2
I-1Doubly, wherein: 1≤i≤n and i are integer.
Further, in the described PMOS array, when the switch conduction that is connected with the variable inverter input of driving, the switch disconnection that is connected with working power, corresponding PMOS transistor selection; Otherwise corresponding PMOS transistor gating not then.
As optional technical scheme, described NMOS array comprises m nmos pass transistor, and wherein m 〉=1 and m are integer; The source grounding of described each nmos pass transistor, drain electrode all connects the output of the variable inverter of described driving, and grid all connects respectively input and the ground of the variable inverter of described driving by two switches.
Further, the channel length of each nmos pass transistor equates with the channel length of the first nmos pass transistor in the variable inverter of described driving in the described NMOS array; Nmos pass transistor M in the described NMOS array
NlChannel width be in the variable inverter of described driving the first nmos pass transistor channel width 2
L-1Doubly, wherein: 1≤l≤m and l are integer.
Further, in the described NMOS array, when the switch conduction that is connected with the variable inverter input of driving, the switch disconnection that is connected with ground, corresponding nmos pass transistor gating; Otherwise corresponding nmos pass transistor gating not then.
As optional technical scheme, each switch in described PMOS array and the described NMOS array all is connected with digital input control signal, be used for controlling the strobe state of each nmos pass transistor in each PMOS transistor of described PMOS array and the NMOS array, to regulate the duty ratio of continuous impulse generator.
As optional technical scheme, PMOS number of transistors n equates with nmos pass transistor quantity m in the described NMOS array in the described PMOS array.
Continuous impulse generator provided by the invention changes PMOS transistor and the nmos pass transistor quantity that access drives inverter module in the variable inverter by switch, differentiates level thereby change its upset, to realize the adjustment of pulse signals duty ratio.Simultaneously, by frequency control module control current source grid terminal voltage, to regulate the charging and discharging capabilities that drives inverter module in the variable inverter, thereby realize its constant work and variable frequency work under different frequency, can produce the continuous impulse that is fixed on the different frequency and can the free adjustment pulse duration, but also can produce the free adjustment pulse duration and can adjust pulse at the continuous impulse of time shaft position by frequency conversion.
Compared with prior art, continuous impulse generator circuit structure provided by the invention is simple, fully compatible with existing cmos semiconductor technique, and can adjust more flexible, more easily pulse duration conveniently to reach optimum signal transmission bandwidth, the pulse train that frequency is controlled and pulsewidth is different is provided, adjusts the bandwidth of signal transmission, obtain high-quality signal, so that modulation system is more flexible, be widely used in wireless communication field.
Description of drawings
Fig. 1 is that the available technology adopting XOR gate produces UWB impulse circuit structure and pulse signal schematic diagram;
Fig. 2 is that available technology adopting produces UWB impulse circuit structure and pulse signal schematic diagram with door;
Fig. 3 is continuous impulse generator architecture block diagram provided by the invention;
Fig. 4 is continuous impulse generator circuit structure schematic diagram provided by the invention;
Fig. 5 is continuous impulse frequency generator control module electrical block diagram provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing embodiments of the present invention are described in further detail.Those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.In addition, if no special instructions, " connection " related in this embodiment all refers to the electricity annexation.
Fig. 3 is continuous impulse generator architecture block diagram provided by the invention.
As shown in Figure 3, the continuous impulse generator that this embodiment provides comprises: oscillator feedback control loop 100, described oscillator feedback control loop 100 comprise that the variable inverter 100a of driving and even number of inverters units in series form chain of inverters 100b; Wherein: drive variable inverter 100a and comprise: inverter module 101; PMOS array 200 is connected in working power V
DdAnd between inverter module 101 outputs of the variable inverter 100a of described driving; NMOS array 200 is connected between inverter module 101 outputs and ground GND of the variable inverter 100a of described driving.
In the continuous impulse generator that this embodiment provides, as shown in Figure 3, chain of inverters 100b is formed by the even number of inverters units in series, and wherein, the characteristic size of each inverter module and driving force all equate.
In this embodiment, the input of chain of inverters 100b links to each other with the output of inverter module 101 among the variable inverter 100a of driving, the output of chain of inverters 100b links to each other with the input of inverter module 101 among the variable inverter 100a of driving, consist of an oscillator feedback control loop that has the odd number inverter module, can realize the basic function of ring oscillator vibration.
As most preferred embodiment, chain of inverters 100b comprises the inverter module of 2 or 4 head and the tail series connection.
Fig. 4 is continuous impulse generator circuit structure schematic diagram provided by the invention.
In the continuous impulse generator that this embodiment provides, as shown in Figure 4, drive variable inverter 100a and also comprise: the first current source I that the PMOS transistor forms
1The second current source I with nmos pass transistor formation
2Inverter module 101 is the CMOS inverter module, comprises a PMOS transistor M
P0With the first nmos pass transistor M
N0, a described PMOS transistor M
P0With the first nmos pass transistor M
N0Source electrode connect respectively the first current source I
1With the second current source I
2, that is: a PMOS transistor M
P0Source electrode link to each other the first nmos pass transistor M with a transistorized drain electrode of the PMOS as voltage-controlled current source
N0Source electrode link to each other with a drain electrode as the nmos pass transistor pipe of voltage-controlled current source.A described PMOS transistor M
P0With the first nmos pass transistor M
N0Grid link together as the input of described inverter module 101, the drain electrode link together as the output of described inverter module 101.
As preferred embodiment, as shown in Figure 3, Figure 4, this continuous impulse generator also comprises frequency control module 400 wherein: described frequency control module 400 comprises two outputs, all connect the variable inverter 100a of described driving, be used for changing the charging and discharging capabilities that drives variable inverter 100a inverter module, realize the adjusting to frequency of oscillation.
Fig. 5 is this embodiment medium frequency control module 400 electrical block diagrams.
In this embodiment, as shown in Figure 5, frequency control module 400 comprises the two-stage current mirroring circuit, and wherein, MOS transistor M1, M2, M3 grid link to each other, and source electrode all connects working power V
Dd, and the grid of MOS transistor M1 and drain electrode link together, and forms the first current mirroring circuit; And MOS transistor M4, M5 grid link to each other, source grounding GND, and drain electrode connects respectively the drain electrode of MOS transistor M2, M3, and the grid of MOS transistor M4 and drain electrode link together, and forms the second current mirroring circuit.Described MOS transistor M1 drain electrode is by a controllable current source I
3GND is connected with ground, this controllable current source I
3The first current mirroring circuit that forms for MOS transistor M1, M2, M3 provides reference current, and the output current of MOS transistor M2 drain electrode provides reference current for the second current mirroring circuit that MOS transistor M4, M5 form.
In this embodiment, such as Fig. 4, shown in Figure 5, the grid voltage P-bias of MOS transistor M1, M2, M3 is connected to and drives formation the first voltage-controlled current source I among the variable inverter 100a as an output of frequency control module 400
1The PMOS transistor gate; The grid voltage N-bias of MOS transistor M4, M5 is connected to and drives formation the second voltage-controlled current source I among the variable inverter 100a as the another output of frequency control module 400
2The nmos pass transistor grid.As most preferred embodiment, MOS transistor M1, M2, M3 are the PMOS transistor, and MOS transistor M4, M5 are nmos pass transistor.
In this embodiment, frequency control module 400 according to the required frequency of oscillation of the output frequency of oscillator feedback control loop 100 and practical application to driving first, second current source I of variable inverter 100a
1, I
2Adjust, change the charging and discharging capabilities that drives inverter module 101 among the variable inverter 100a, realize the adjusting to frequency of oscillation.
In this embodiment, drive the first current source I among the variable inverter 100a
1With the second current source I
2Main Function be control the one PMOS transistor M
P0With the first nmos pass transistor M
N0The charging and discharging currents of the inverter module that consists of is by controlling as first, second voltage-controlled current source I
1, I
2The PMOS transistor and the grid voltage of nmos pass transistor, can change voltage-controlled current source I
1, I
2Size of current, pour into by a PMOS transistor M thereby change
P0With the first nmos pass transistor M
N0The size of the inverter module charging and discharging currents that consists of, thereby the frequency of oscillation of regulating whole oscillator feedback control loop 100 are to reach the purpose of regulating the continuous impulse frequency generator.
In the continuous impulse generator that this embodiment provides, as shown in Figure 3, Figure 4, the variable inverter 100a of described driving also comprises and is connected in working power V
DdAnd the PMOS array 200 between inverter module 101 outputs of the variable inverter 100a of described driving.Described PMOS array 200 comprises n PMOS transistor, and wherein n 〉=1 and n are integer; Each PMOS transistor M of described formation PMOS array 200
P1~ M
PnSource electrode all connect working power V
Dd, drain electrode all connects the variable inverter 100a of described driving output, and grid passes through switch S respectively
P1~ S
PnAnd S
P1' ~ S
Pn' connection working power V
DdInput with the variable inverter 100a of described driving.
In this embodiment, in the described PMOS array 200, when the switch S that is connected with the variable inverter 100a input of driving
PiConducting, with working power V
DdThe switch S that connects
Pi' when disconnecting, corresponding PMOS transistor M
PiGating; Otherwise, when the switch S that is connected with the variable inverter 100a input of driving
PiDisconnect, with working power V
DdThe switch S that connects
Pi' during conducting, corresponding PMOS transistor M
PiGating not.Wherein: 1≤i≤n and n are integer.
With PMOS transistor M in the PMOS array 200
P1Gating and PMOS transistor M
P2Be not gated for example.When circuit working need to be selected PMOS transistor M in the PMOS array 200
P1When access drives variable inverter 100a, switch S
P1Closed conducting is with PMOS transistor M
P1The grid termination enter to drive the input of variable inverter 100a, and Simultaneous Switching S
P1' disconnect, guarantee PMOS transistor M
P1Normal operation; And unchecked PMOS transistor M in the PMOS array 200
P2, then must be with S
P2Disconnect S
P2' closed conducting, so that PMOS transistor M
P2Disconnect with the input that drives variable inverter 100a, and with PMOS transistor M
P2Grid termination working power V
DdThereby, turn-off PMOS transistor M
P2, guarantee that circuit is stable.
In the continuous impulse generator that this embodiment provides, as shown in Figure 3, Figure 4, the variable inverter 100a of described driving also comprises the NMOS array 300 between inverter module 101 outputs that are connected in the variable inverter 100a of described driving and the ground GND.Described NMOS array 300 comprises m nmos pass transistor, and wherein m 〉=1 and m are integer; Each nmos pass transistor M of described formation NMOS array 300
N1~ M
NmSource grounding GND, the drain electrode all connect the variable inverter 100a of described driving output, grid passes through switch S respectively
N1~ S
NmAnd S
N1' ~ S
Nm' connect input and the ground GND of the variable inverter 100a of described driving.
In this embodiment, in the described NMOS array 300, when the switch S that is connected with the variable inverter 100a input of driving
NlConducting, the switch S that is connected with ground GND
Pl' when disconnecting, corresponding nmos pass transistor M
NlGating; Otherwise, when the switch S that is connected with the variable inverter 100a input of driving
NlThe switch S that disconnect, is connected with ground GND
Nl' during conducting, corresponding nmos pass transistor M
NlGating not.Wherein: 1≤l≤m and l are integer.
With nmos pass transistor M in the NMOS array 300
N2Gating and nmos pass transistor M
N1Be not gated for example.When circuit working need to be selected nmos pass transistor M in the NMOS array 300
N2When the pipe access drives variable inverter 100a, switch S
N2Closed conducting is with nmos pass transistor M
N2The grid termination enter to drive the input of variable inverter 100a, and Simultaneous Switching S
N2' disconnect, guarantee nmos pass transistor M
N2Normal operation.In like manner, unchecked NMOS pipe M in the NMOS array 300
N1, then must be with switch S
N1Disconnect, and switch S
N1' closed conducting, so that nmos pass transistor M
N1Disconnect with the input that drives variable inverter 100a, and with nmos pass transistor M
N1Grid end ground connection GND, thereby turn-off nmos pass transistor M
N1, guarantee that circuit is stable.
In this embodiment, by the switch S in the PMOS array 200
p(S
P1~ S
Pn, S
P1' ~ S
Pn') with NMOS array 300 in switch S
n(S
N1~ S
Nm, S
N1' ~ S
Nmn') closed conducting and disconnection, change quantity and size that access drives PMOS transistor and the nmos pass transistor of variable inverter 100a, differentiate level thereby change the upset that drives variable inverter 100a, thereby realize the adjusting to continuous impulse generator duty ratio.Wherein, each switch S in the PMOS array 200
p(S
P1~ S
Pn, S
P1' ~ S
Pn') with NMOS array 300 in each switch S
n(S
N1~ S
Nm, S
N1' ~ S
Nmn') the external digital input signal control of on off state by its connection.
In this embodiment, acting as of PMOS array 200 and NMOS array 300: change to the ability that drives the charge and discharge of inverter module 101 output parasitic capacitances among the variable inverter 100a according to system requirements, change the duty ratio of output pulse signal.
In order to realize the able to programme of pulse signal duty cycle adjustment, as most preferred embodiment, each PMOS transistor M in the described PMOS array 200
P1~ M
PnChannel length and described inverter module 101 in a PMOS transistor M
P0Channel length equate; PMOS transistor M in the described PMOS array 200
PiChannel width be a PMOS transistor M in the described inverter module 101
P02 of channel width
I-1Doubly, wherein: 1≤i≤n and i are integer.That is: in the PMOS array 200, PMOS transistor M
P1Channel width and a PMOS transistor M
P0Channel width equate; PMOS transistor M
P2Channel width be a PMOS transistor M
P02 times of channel width; PMOS transistor M
P3Channel width be a PMOS transistor M
P04 times of channel width ... by that analogy, PMOS transistor M
PnFor channel width be a PMOS transistor M
P02
N-1Doubly.
In like manner, each nmos pass transistor M in the described NMOS array 300
N1~ M
NmChannel length and described inverter module 101 in the first nmos pass transistor M
N0Channel length equate; Nmos pass transistor M in the described NMOS array 300
NiChannel width be the first nmos pass transistor M in the described inverter module 101
N02 of channel width
L-1Doubly, wherein: 1≤l≤m and l are integer.That is: in the NMOS array 300, nmos pass transistor M
N1Channel width and the first nmos pass transistor M
N0Channel width equate; Nmos pass transistor M
N2Channel width be the first nmos pass transistor M
N02 times of channel width; Nmos pass transistor M
N3Channel width be the first nmos pass transistor M
N04 times of channel width ... by that analogy, nmos pass transistor M
NmFor channel width be the first nmos pass transistor M
N02
M-1Doubly.
Can relatively access less metal-oxide-semiconductor like this, to realize the duty cycle adjustment of maximum magnitude.
As most preferred embodiment, PMOS number of transistors n equates with nmos pass transistor quantity m in the described NMOS array 300 in the described PMOS array 200, i.e. n=m.At this moment, by the quantity control of gate transistor in PMOS array 200 and the NMOS array 300, can realize that the full scale of output pulse signal duty ratio is regulated, the adjusting with maximum is dynamic.Wherein, all switches come the control switch state by the digital input control signal of outside input in PMOS array 200 and the NMOS array 300, realize the gating access control of MOS transistor, and transistorized concrete quantity in PMOS array 200 and the NMOS array 300 is determined as design parameter flexibly according to duty cycle adjustment scope and degree of regulation that system is required.
The continuous impulse generator that this embodiment provides is connected across working power V by adjusting
DdAnd drive the PMOS array 200 between the inverter module 101 among the variable inverter 100a and be connected across ground GND and regulate the upset that drives inverter module 101 among the variable inverter 100a with the PMOS transistor that drives the 300 access inverter modules of the NMOS array between the inverter module 101,101 inputs among the variable inverter 100a and nmos pass transistor quantity and differentiate level, thereby realize controlling and the purpose of regulation output pulse signal duty ratio.
Simultaneously, drive current source grid terminal voltage among the variable inverter 100a by frequency control module 400 controls, to regulate the charging and discharging capabilities that drives variable inverter 100a, thereby realize its constant work and variable frequency work under different frequency, can produce the continuous impulse that is fixed on the different frequency and can the free adjustment pulse duration, but also can produce the free adjustment pulse duration and can adjust pulse at the continuous impulse of time shaft position by frequency conversion.
Compared with prior art, the continuous impulse generator circuit structure that this embodiment provides is simple, fully compatible with existing cmos semiconductor technique, and can adjust more flexible, more easily pulse duration conveniently to reach optimum signal transmission bandwidth, the pulse train that frequency is controlled and pulsewidth is different is provided, adjusts the bandwidth of signal transmission, obtain high-quality signal, so that modulation system is more flexible, be widely used in wireless communication field.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (12)
1. a continuous impulse generator is characterized in that, comprises the oscillator feedback control loop, and described oscillator feedback control loop comprises the chain of inverters that drives variable inverter and the formation of even number of inverters units in series, and the variable inverter of described driving comprises:
Inverter module;
The PMOS array is connected between the inverter module output of working power and the variable inverter of described driving;
The NMOS array is connected between the inverter module output and ground of the variable inverter of described driving.
2. continuous impulse generator according to claim 1 is characterized in that, the variable inverter of described driving also comprises: the second current source that the first current source that the PMOS transistor forms and nmos pass transistor form; Described inverter module is the CMOS inverter module, comprise a PMOS transistor and the first nmos pass transistor, a described PMOS transistor be connected the source electrode of nmos pass transistor and connect respectively the first current source and the second current source, grid links together as the input of described inverter module, and drain electrode links together as the output of described inverter module.
3. continuous impulse generator according to claim 2 is characterized in that, comprises 2 or 4 inverter modules in the chain of inverters that described even number of inverters units in series forms, and the characteristic size of each inverter module is all equal with driving force.
4. according to claim 2 or 3 described continuous impulse generators, it is characterized in that described continuous impulse generator also comprises frequency control module, described frequency control module comprises two outputs, connect respectively described first, second current source grid, be used for regulating the frequency of continuous impulse generator.
5. continuous impulse generator according to claim 4 is characterized in that, described PMOS array comprises n PMOS transistor, and wherein n 〉=1 and n are integer; The transistorized source electrode of described each PMOS all connects working power, and drain electrode all connects the variable inverter output of described driving, and grid all connects respectively the input of working power and the variable inverter of described driving by two switches.
6. continuous impulse generator according to claim 5 is characterized in that, the transistorized channel length of each PMOS equates with the transistorized channel length of a PMOS in the variable inverter of described driving in the described PMOS array; PMOS transistor M in the described PMOS array
PiChannel width be in the variable inverter of described driving a PMOS transistor channel width 2
I-1Doubly, wherein: 1≤i≤n and i are integer.
7. continuous impulse generator according to claim 5 is characterized in that, in the described PMOS array, and when the switch conduction that is connected with the variable inverter input of driving, the switch disconnection that is connected with working power, corresponding PMOS transistor selection; Otherwise corresponding PMOS transistor gating not then.
8. continuous impulse generator according to claim 4 is characterized in that, described NMOS array comprises m nmos pass transistor, and wherein m 〉=1 and m are integer; The source grounding of described each nmos pass transistor, drain electrode all connects the output of the variable inverter of described driving, and grid all connects respectively input and the ground of the variable inverter of described driving by two switches.
9. continuous impulse generator according to claim 8 is characterized in that, the channel length of each nmos pass transistor equates with the channel length of the first nmos pass transistor in the variable inverter of described driving in the described NMOS array; Nmos pass transistor M in the described NMOS array
NlChannel width be in the variable inverter of described driving the first nmos pass transistor channel width 2
L-1Doubly, wherein: 1≤l≤m and l are integer.
10. continuous impulse generator according to claim 8 is characterized in that, in the described NMOS array, and when the switch conduction that is connected with the variable inverter input of driving, the switch disconnection that is connected with ground, corresponding nmos pass transistor gating; Otherwise corresponding nmos pass transistor gating not then.
11. the described continuous impulse generator of any one according to claim 5 ~ 10, it is characterized in that, each switch in described PMOS array and the described NMOS array all is connected with digital input control signal, be used for controlling the strobe state of each nmos pass transistor in each PMOS transistor of described PMOS array and the NMOS array, to regulate the duty ratio of continuous impulse generator.
12. the described continuous impulse generator of any one is characterized in that according to claim 5 ~ 10, PMOS number of transistors n equates with nmos pass transistor quantity m in the described NMOS array in the described PMOS array.
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