CN110391802B - Frequency shift Gaussian pulse generating circuit based on digital logic realization - Google Patents

Frequency shift Gaussian pulse generating circuit based on digital logic realization Download PDF

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CN110391802B
CN110391802B CN201910502090.7A CN201910502090A CN110391802B CN 110391802 B CN110391802 B CN 110391802B CN 201910502090 A CN201910502090 A CN 201910502090A CN 110391802 B CN110391802 B CN 110391802B
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nmos transistor
output end
pulse
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CN110391802A (en
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朱樟明
刘马良
高吉
肖金海
杨银堂
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/282—Transmitters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

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  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a frequency shift Gaussian pulse generating circuit based on digital logic implementation.A first input end of a delay module is connected with a delay control signal output end, and a second input end of the delay module is connected with a trigger signal output end; the output end of the delay module is connected with the first input end of the pulse generation logic module, the output end of the delay module is connected with the first input end of the pulse combination logic, and the output end of the pulse combination logic is connected with the output end VoutConnecting; the input end of the decoding module is connected with the control signal output end, the first output end of the decoding module is connected with the second input end of the pulse generation logic module, and the second output end of the decoding module is connected with the second input end of the pulse combination logic unit. The method has the advantages of low power consumption, small area and large adjusting range.

Description

Frequency shift Gaussian pulse generating circuit based on digital logic realization
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a frequency-shift Gaussian pulse generating circuit based on digital logic implementation.
Background
The ultra-wideband pulse radar system can realize the functions of ranging, positioning, imaging and the like by transmitting ultra-wideband pulse signals and processing echo signals. The ultra-wideband pulse signal is closely related to the system performance, and the signal bandwidth determines the detection precision. The ultra-wideband pulse signal is realized mainly by two modes, namely a baseband narrow pulse mode and a carrier modulation mode. In general, the baseband narrow pulse form mainly includes a gaussian pulse and its derivative waveforms, an early pulse waveform, a rectangular wave, and the like. The carrier modulation based ultra-wideband pulse signal is mainly to modulate the amplitude of a sinusoidal carrier by using various envelope signals, and the commonly used envelope signals mainly comprise rectangular wave and gaussian pulse. Compared with a baseband narrow pulse form, the carrier modulation-based ultra-wideband pulse signal can select a proper frequency band by adjusting carrier frequency, and spectrum resources can be flexibly utilized.
At present, an on-chip frequency shift Gaussian pulse signal generation mode realized based on a CMOS (complementary metal oxide semiconductor) process mainly adopts an arbitrary waveform generator, and although the mode can generate waveforms with arbitrary shapes, the mode has large area and power consumption and is not beneficial to the application of an ultra-wideband pulse radar system with low power consumption and high integration level. Generally, the ultra-wideband pulse signal can be realized by combining the single pulses by using digital logic, but the traditional ultra-wideband pulse signal realized based on the digital logic has the envelope of a rectangular wave and has larger side lobes, and meanwhile, the performance of the power amplifier is deteriorated by higher harmonics contained in the wave form.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a frequency-shifted gaussian pulse generating circuit based on digital logic implementation. The technical problem to be solved by the invention is realized by the following technical scheme:
a control signal output terminal for transmitting an external control signal B1B0；
A delay control signal output terminal for transmitting the delay control signal Vc；
The Trigger signal output end is used for sending a Trigger signal Trigger;
a decoding module, an input end of the decoding module is connected with the control signal output end, and the decoding module is used for receiving the external control signal B1B0And for the external control signal B1B0Decoding to obtain a decoding control signal;
a delay module, a first input end of the delay module is connected with the delay control signal output end, a second input end of the delay module is connected with the trigger signal output end, and the delay module is used for receiving the delay control signal VcThe Trigger signal Trigger is set and the delay control signal V is setcUnder the control of the Trigger signal Trigger, delaying the Trigger signal Trigger to obtain a delayed Trigger signal;
a pulse generation logic module, a first input end of the pulse generation logic module is connected with an output end of the delay module, a second input end of the pulse generation logic module is connected with a first output end of the decoding module, and the pulse generation logic module is used for generating a single pulse signal according to the delay trigger signal and the decoding control signal;
a pulse combinational logic circuit module, a first input end of the pulse combinational logic circuit module being connected with an output end of the pulse generation logic module, a second input end of the pulse combinational logic circuit module being connected with a second output end of the decoding module, the pulse combinational logic circuit module being configured to combine the single pulse signals according to the decoding control signal to obtain a frequency-shifted gaussian pulse signal;
output end VoutSaid output terminal VoutConnected with the output end of the pulse combination logic circuit module, and the output end VoutFor outputting the frequency-shifted gaussian pulse signal.
In one embodiment of the present invention, the decoding module is a 2-4 decoding circuit.
In one embodiment of the present invention, the delay module includes 2i +1 delay units, i is 0,1,2,3, 4;
the 2i +1 delay units are sequentially cascaded;
and the control signal input ends of the 2i +1 delay units are connected with the delay control signal output end.
In one embodiment of the present invention, the delay unit includes: a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and a power supply end VDD;
the gates of the PMOS transistor MP1 and the NMOS transistor MN1 are used as the signal input ends of the delay unit; the source electrode of the PMOS tube MP1 is connected with the power supply end VDD, the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN2, and the drain electrode of the PMOS tube MP1 is also connected with the input end of the first inverter INV 1;
the gate of the NMOS transistor MN2 serves as a signal input end of the delay unit, the source of the NMOS transistor MN1 is grounded, the drain of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN2, and the drain of the NMOS transistor MN2 is connected to the input end of the first inverter INV 1;
the drain electrodes of the PMOS transistor MP2 and the NMOS transistor MN3 are connected to the output end of the first inverter INV1, the source electrodes of the PMOS transistor MP2 and the NMOS transistor MN3 are connected to the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 serves as the second output end of the delay unit, the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, the output end INV2 of the second inverter is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 serves as the first output end of the delay unit.
In one embodiment of the present invention, the pulse generating unit includes: a first nand gate, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an NMOS transistor MN4, and a PMOS transistor MP 3;
a first input end of the first nand gate is connected with the trigger signal output end, a second input end of the first nand gate is connected with a second output end of the delay unit, a third input end of the first nand gate is connected with a first output end of the decoding module, an output end of the first nand gate is connected with an input end of the fifth inverter INV5, and an output end of the first nand gate is further connected with drains of the PMOS transistor MP3 and the NMOS transistor MN 4; an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV6, and an output end of the sixth inverter INV6 serves as a second output end of the pulse generating unit; the gate of the PMOS transistor MP3 is grounded to GND, the gate of the NMOS transistor MN4 is connected to the power supply terminal VDD, the sources of the PMOS transistor MP3 and the NMOS transistor MN4 are connected to the input terminal of the seventh inverter INV7, and the output terminal of the seventh inverter INV7 serves as the first output terminal of the pulse generating unit.
In one embodiment of the present invention, the pulse generation logic module includes 2i +1 pulse generation units, i is 0,1,2,3, 4;
the control signal input ends of the first pulse generating unit, the second pulse generating unit … …, the 2i pulse generating unit and the 2i +1 pulse generating unit are connected with the first output end of the decoding module;
a first signal input end of the first pulse generating unit is connected with the trigger signal output end;
the first signal input ends of the second pulse generating unit … …, the 2i pulse generating unit and the 2i +1 pulse generating unit are respectively connected with the first output ends of the first delay unit, the second delay unit … … and the 2i delay unit;
a second signal input end of the 2i +1 pulse generating unit is connected with a second output end of the 2i +1 delay unit;
and the first output end and the second output end of the 2i +1 th pulse generation unit are connected with the first input end of the pulse combination logic module.
In one embodiment of the present invention, i-4.
In one embodiment of the invention, the pulse combination logic circuit module comprises PMOS tubes MP 4-16, NMOS tubes MN 5-15, an output capacitor CAP1 and a second NOR gate;
the grid electrode of the PMOS tube MP4 is connected with the second output end of the first pulse generating unit, the grid electrode of the PMOS tube MP5 is connected with the second output end of the third pulse generating unit, and the drain electrodes of the PMOS tube MP4 and the PMOS tube MP5 pass through the output end VoutThe source electrodes of the PMOS tube MP4 and the PMOS tube MP5 are connected with the drain electrode of the PMOS tube MP6, and the grid electrode of the PMOS tube MP6 is connected with the second output end of the decoding module through an inverter;
the gate of the PMOS transistor MP7 is connected to the second output terminal of the third pulse generating unit, the gate of the PMOS transistor MP8 is connected to the second output terminal of the fifth pulse generating unit, and the drains of the PMOS transistor MP7 and the PMOS transistor MP8 pass through the output terminal VoutThe source electrodes of the PMOS tube MP7 and the PMOS tube MP8 are connected with the drain electrode of the PMOS tube MP9, and the grid electrode of the PMOS tube MP9 is connected with the second output end of the decoding module through an inverter;
a gate of the PMOS transistor MP10 is connected to the second output terminal of the fifth pulse generating unit, and a gate of the PMOS transistor MP11 is connected to the seventh pulse generating unitThe second output end of the pulse generating unit is connected, and the drains of the PMOS tube MP10 and the PMOS tube MP11 pass through the output end VoutThe source electrodes of the PMOS tube MP10 and the PMOS tube MP11 are connected with the drain electrode of the PMOS tube MP12, and the grid electrode of the PMOS tube MP12 is connected with the second output end of the decoding module through an inverter;
the gate of the PMOS transistor MP13 is connected to the second output terminal of the fifth pulse generating unit, the gate of the PMOS transistor MP14 is connected to the second output terminal of the seventh pulse generating unit, the gate of the PMOS transistor MP15 is connected to the second output terminal of the ninth pulse generating unit, and the drains of the PMOS transistor MP13, the PMOS transistor MP14, and the PMOS transistor MP15 are connected via the output terminal VoutThe source electrodes of the PMOS tube MP13, the PMOS tube MP14 and the PMOS tube MP15 are connected with the drain electrode of the PMOS tube MP16, and the grid electrode of the PMOS tube MP16 is connected with the second output end of the decoding module through an inverter;
the gate of the NMOS transistor MN5 is connected to the first output terminal of the second pulse generating unit, and the drain of the NMOS transistor MN5 passes through the output terminal (V) of the pulse combinational logic circuit blockout) The source electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN6, the source electrode of the NMOS transistor MN6 is grounded, and the gate electrode of the NMOS transistor MN6 is connected with the second output end of the decoding module;
the gate of the NMOS transistor MN7 is connected to the first output terminal of the fourth pulse generating unit, and the drain of the NMOS transistor MN7 passes through the output terminal VoutThe source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8, the source of the NMOS transistor MN8 is grounded, the gate of the NMOS transistor MN8 is connected to the output of the second nor gate, the output of the second nor gate is connected, the first input of the second nor gate is connected to the second output of the decoding module through the nor gate, and the second input of the second nor gate is connected to the second output of the decoding module;
the gate of the NMOS transistor MN9 is connected to the first output terminal of the fourth pulse generating unit, the gate of the NMOS transistor MN10 is connected to the first output terminal of the fourth pulse generating unit, and the gate of the NMOS transistor MN11 is connected to the gate of the NMOS transistor MN11The first output end of the sixth pulse generating unit is connected with the first output end of the sixth pulse generating unit; the drains of the NMOS transistor MN9, the NMOS transistor MN10 and the NMOS transistor MN11 pass through the output end VoutOutputting; the source electrodes of the NMOS transistor MN9, the NMOS transistor MN10 and the NMOS transistor MN11 are connected with the drain electrode of the NMOS transistor MN12, the grid electrode of the NMOS transistor MN12 is connected with the second output end of the decoding module, and the source electrode of the NMOS transistor MN12 is grounded;
the gate of the NMOS transistor MN13 is connected to the first output terminal of the sixth pulse generating unit, and the gate of the NMOS transistor MN14 is connected to the first output terminal of the eighth pulse generating unit; the drains of the NMOS transistor MN13 and the NMOS transistor MN14 pass through the output end VoutOutputting; the source electrodes of the NMOS transistor MN13 and the NMOS transistor MN14 are connected with the drain electrode of the NMOS transistor MN15, the grid electrode of the NMOS transistor MN15 is connected with the second output end of the decoding module, and the source electrode of the NMOS transistor MN15 is connected;
the upper polar plate of the output capacitor CAP1 is connected with the output end of the pulse combination logic circuit module, and the lower polar plate of the output capacitor CAP1 is grounded.
The invention has the beneficial effects that:
compared with the traditional ultra-wideband pulse waveform generating circuit, the frequency-shifting Gaussian pulse generating circuit based on digital logic has Gaussian pulse envelope and lower power consumption and area. Meanwhile, by introducing the pulse number control logic, the bandwidth of the ultra-wideband pulse signal can be controlled by adjusting the single pulse width and the single pulse number to obtain different voltage amplitudes, so that the envelope shape similar to Gaussian pulse is realized, and low power consumption, small area and larger adjustment range are realized.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a block diagram of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 2 is a timing diagram of external control signals of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a delay module of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 4 is a circuit schematic diagram of a delay unit of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 5 is a timing diagram of a Trigger signal Trigger of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a pulse generation logic module of a frequency-shift gaussian pulse generation circuit implemented based on digital logic according to an embodiment of the present invention;
fig. 7 is an electrical diagram of a pulse generating unit of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention;
FIG. 8 is an inverted narrow pulse signal S of a pulse generating unit of a frequency-shifted Gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present inventionN[i]Timing diagrams of (1);
fig. 9 is a circuit schematic diagram of a pulse combination logic circuit module of a frequency-shifted gaussian pulse generation circuit implemented based on digital logic according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a block diagram of a frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to an embodiment of the present invention, where the frequency-shifted gaussian pulse generating circuit implemented based on digital logic according to the embodiment of the present invention includes a control signal output terminal, a delay control signal output terminal, a trigger signal output terminal, a decoding module, a delay module, a pulse generating logic module, a pulse combinational logic circuit module, and an output terminal Vout. The delay control signal output end and the trigger signal output end respectively output a delay control signal VcTrigger, triggeringThe signal Trigger is input into a delay module, and the delay module delays a control signal VcThe delay of the external trigger signal is realized under the control of the controller, and a delay trigger signal is obtained; the decoding module receives an external control signal B from a control signal output end1B0And to the external control signal B1B0Decoding to obtain a decoding control signal; the first input end and the second input end of the pulse generation logic module respectively input a delay trigger signal and a decoding control signal to obtain a single pulse signal; the first input end and the second input end of the pulse combination logic respectively input a single pulse signal and a decoding control signal, and the single pulse signal is combined according to the decoding control signal to obtain a corresponding frequency shift Gaussian pulse signal.
Example two
On the basis of the first embodiment, the decoding module of the present embodiment employs a 2-4 decoding circuit, the delay module includes 9 delay units, and the pulse generation logic module includes 9 pulse generation units.
Further, as shown in FIG. 2, the control signal output terminal provides an external control signal B for the 2-4 decoding circuit1B0The output end of the delay control signal provides a delay control signal V for the delay modulecThe trigger signal output end provides a certain repetition frequency period T for the delay moduleprfTrigger signal Trigger, delay unit circuit delay control signal VcThe Trigger signal Trigger is delayed under the control of the Trigger signal Trigger, the delayed signal passes through the pulse generation logic module to generate a corresponding single pulse signal, wherein the width of the single pulse signal is controlled by a delay control signal VcDetermining that the number of generated single pulses is controlled by the output of the 2-4 decoding circuit when B1B0When 2' b00, 3 monopulse signals are generated; when B is present1B0When 2' b01, 5 monopulse signals are generated; when B is present1B0When 2' b10, 7 monopulse signals are generated; when B is present1B0When 2' b11, 9 monopulse signals are generated. Finally, the single pulse signal generated by the pulse generation logic module is spliced by the pulse combination logic circuit module to generate frequency shift Gaussian pulseThe signal is pulsed.
EXAMPLE III
Based on the first and second embodiments, as shown in fig. 3,4 and 5, the delay trigger signal V output from the first output terminal of the delay unit in the delay moduleR[i-1]The gates of NMOS transistor MN1 and PMOS transistor MP1 in the latter delay subunit are connected, wherein VR0Trigger, i 1,2 … 9. When V isR[i-1]After the signal changes from low level to high level, the PMOS transistor MP1 is turned off, the NMOS transistor N1 is turned on, the potential of the node X is discharged from high level to low level through the NMOS transistor MN1 and the NMOS transistor MN2, and the discharge time is controlled by a delay control signal V connected with the gate end of the NMOS transistor MN2cAnd (6) determining. Then obtaining a delay trigger signal V through a first inverter, a second inverter and a third inverterR[i]The other path of the delayed trigger signal passes through a first inverter, a fourth inverter and a primary transmission gate consisting of a PMOS tube MP2 and an NMOS tube MN3 to obtain an inverted delayed trigger signal VF[i]. In this embodiment, 9 delay units are used in total, and finally 9 delay trigger signals V are generatedR1-VR9Simultaneously generating 9 reverse-phase delay trigger signals VF1-VF9。
Example four
Based on the first, second and third embodiments, as shown in fig. 6, 7 and 8, the 2-4 decoding circuit decodes the external control signal B1B0Decoding and outputting to obtain a decoding control signal P4P3P2P1Decoding the control signal P1The control signal input ends are respectively sent to the first pulse generating unit, the second pulse generating unit and the third pulse generating unit; the control signal input ends of the fourth pulse generating unit and the fifth pulse generating unit input a decoding control signal P2(ii) a The control signal input ends of the sixth pulse generating unit and the seventh pulse generating unit input decoding control signals P3(ii) a The control signal input ends of the eighth pulse generating unit and the ninth pulse generating unit input a decoding control signal P4. The number of generated single pulse signals can be switched among 3, 5, 7 and 9 under the control of a decoding control signal output by the 2-4 decoding circuit.
Specifically, when B1B0When 2' b00, the control signal P is decoded4P3P2P1The first pulse generating unit, the second pulse generating unit and the third pulse generating unit work normally, and the rest pulse generating units are turned off, so that three narrow pulse signals are generated. When the time delay triggers signal VR[i-1]After jumping from low level to high level and being delayed by a delay unit, the reverse phase delay trigger signal VF[i]Jumping from high level to low level, delaying trigger signal VR[i-1]And an inverted delayed trigger signal VF[i]After passing through the NAND gate, a corresponding narrow pulse signal S is generated after passing through a first-stage transmission gate consisting of a PMOS transistor MP3 and an NMOS transistor MN4 and a seventh inverter[i]After passing through the fifth inverter and the sixth inverter, an inverted signal S is generatedN[i]Wherein the narrow pulse width is determined by the delay unit.
EXAMPLE five
On the basis of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, as shown in fig. 9, the size ratio of the PMOS transistors MP4, MP5, MP7, MP8, MP10, MP11, MP13, MP14 and MP15 in this embodiment is 1:1:1:1:1:1:1:1, and the size ratio of the NMOS transistors MN5, MN7, MN9, MN10, MN11, MN13 and MN14 is 1:1:1:1:1: 1. When the external control signal B1B0 is 2' B00, the control signal P is decoded4P3P2P14' b0001, its inverse signal PN4PN3PN2PN14' b 1110. At this time, the PMOS transistor MP6 is turned on, and the PMOS transistor MP9, the PMOS transistor MP12 and the PMOS transistor MP16 are turned off; the NMOS transistor MN6 is turned on, and the NMOS transistor MN8, the NMOS transistor MN12 and the NMOS transistor MN15 are turned off. Inverse narrow pulse signal SN[1]Firstly, the high level is changed into the low level, the PMOS tube MP4 is switched on, the rest MOS tubes are switched off, and the output capacitor CAP1 is charged through the PMOS tube MP 4; then inverting the narrow pulse signal SN[1]Jumping from low level to high level, the PMOS tube MP4 is turned off, and the narrow pulse signal S is simultaneously[2]When the voltage is switched from low level to high level, the NMOS tube MN5 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 5; after a delay time of a delay unit, the narrow pulse signalNumber S[2]Jump from high level to low level, NMOS pipe MN5 is turned off, and at the same time, inverse narrow pulse signal SN[3]When the voltage is switched from high level to low level, the PMOS tube MP5 is conducted, and the output capacitor CAP1 is charged through the MP 5; after the delay time of a delay unit, the narrow pulse signal S is reversedN[3]Jump from low to high, the PMOS transistor MP8 is turned off. At this time, the ultra-wideband pulse signal is composed of three single pulses.
When the external control signal B1B0When 2' b01, the control signal P is decoded4P3P2P14' b0011, the inverse signal is PN4PN3PN2PN14' b 1100. At this time, the PMOS transistor MP6 and the PMOS transistor MP9 are turned on, and the PMOS transistor MP12 and the PMOS transistor MP16 are turned off; the NMOS transistor MN6 and the NMOS transistor MN8 are turned on, and the NMOS transistor MN12 and the NMOS transistor MN15 are turned off. Inverse narrow pulse signal SN[1]Firstly, the high level is converted into the low level, the PMOS tube MP4 is switched on, the rest MOS tubes are switched off, and the output capacitor CAP1 is charged through the PMOS tube MP 4; and then narrow pulse signal SN[1]Jumping from low level to high level, the PMOS tube MP4 is turned off, and the narrow pulse signal S is simultaneously[2]When the voltage is switched from low level to high level, the NMOS tube MN5 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 5; after a delay time of a delay unit, the narrow pulse signal S[2]The NMOS tube MN5 is turned off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[3]When the voltage jumps from the high level to the low level, the PMOS transistor MP5 is conducted with the NMOS transistor MN7, the PMOS transistor MP5 and the NMOS transistor MN7 charge the output capacitor CAP1 at the same time, and the output voltage amplitude of the output capacitor is increased; after a delay time of a delay unit, the narrow pulse signal S is invertedN[3]Jumping from low level to high level, the PMOS transistor MP5 and the PMOS transistor MP7 are turned off, and simultaneously, the narrow pulse signal S is reversedN[4]When the low level is changed into the high level, the NMOS tube MN7 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 7; after a delay time of a delay subunit, inverting the narrow pulse signal SN[4]Jump from high level to low level, NMOS pipe MN7 is turned off, and at the same time, narrow pulse signal S is reversedN[5]Jumping from high level to low level;the PMOS tube MP8 is conducted, and the output capacitor CAP1 is charged through the PMOS tube MP 8; after a delay time of a delay unit, the narrow pulse signal S is reversedN[5]Jump from low to high, the PMOS transistor MP8 is turned off. At this time, the ultra-wideband pulse signal is composed of five single pulses.
When the external control signal B1B0When 2' b10, the control signal P is decoded4P3P2P14' b0111, its inverse signal is PN4PN3PN2PN14' b 1000. At this time, the PMOS transistor MP6, the PMOS transistor MP9, and the PMOS transistor MP12 are turned on, and the PMOS transistor MP16 is turned off; the NMOS transistor MN6, the NMOS transistor MN8 and the NMOS transistor MN12 are turned on, and the NMOS transistor MN15 is turned off. Inverse narrow pulse signal SN[1]Jumping from high level to low level, the NMOS transistor MN4 is switched on, the rest MOS transistors are switched off, and the output capacitor CAP1 is charged through the PMOS transistor MP 4; then inverting the narrow pulse signal SN[1]Jumping from low level to high level, the PMOS tube MP4 is turned off, and the narrow pulse signal S is simultaneously[2]Jumping from low level to high level, the NMOS tube MN5 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 5; after a delay time of a delay unit, the narrow pulse signal S[2]The NMOS tube MN5 is turned off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[3]When the voltage jumps from the high level to the low level, the PMOS transistor MP5 and the PMOS transistor MP7 are conducted, the output capacitor CAP1 is charged through the PMOS transistor MP5 and the PMOS transistor MP7 at the same time, and the amplitude of the output voltage of the output capacitor CAP1 is increased; after a delay time of a delay unit, the narrow pulse signal S is invertedN[3]Jumping from low level to high level, the PMOS transistor MP5 and the PMOS transistor MP7 are turned off, and simultaneously, the narrow pulse signal S is reversedN[4]When the low level is changed into the high level, the NMOS tube MN7, the NMOS tube MN9 and the NMOS tube MN10 are conducted, the output capacitor CAP1 is discharged through the NMOS tube MN7, the NMOS tube MN9 and the NMOS tube MN10, and the amplitude of output voltage is further increased; after a delay time of a delay unit, the narrow pulse signal S is invertedN[4]When the high level is switched to the low level, the NMOS transistor MN7, the NMOS transistor MN9 and the NMOS transistor MN10 are switched off, and meanwhile, the narrow pulse signal S is reversedN[5]Jump from high level to low levelWhen the PMOS transistor MP8 and the PMOS transistor MP10 are turned on, the capacitor CAP1 is output through the two MOS transistors MP8 and MP 10; after a delay time of a delay unit, the narrow pulse signal S is invertedN[5]Jumping from low level to high level, the PMOS transistor MP8 and the PMOS transistor MP10 are turned off, and the narrow pulse signal S[6]When the low level is changed into the high level, the NMOS tube MN11 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 11; after a delay time of a delay unit, the narrow pulse signal S[6]The NMOS tube MN11 is turned off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[7]When the voltage is switched from high level to low level, the PMOS tube MP11 is conducted, and the output capacitor CAP1 is charged through the PMOS tube MP 11; narrow pulse signal S of one time delay unit after delay time inversionN[7]Jump from low to high, the PMOS transistor MP11 is turned off. At this time, the ultra-wideband pulse signal is composed of seven single pulses.
When the external control signal B1B0When 2' b11, the control signal P is decoded4P3P2P14' b1111, the inverse signal is PN4PN3PN2PN14' b 0000. At this time, the PMOS transistor MP6, the PMOS transistor MP9, the PMOS transistor MP12 and the PMOS transistor MP16 are turned on; the NMOS transistor MN6, the NMOS transistor MN12 and the NMOS transistor MN15 are turned on, and the NMOS transistor MN8 is turned off. Inverse narrow pulse signal SN[1]Firstly, the high level is converted into the low level, the PMOS tube MP4 is switched on, the rest MOS tubes are kept switched off, and the output capacitor CAP1 is charged through the PMOS tube MP 4; then inverting the narrow pulse signal SN[1]Jumping from low level to high level, the PMOS tube MP4 is turned off, and simultaneously, the narrow pulse signal S[2]When the low level is changed into the high level, the NMOS tube MN5 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 5; after a delay time of a delay unit, the narrow pulse signal S[2]The NMOS tube MN5 is turned off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[3]When the voltage is changed from the high level to the low level, the PMOS tube MP5 is conducted with the PMOS tube MP7, and the output capacitor CAP1 is charged through the PMOS tube MP5 and the PMOS tube MP 7; after the delay time of a delay unit, the narrow pulse signal is invertedSN[3]Jumping from low level to high level, the PMOS transistor MP5 and the PMOS transistor MP7 are turned off, and the narrow pulse signal S[4]When the voltage is switched from low level to high level, the NMOS transistor MN9 is conducted with the NMOS transistor MN10, and the output capacitor CAP1 is discharged through the NMOS transistor MN9 and the NMOS transistor MN 10; after a delay time of a delay unit, the narrow pulse signal S is simultaneously transmitted[4]The NMOS transistor MN9 and the NMOS transistor MN10 are switched off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[5]When the voltage is switched from the high level to the low level, the PMOS tube MP8, the PMOS tube MP10 and the PMOS tube MP13 are conducted, and the output capacitor CAP1 is charged through the PMOS tube MP8, the PMOS tube MP10 and the PMOS tube MP 13; after a delay time of a delay unit, the narrow pulse signal S is invertedN[5]When the voltage level is changed from low level to high level, the PMOS transistor MP8, the PMOS transistor MP10 and the PMOS transistor MP13 are turned off, and meanwhile, the narrow pulse signal S[6]When the low level is changed into the high level, the NMOS tube MN11 is conducted with the NMOS tube MN13, and the output capacitor CAP1 is discharged through the NMOS tube MN11 and the NMOS tube MN 13; after a delay time of a delay unit, the narrow pulse signal S[6]The NMOS transistor MN11 and the NMOS transistor MN13 are switched off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[7]When the voltage is changed from the high level to the low level, the PMOS tube MP11 is conducted with the PMOS tube MP14, and the output capacitor CAP1 is charged through the PMOS tube MP11 and the PMOS tube MP 14; after a delay time of a delay unit, the narrow pulse signal S is invertedN[7]Jumping from low level to high level, the PMOS transistor MP11 and the PMOS transistor MP14 are turned off, and simultaneously, the narrow pulse signal S[8]When the low level is changed into the high level, the NMOS tube MN14 is conducted, and the output capacitor CAP1 is discharged through the NMOS tube MN 14; after a delay time of a delay unit, the narrow pulse signal S[8]The NMOS tube MN14 is turned off when the high level is switched to the low level, and meanwhile, the narrow pulse signal S is reversedN[9]When the voltage is switched from high level to low level, the PMOS tube MP15 is conducted, and the output capacitor CAP1 is charged through the PMOS tube MP 15; narrow pulse signal S with reverse phase after one time delay unitN[9]Jump from low to high, the PMOS transistor MP15 is turned off. At this time, the ultra-wideband pulse signal is composed of nine single pulses.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (8)

1. A frequency-shifted gaussian pulse generation circuit implemented based on digital logic, comprising:
a control signal output terminal for transmitting an external control signal (B)1B0)；
A delay control signal output terminal for transmitting a delay control signal (V)c)；
A Trigger signal output end for sending a Trigger signal (Trigger);
a decoding module, the input of which is connected to the control signal output, for receiving the external control signal (B)1B0) And for said external control signal (B)1B0) Decoding to obtain a decoding control signal;
a delay module, a first input end of the delay module being connected with the delay control signal output end, a second input end of the delay module being connected with the trigger signal output end, the delay module being configured to receive the delay control signal (V)c) The Trigger signal (Trigger) and the delay control signal (V)c) Under the control of the Trigger signal (Trigger), delaying the Trigger signal (Trigger) to obtain a delayed Trigger signal;
a pulse generation logic module, a first input end of the pulse generation logic module is connected with an output end of the delay module, a second input end of the pulse generation logic module is connected with a first output end of the decoding module, and the pulse generation logic module is used for generating a single pulse signal according to the delay trigger signal and the decoding control signal;
a pulse combinational logic circuit module, a first input end of the pulse combinational logic circuit module being connected with an output end of the pulse generation logic module, a second input end of the pulse combinational logic circuit module being connected with a second output end of the decoding module, the pulse combinational logic circuit module being configured to combine the single pulse signals according to the decoding control signal to obtain a frequency-shifted gaussian pulse signal;
output terminal (V)out) Said output terminal (V)out) Connected to the output of the pulse combinational logic circuit module, the output (V)out) For outputting the frequency-shifted gaussian pulse signal.
2. The circuit of claim 1, wherein the decoding module is a 2-4 decoding circuit.
3. The frequency-shifted gaussian pulse generation circuit based on digital logic implementation, according to claim 1, wherein said delay module comprises 2i +1 delay units, i is 0,1,2,3, 4;
the 2i +1 delay units are sequentially cascaded;
and the control signal input ends of the 2i +1 delay units are connected with the delay control signal output end.
4. The circuit of claim 3, wherein the delay unit comprises: a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and a power supply end VDD;
the gates of the PMOS transistor MP1 and the NMOS transistor MN1 are used as the signal input ends of the delay unit; the source electrode of the PMOS tube MP1 is connected with the power supply end VDD, the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN2, and the drain electrode of the PMOS tube MP1 is also connected with the input end of the first inverter INV 1;
the gate of the NMOS transistor MN2 is used as a signal input end of the delay unit, the source of the NMOS transistor MN1 is grounded, the drain of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN2, and the drain of the NMOS transistor MN2 is connected to the input end of the first inverter INV 1;
the drain electrodes of the PMOS transistor MP2 and the NMOS transistor MN3 are connected to the output end of the first inverter INV1, the source electrodes of the PMOS transistor MP2 and the NMOS transistor MN3 are connected to the input end of the fourth inverter INV4, the output end of the fourth inverter INV4 serves as the second output end of the delay unit, the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, the output end INV2 of the second inverter is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 serves as the first output end of the delay unit.
5. The frequency-shifted gaussian pulse generation circuit implemented based on digital logic according to claim 4, wherein said pulse generation logic module comprises 2i +1 pulse generation units, i is 0,1,2,3, 4;
the control signal input ends of the first pulse generating unit, the second pulse generating unit … …, the 2i pulse generating unit and the 2i +1 pulse generating unit are connected with the first output end of the decoding module;
a first signal input end of the first pulse generating unit is connected with the trigger signal output end;
the first signal input ends of the second pulse generating unit … …, the 2i pulse generating unit and the 2i +1 pulse generating unit are respectively connected with the first output ends of the first delay unit, the second delay unit … … and the 2i delay unit;
a second signal input end of the 2i +1 pulse generating unit is connected with a second output end of the 2i +1 delay unit;
and the first output end and the second output end of the 2i +1 th pulse generation unit are connected with the first input end of the pulse combination logic module.
6. The frequency-shifted Gaussian pulse generation circuit implemented based on digital logic according to claim 5, wherein the pulse generation unit comprises: a first nand gate, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an NMOS transistor MN4, and a PMOS transistor MP 3;
a first input end of the first nand gate is connected with the trigger signal output end, a second input end of the first nand gate is connected with a second output end of the delay unit, a third input end of the first nand gate is connected with a first output end of the decoding module, an output end of the first nand gate is connected with an input end of the fifth inverter INV5, and an output end of the first nand gate is further connected with drains of the PMOS transistor MP3 and the NMOS transistor MN 4; an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV6, and an output end of the sixth inverter INV6 serves as a second output end of the pulse generating unit; the gate of the PMOS transistor MP3 is grounded to GND, the gate of the NMOS transistor MN4 is connected to the power supply terminal VDD, the sources of the PMOS transistor MP3 and the NMOS transistor MN4 are connected to the input terminal of the seventh inverter INV7, and the output terminal of the seventh inverter INV7 serves as the first output terminal of the pulse generating unit.
7. The frequency-shifted gaussian pulse generation circuit implemented based on digital logic according to claim 3 or 5, wherein i is 4.
8. The frequency-shifted Gaussian pulse generation circuit based on digital logic implementation is characterized in that the pulse combination logic circuit module comprises PMOS tubes MP 4-16 and NMOS tubes MN 5-15, an output capacitor CAP1 and a second NOR gate;
the gate of the PMOS transistor MP4 is connected to the second output terminal of the first pulse generating unit, the gate of the PMOS transistor MP5 is connected to the second output terminal of the third pulse generating unit, and the drains of the PMOS transistor MP4 and the PMOS transistor MP5 pass through the output terminal (V)out) The output ends of the PMOS tubes MP4 and MP5 are connected with the drain of the PMOS tube MP6, and the gate of the PMOS tube MP6 is connected with the second end of the decoding module through an inverterThe output end is connected;
the gate of the PMOS transistor MP7 is connected to the second output terminal of the third pulse generating unit, the gate of the PMOS transistor MP8 is connected to the second output terminal of the fifth pulse generating unit, and the drains of the PMOS transistor MP7 and the PMOS transistor MP8 pass through the output terminal (V)out) The source electrodes of the PMOS tube MP7 and the PMOS tube MP8 are connected with the drain electrode of the PMOS tube MP9, and the grid electrode of the PMOS tube MP9 is connected with the second output end of the decoding module through an inverter;
the gate of the PMOS transistor MP10 is connected to the second output terminal of the fifth pulse generating unit, the gate of the PMOS transistor MP11 is connected to the second output terminal of the seventh pulse generating unit, and the drains of the PMOS transistor MP10 and the PMOS transistor MP11 pass through the output terminal (V)out) The source electrodes of the PMOS tube MP10 and the PMOS tube MP11 are connected with the drain electrode of the PMOS tube MP12, and the grid electrode of the PMOS tube MP12 is connected with the second output end of the decoding module through an inverter;
the gate of the PMOS transistor MP13 is connected to the second output terminal of the fifth pulse generating unit, the gate of the PMOS transistor MP14 is connected to the second output terminal of the seventh pulse generating unit, the gate of the PMOS transistor MP15 is connected to the second output terminal of the ninth pulse generating unit, and the drains of the PMOS transistor MP13, the PMOS transistor MP14 and the PMOS transistor MP15 pass through the output terminal (V _ out) (i.e., V _ out)out) The source electrodes of the PMOS tube MP13, the PMOS tube MP14 and the PMOS tube MP15 are connected with the drain electrode of the PMOS tube MP16, and the grid electrode of the PMOS tube MP16 is connected with the second output end of the decoding module through an inverter;
the gate of the NMOS transistor MN5 is connected to the first output terminal of the second pulse generating unit, and the drain of the NMOS transistor MN5 passes through the output terminal (V) of the pulse combinational logic circuit blockout) The source electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN6, the source electrode of the NMOS transistor MN6 is grounded, and the gate electrode of the NMOS transistor MN6 is connected with the second output end of the decoding module;
the gate of the NMOS transistor MN7 is connected to the first output terminal of the fourth pulse generating unit, and the drain of the NMOS transistor MN7 passes through the output terminal (V)out) Output ofThe source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8, the source of the NMOS transistor MN8 is grounded, the gate of the NMOS transistor MN8 is connected to the output of the second nor gate, the output of the second nor gate is connected, the first input of the second nor gate is connected to the second output of the decoding module through the nor gate, and the second input of the second nor gate is connected to the second output of the decoding module;
the gate of the NMOS transistor MN9 is connected to the first output terminal of the fourth pulse generating unit, the gate of the NMOS transistor MN10 is connected to the first output terminal of the fourth pulse generating unit, and the gate of the NMOS transistor MN11 is connected to the first output terminal of the sixth pulse generating unit; the drains of the NMOS transistor MN9, the NMOS transistor MN10 and the NMOS transistor MN11 pass through the output end VoutOutputting; the source electrodes of the NMOS transistor MN9, the NMOS transistor MN10 and the NMOS transistor MN11 are connected with the drain electrode of the NMOS transistor MN12, the grid electrode of the NMOS transistor MN12 is connected with the second output end of the decoding module, and the source electrode of the NMOS transistor MN12 is grounded;
the gate of the NMOS transistor MN13 is connected to the first output terminal of the sixth pulse generating unit, and the gate of the NMOS transistor MN14 is connected to the first output terminal of the eighth pulse generating unit; the drains of the NMOS transistor MN13 and the NMOS transistor MN14 pass through the output end (V)out) Outputting; the source electrodes of the NMOS transistor MN13 and the NMOS transistor MN14 are connected with the drain electrode of the NMOS transistor MN15, the grid electrode of the NMOS transistor MN15 is connected with the second output end of the decoding module, and the source electrode of the NMOS transistor MN15 is connected;
the upper polar plate of the output capacitor CAP1 is connected with the output end of the pulse combination logic circuit module, and the lower polar plate of the output capacitor CAP1 is grounded.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545304B1 (en) * 2006-09-01 2009-06-09 University Of Rochester Distributed arbitrary waveform generator
CN102147460A (en) * 2010-02-10 2011-08-10 中国科学院电子学研究所 System and method for receiving ultra wide band pulsed radar
CN103066953A (en) * 2012-12-27 2013-04-24 上海集成电路研发中心有限公司 Continuous pulse generator
CN103081367A (en) * 2010-07-27 2013-05-01 埃克斯-马赛大学 Method and device for generating ultra wide band pulses (UWB)
CN104967464A (en) * 2015-07-03 2015-10-07 桂林电子科技大学 CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter
CN104967465A (en) * 2015-07-03 2015-10-07 桂林电子科技大学 CMOS fully digital frequency adjustable pulse radio ultra-wideband transmitter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545304B1 (en) * 2006-09-01 2009-06-09 University Of Rochester Distributed arbitrary waveform generator
CN102147460A (en) * 2010-02-10 2011-08-10 中国科学院电子学研究所 System and method for receiving ultra wide band pulsed radar
CN103081367A (en) * 2010-07-27 2013-05-01 埃克斯-马赛大学 Method and device for generating ultra wide band pulses (UWB)
CN103066953A (en) * 2012-12-27 2013-04-24 上海集成电路研发中心有限公司 Continuous pulse generator
CN104967464A (en) * 2015-07-03 2015-10-07 桂林电子科技大学 CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter
CN104967465A (en) * 2015-07-03 2015-10-07 桂林电子科技大学 CMOS fully digital frequency adjustable pulse radio ultra-wideband transmitter

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