CN112491411B - exclusive-OR gate circuit for reducing delay of NAND gate input signal - Google Patents

Abstract

The input signals A and B in the path 1 are input into the NAND gate module after passing through the transmission gate module and the NAND gate module, the input signals A and B in the path 2 are input into the NAND gate module after passing through the driving module, and then the NAND gate module utilizes three NAND gates to realize the exclusive-OR gate logic to obtain the output signals of the exclusive-OR gate circuit. The delay of the driving module and the transmission gate module is adjustable, so that the delay of the input signals A and B passing through the transmission gate module and the NOT gate module is identical with the delay of the input signals A and B passing through the driving module as far as possible by controlling the delay of the driving module and the transmission gate module, thereby improving the influence on the pulse width and the delay of the output signals caused by the delay of the input signals of the NOT gate in the exclusive-OR gate circuit and simultaneously increasing the driving capability of the subsequent circuits.

Description

An Exclusive OR Gate Circuit for Reducing the Delay of NAND Gate Input Signal

technical field

The invention belongs to the technical field of electronic circuits, and relates to an exclusive OR gate circuit for reducing the delay of an input signal of a NAND gate.

Background technique

As shown in Figure 1, it is a traditional XOR gate circuit, and its working principle is as follows: the two input signals of the XOR gate circuit are the first input signal A and the second input signal B, and the non-operation output of the first input signal A A' and the second input signal B are input to the first NAND gate NAND1 for NAND operation, and the non-operation output B' of the first input signal A and the second input signal B is input to the second NAND gate NAND2 for NAND operation , the outputs of the first NAND gate NAND1 and the second NAND gate NAND2 are input to the third NAND gate NAND3 for NAND operation, and the obtained output signal Y of the third NAND gate NAND3 is the first input signal A and the second NAND gate Exclusive OR (XOR) operation output of input signal B.

However, for the traditional XOR gate circuit, due to the inherent delay of the inverter, the first input signal A and the second input signal B will have an additional delay after passing through the NOT gate, resulting in the input to the first NAND gate NAND1 The delays of the two signals are different, and the delays of the two signals input to the second NAND gate NAND2 are also different, which further affect the pulse width and delay of the output signal Y.

Contents of the invention

Aiming at the problem that the above-mentioned traditional XOR gate circuit has different delays of the two signals input to the NAND gate due to the inherent delay of the inverter, resulting in the influence of the pulse width and delay of the output signal Y of the XOR gate circuit, the present invention proposes An XOR gate circuit is developed, which can reduce the delay of the input signal of the NAND gate, so that the delay of the signal arriving at the NAND gate module is as consistent as possible.

Technical scheme of the present invention is as follows:

An exclusive OR gate circuit for reducing the input signal delay of a NAND gate, including a NOT gate module and a NAND gate module,

The NAND gate module includes a first NAND gate, a second NAND gate and a third NAND gate, the first input of the third NAND gate is connected to the output of the first NAND gate, and the second input of the NAND gate is Connect the output end of the second NAND gate, and its output end outputs the output signal of the XOR gate circuit;

The NOT gate module includes two input terminals and two output terminals, and the signal at the first input terminal of the NOT gate module is output from the first output terminal of the NOT gate module to the first NAND gate after inversion. An input terminal, the signal of the second input terminal of the NOT gate module is output from the second output terminal of the NOT gate module to the first input terminal of the second NAND gate after inversion;

The XOR gate circuit also includes a transmission gate module and a drive module,

The transmission gate module includes a first transmission gate and a second transmission gate that are constantly turned on, and the two connection ends of the first transmission gate are respectively connected to the first input signal of the XOR gate circuit and the second transmission gate of the NOT gate module. An input terminal, the two connection terminals of the second transmission gate are respectively connected to the second input signal of the XOR gate circuit and the second input terminal of the NOT gate module;

The drive module includes a first drive unit and a second drive unit, the input end of the first drive unit is connected to the first input signal of the XOR gate circuit, and the output end of the first drive unit is connected to the second input end of the second NAND gate; The input end of the second driving unit is connected to the second input signal of the XOR gate circuit, and the output end thereof is connected to the second input end of the first NAND gate;

By adjusting the delay of the transmission gate module and the driving module, the signals at the two input terminals of the first NAND gate and the signals at the two input terminals of the second NAND gate have the same delay as possible.

Specifically, the first transmission gate and the second transmission gate have the same structure, the first transmission gate includes a first NMOS transistor and a first PMOS transistor, the gate of the first NMOS transistor is connected to the substrate of the first PMOS transistor Input power supply, the gate of the first PMOS transistor and the substrate of the first NMOS transistor are grounded, the source of the first NMOS transistor and the source of the first PMOS transistor are interconnected and serve as a connection terminal of the first transmission gate, the first The drain of the NMOS transistor is interconnected with the drain of the first PMOS transistor and serves as another connection end of the first transmission gate.

Specifically, both the first driving unit and the second driving unit include an even number of cascaded inverters.

Specifically, the NOT gate module includes a first inverter and a second inverter, the input terminal of the first inverter serves as the first input terminal of the NOT gate module, and its output terminal serves as the first input terminal of the NOT gate module. the first output terminal of the second inverter; the input terminal of the second inverter is used as the second input terminal of the NOT gate module, and the output terminal thereof is used as the second output terminal of the NOT gate module.

Specifically, both the first driving unit and the second driving unit include two cascaded inverters, the inverters in the inverter module and the driving module are composed of MOS transistors, and the driving module and the transmission The size of the MOS tube in the gate module is designed to be consistent with the size of the MOS tube in the NOT-gate module.

The working principle of the present invention is: the first input signal A and the second input signal B arrive at the NAND gate module through two paths, the transmission gate module and the NOT gate module are set in path 1, and the first input signal A and the The second input signal B passes through a transmission gate structure and then performs a non-operation; the path 2 is provided with a drive module, and the first input signal A and the second input signal B in path 2 do not perform a non-operation, and then input the NAND gate module after driving ; Since the delay of the transmission gate module and the driving module is adjustable, by adjusting the delay of the transmission gate module in path 1 and adjusting the delay of the driving module in path 2, the first input signal A and the second input signal B can be passed through The delays of the first NAND gate NAND1 and the second NAND gate NAND2 in the NAND gate module after the two paths are as same as possible, thereby reducing the delay of the input signals of the first NAND gate NAND1 and the second NAND gate NAND2 jet lag.

The beneficial effects of the present invention are: the XOR gate circuit proposed by the present invention is provided with two paths, the input signals A and B respectively pass through the transmission gate module and the NOT gate module in path 1 to reach the NAND gate module, and the input signals A and B In path 1, the drive module reaches the NAND gate module, and by adjusting the delay of the drive module of the transmission gate module, the delay of the signal arriving at the NAND gate module is as consistent as possible, reducing the delay of the NAND gate input signal, At the same time, the driving capability of subsequent circuits is also increased.

Description of drawings

A better understanding of the following description of different embodiments of the invention is provided by the following drawings, which schematically illustrate the main features of some embodiments of the invention. These figures and examples present some embodiments of the invention in a non-limiting, non-exhaustive manner. For the sake of brevity, the same or similar components or structures with the same function in different drawings use the same reference signs.

Figure 1 is a schematic diagram of the connection of a traditional XOR gate circuit.

FIG. 2 is a structural block diagram of an XOR gate circuit for reducing the input signal delay of the NAND gate proposed by the present invention.

FIG. 3 is a circuit diagram of an implementation of a transmission gate module in an exclusive OR gate circuit for reducing the input signal delay of a NAND gate proposed by the present invention.

FIG. 4 is a circuit diagram of an implementation of a NOT gate module in an exclusive OR gate circuit proposed by the present invention to reduce the input signal delay of the NAND gate.

FIG. 5 is a circuit diagram of an implementation of a driving module in an XOR gate circuit for reducing the input signal delay of a NAND gate proposed by the present invention.

FIG. 6 is a circuit diagram for realizing a NAND gate module in an exclusive OR gate circuit proposed by the present invention to reduce the input signal delay of the NAND gate.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below in conjunction with the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that in the present invention, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between.

As shown in Figure 2, the present invention proposes an exclusive OR gate circuit that reduces the delay of the input signal of the NAND gate, including a NOT gate module, a NAND gate module, a transmission gate module and a drive module, and the exclusive OR gate circuit has two The input signals, that is, the first input signal A and the second input signal B, the first input signal A and the second input signal B respectively pass through the path 1 and the path 2 to reach the NAND gate module.

Path 1 includes a transmission gate module and a non-gate module. The transmission gate module includes a first transmission gate and a second transmission gate with constant conduction, which can be composed of MOS transistors. As shown in Figure 3, the first transmission gate includes a first NMOS transistor MN0 and the first PMOS transistor MP0, the source of the first NMOS transistor MN0 is connected to the source of the first PMOS transistor MP0 and serves as a connection end of the first transmission gate, and the drain of the first NMOS transistor MN0 is connected to the first PMOS transistor MP0 The drain of the first NMOS transistor MN0 is used as the other connection end of the first transmission gate, the substrate of the first NMOS transistor MN0 is grounded, the gate of the first NMOS transistor MN0 is connected to the input power supply, the substrate of the first PMOS transistor MP0 is connected to the input power supply, and the substrate of the first NMOS transistor MN0 is connected to the input power supply. A gate of the PMOS transistor MP0 is grounded. The second transmission gate includes a second NMOS transistor MN1 and a second PMOS transistor MP1. The source of the second NMOS transistor MN1 is connected to the source of the second PMOS transistor MP1 and serves as a connection terminal of the second transmission gate. The second NMOS transistor MN1 The drain of the second PMOS transistor MP1 is connected to the drain of the second transmission gate, the substrate of the second NMOS transistor MN1 is connected to the ground, the gate of the second NMOS transistor MN2 is connected to the input power supply, and the second PMOS transistor The substrate of MP1 is connected to the input power supply, and the gate of the second PMOS transistor MP2 is grounded.

The two connection ends of the first transmission gate are respectively connected to the first input signal A and the first input end of the NOT gate module, and the two connection ends of the second transmission gate are respectively connected to the second input signal B and the second input of the NOT gate module The two connection terminals of the transmission gate are interchangeable, such as the connection terminal of the first transmission gate that can connect the source of the first NMOS transistor MN0 and the source of the first PMOS transistor MP0 in the embodiment shown in FIG. Connect the first input signal A as the input terminal of the transmission gate module, and output the connection terminal of the first transmission gate connecting the drain of the first NMOS transistor MN0 and the drain of the first PMOS transistor MP0 as the output terminal of the transmission gate module The first input signal A passes through the signal A1 of the first transmission gate; it can also be reversed, and the connection end of the first transmission gate connected to the drain of the first NMOS transistor MN0 and the drain of the first PMOS transistor MP0 is used as a transmission gate The input terminal of the module is connected to the first input signal A, and the connection terminal of the first transmission gate connecting the source of the first NMOS transistor MN0 and the source of the first PMOS transistor MP0 is used as the output terminal of the transmission gate module to output the first input Signal A passes through signal A1 of the first transmission gate. The same is true for the second transmission gate, which will not be repeated here.

Since the input power supply DVDD and the ground DGND are constantly input high level and low level respectively, the first NMOS transistor MN0 and the second NMOS transistor MN1 are always on, and the first PMOS transistor MP0 and the second PMOS transistor MP1 are also always on. , the signals A1 and B1 of the first input signal A and the second input signal B through the first transmission gate and the second transmission gate are always output. By adjusting the width-to-length ratios of the first NMOS transistor MN0 , the second NMOS transistor MN1 , the first PMOS transistor MP0 and the second PMOS transistor MP1 , the delay between the input signals A and B and the output signals A1 and B1 of the transmission gate module can be adjusted.

The output signals A1 and B1 of the transmission gate module are input into the NOT gate module. The NOT gate module includes two input terminals and two output terminals. The first input terminal of the NOT gate module is connected to the signal A1, and the second input terminal of the NOT gate module Connect the signal B1, the signal A1 is inverted to obtain the signal A2 and output from the first output terminal of the NOT gate module, and the signal B1 is inverted to obtain the signal B2 and output from the second output terminal of the NOT gate module.

As shown in Figure 4, an implementation structure of the NOT gate module is provided, including a first inverter INV1 and a second inverter INV2; the input terminal of the first inverter INV1 is connected to the signal A1 output by the transmission gate module, The output terminal of the first inverter INV1 outputs signal A2 and is connected to the first input terminal of the first NAND gate NAND1 in the NAND gate module, the power supply pole of the first inverter INV1 is connected to the input power supply, and the first inverter INV1 The ground terminal of the second inverter INV2 is connected to the signal B1 output by the transmission gate module, and the output terminal of the second inverter INV2 outputs the signal B2 and is connected to the second NAND gate NAND2 in the NAND gate module. One input terminal, the power pole of the second inverter INV2 is connected to the input power supply, and the ground terminal of the second inverter INV2 is grounded.

The first inverter INV1 and the second inverter INV2 perform non-operations on the input signal A1 and signal B1 respectively. If the input signal is high level, it will output low level; if the input signal is low level, it will output high level.

In path 2, the drive module includes a first drive unit and a second drive unit, the input of the first drive unit is connected to the first input signal A, and its output is connected to the second input of the second NAND gate NAND2 in the NAND gate module terminal; the input terminal of the second drive unit is connected to the second input signal B, and its output terminal is connected to the second input terminal of the first NAND gate NAND1 in the NAND gate module. In some embodiments, the first driving unit and the second driving unit may be composed of an even number of cascaded inverters, as shown in FIG. 5 , in this embodiment, the third inverter INV3 and the fourth inverter INV4 are used The first drive unit is formed by cascading, the second drive unit is formed by cascading the fifth inverter INV5 and the sixth inverter INV6, the input terminal of the third inverter INV3 is connected to the first input signal A, and the third inverter The output terminal of INV3 is connected to the input terminal of the fourth inverter INV4; the output terminal of the fourth inverter INV4 outputs signal A3 and is connected to the second input terminal of the second NAND gate NAND2 in the NAND gate module; the fifth inverter The input terminal of the inverter INV5 is connected to the second input signal B, the output terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6; the output terminal of the sixth inverter INV6 outputs the signal B3 and is connected to the NAND gate module The second input terminal of the first NAND gate NAND1; the power supply poles of the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5 and the sixth inverter INV6 are connected to the input power supply, and the ground terminal is grounded .

In this embodiment, both the first drive unit and the second drive unit are composed of two cascaded inverters. Taking the first drive unit as an example, if the first input signal A is high, after passing through the third inverter INV3 Output low level, the output of the fourth inverter INV4 becomes high level; if the first input signal 1 is low, output high level after passing through the third inverter INV3, and output through the fourth inverter INV4 becomes low again. Since the third inverter INV3 and the fourth inverter INV4 are proportionally amplified, the inverter chain formed increases the current driving capability, and the third inverter INV3 and the fourth inverter are formed by adjusting The MOS aspect ratio of INV4 can adjust the delay of the output signal A3 after the first input signal A passes through the first driving unit. The same is true for the second drive unit, which will not be repeated here.

The present invention makes the delay of the signal arriving at the NAND gate module as consistent as possible by controlling the delay of the drive module and the transmission gate module. The gate module uses an inverter to achieve inversion, then the PMOS and NMOS sizes of the transmission gate module and the driver module can be designed to be consistent with the PMOS and NMOS sizes of the NOT module. In the inverter used by the module, the PMOS width-to-length ratio is 4.4um/60nm, and the NMOS width-to-length ratio is 1.44um/60nm. The width-to-length ratio of the two transmission gates is also set to be the same, so the delay of the signal reaching the NAND gate module can be realized. As consistent as possible, and then implement the XOR gate logic in the NAND gate module.

The structure of the NAND gate module is as shown in Figure 6, including the first NAND gate NAND1, the second NAND gate NAND2 and the third NAND gate NAND3, the first input end of the first NAND gate NAND1 is connected to the output of the NAND gate module signal A2 of the first NAND gate NAND1, the second input terminal of the first NAND gate is connected to the signal B3 output by the drive module, the output terminal of the first NAND gate NAND1 is connected to the first input terminal of the third NAND gate NAND3, and the first NAND gate The power pole of NAND1 is connected to the input power supply, and the ground terminal of the first NAND gate NAND1 is grounded. The first input terminal of the second NAND gate NAND2 is connected to the signal B2 output by the NOT gate module, the second input terminal of the second NAND gate NAND2 is connected to the signal A3 output by the driving module, and the output terminal of the second NAND gate NAND2 is connected to the first output terminal of the NAND gate NAND2. The second input terminal of the three NAND gate NAND3, the power supply pole of the second NAND gate NAND2 is connected to the input power supply, and the ground terminal of the second NAND gate NAND2 is grounded. The output terminal of the third NAND gate NAND3 outputs the output signal Y of the XOR gate circuit, the power supply pole of the third NAND gate NAND3 is connected to the input power supply, and the ground terminal of the third NAND gate NAND3 is grounded.

The connection mode of the three NAND gates constitutes the exclusive OR gate logic. The operation logic of the exclusive OR gate is: when the input signal 1 is high and the input signal 2 is low, the output signal is high; when the input signal 1 is low, the input When signal 2 is low, the output signal is low; when input signal 1 is low and input signal 2 is high, the output signal is high; when input signal 1 is high and input signal 2 is high, the output signal is low.

If the first input signal A is low and the second input signal B is low, the first input signal A passes through the transmission gate module to obtain a low-level signal A1, and then passes through the NOT gate module to obtain a high-level signal A2, which is input to the first AND The first input terminal of the NAND gate NAND1, the second input signal B is input to the second input terminal of the first NAND gate NAND1 through the drive module to obtain a low level signal B3, at this time, the first input of the first NAND gate NAND1 The signal at the second input terminal is high and the signal at the second input terminal is low, so the output signal is high and output to the first input terminal of the third NAND gate NAND3. The second input signal B passes through the transmission gate module to obtain a low-level signal B1, and then passes through the NOT gate module to obtain a high-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, and the first input signal A passes through the drive module. The low-level signal A3 is input to the second input terminal of the second NAND gate NAND2. At this time, the signal at the first input terminal of the second NAND gate NAND2 is high and the signal at the second input terminal is low, so the output signal is High and output to the second input terminal of the third NAND gate NAND3, the two input signals of the third NAND gate NAND1 are both high, so the output signal Y of the exclusive OR gate is low.

If the first input signal A is low and the second input signal B is high, the first input signal A passes through the transmission gate module to obtain a low-level signal A1, and then passes through the NOT gate module to obtain a high-level signal A2, which is input to the first AND The first input terminal of the NAND gate NAND1, the second input signal B is input to the second input terminal of the first NAND gate NAND1 through the driving module to obtain a high level signal B3, at this time the first input of the first NAND gate NAND1 The signal at the terminal is high and the signal at the second input terminal is high, so the output signal is low and output to the first input terminal of the third NAND gate NAND3. The second input signal B passes through the transmission gate module to obtain a high-level signal B1, and then passes through the NOT gate module to obtain a low-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, and the first input signal A passes through the drive module. The low-level signal A3 is input to the second input terminal of the second NAND gate NAND2. At this time, the signal at the first input terminal of the second NAND gate NAND2 is low, and the signal at the second input terminal is low, so the output signal is High and output to the second input terminal of the third NAND gate NAND3, the signal of the first input terminal of the third NAND gate NAND1 is low, the signal of the second input terminal is high, so the output signal Y of the exclusive OR gate is high.

If the first input signal A is high and the second input signal B is low, the first input signal A passes through the transmission gate module to obtain a high-level signal A1, and then passes through the NOT gate module to obtain a low-level signal A2, which is input to the first AND The first input terminal of the NAND gate NAND1, the second input signal B is input to the second input terminal of the first NAND gate NAND1 through the drive module to obtain a low level signal B3, at this time, the first input of the first NAND gate NAND1 The signal at the terminal is low and the signal at the second input terminal is low, so the output signal is high and output to the first input terminal of the third NAND gate NAND3. The second input signal B passes through the transmission gate module to obtain a low-level signal B1, and then passes through the NOT gate module to obtain a high-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, and the first input signal A passes through the drive module. The high-level signal A3 is input to the second input terminal of the second NAND gate NAND2. At this time, the signal at the first input terminal of the second NAND gate NAND2 is high, and the signal at the second input terminal is high, so the output signal is Low and output to the second input terminal of the third NAND gate NAND3, the signal of the first input terminal of the third NAND gate NAND1 is high, the signal of the second input terminal is low, so the output signal Y of the exclusive OR gate is high.

If the first input signal A is high and the second input signal B is high, the first input signal A passes through the transmission gate module to obtain a high-level signal A1, and then passes through the NOT gate module to obtain a low-level signal A2, which is input to the first AND The first input terminal of the NAND gate NAND1, the second input signal B is input to the second input terminal of the first NAND gate NAND1 through the driving module to obtain a high level signal B3, at this time the first input of the first NAND gate NAND1 The signal at the second input terminal is low and the signal at the second input terminal is high, so the output signal is high and output to the first input terminal of the third NAND gate NAND3. The second input signal B passes through the transmission gate module to obtain a high-level signal B1, and then passes through the NOT gate module to obtain a low-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, and the first input signal A passes through the drive module. The high-level signal A3 is input to the second input terminal of the second NAND gate NAND2. At this time, the signal at the first input terminal of the second NAND gate NAND2 is low and the signal at the second input terminal is high, so the output signal is High and output to the second input terminal of the third NAND gate NAND3, the two input signals of the third NAND gate NAND1 are both high, so the output signal Y of the exclusive OR gate is low.

Through the above analysis, it can be seen that the exclusive OR gate circuit proposed by the present invention realizes the exclusive OR gate logic, and since the present invention sets the transmission gate module on path 1 and the drive module on path 2, the delay between the transmission gate module and the drive module All of them can be adjusted. By adjusting the size of the MOS transistors that constitute the transmission gate module and the drive module, the delay of the signal passing through the transmission gate module and the drive module can be adjusted. As shown in Figure 2, the signals A and B pass through the transmission gate module and the NOT gate module to the NAND gate module are A2 and B2, and the signals A and B pass through the drive module and reach the NAND gate module are A3 and B3. The delay of the transmission gate module and the drive module is adjusted so that the delays of the signals A2 and B2 and A3 and B3 are as consistent as possible, and the delay difference becomes smaller. Output signal Y, so the change of adjacent pulses of the same signal of Y is reduced; at the same time, the driving ability of the subsequent circuit is also increased.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (5)

1. An XOR gate circuit that reduces the delay of the input signal of the NAND gate, including a NOT gate module and a NAND gate module, The NAND gate module includes a first NAND gate, a second NAND gate and a third NAND gate, the first input of the third NAND gate is connected to the output of the first NAND gate, and the second input of the NAND gate is Connect the output end of the second NAND gate, and its output end outputs the output signal of the XOR gate circuit; The NOT gate module includes two input terminals and two output terminals, and the signal at the first input terminal of the NOT gate module is output from the first output terminal of the NOT gate module to the first NAND gate after inversion. An input terminal, the signal of the second input terminal of the NOT gate module is output from the second output terminal of the NOT gate module to the first input terminal of the second NAND gate after inversion; It is characterized in that the XOR gate circuit also includes a transmission gate module and a drive module, The transmission gate module includes a first transmission gate and a second transmission gate that are constantly turned on, and the two connection ends of the first transmission gate are respectively connected to the first input signal of the XOR gate circuit and the second transmission gate of the NOT gate module. An input terminal, the two connection terminals of the second transmission gate are respectively connected to the second input signal of the XOR gate circuit and the second input terminal of the NOT gate module; The drive module includes a first drive unit and a second drive unit, the input end of the first drive unit is connected to the first input signal of the XOR gate circuit, and the output end of the first drive unit is connected to the second input end of the second NAND gate; The input end of the second driving unit is connected to the second input signal of the XOR gate circuit, and the output end thereof is connected to the second input end of the first NAND gate; By adjusting the delay of the transmission gate module and the driving module, the signals at the two input terminals of the first NAND gate and the signals at the two input terminals of the second NAND gate have the same delay as possible. 2. The XOR gate circuit for reducing NAND gate input signal delay according to claim 1, wherein the first transmission gate and the second transmission gate have the same structure, and the first transmission gate includes the first transmission gate An NMOS transistor and a first PMOS transistor, the grid of the first NMOS transistor and the substrate of the first PMOS transistor are connected to the input power supply, the grid of the first PMOS transistor and the substrate of the first NMOS transistor are grounded, and the substrate of the first NMOS transistor is grounded. The source is interconnected with the source of the first PMOS transistor and used as a connection terminal of the first transmission gate, and the drain of the first NMOS transistor is interconnected with the drain of the first PMOS transistor and used as another connection of the first transmission gate end. 3. The XOR gate circuit for reducing the delay of the input signal of the NAND gate according to claim 1 or 2, wherein the first drive unit and the second drive unit each include an even number of cascaded inverting device. 4. The XOR gate circuit reducing the delay of the input signal of the NAND gate according to claim 3, wherein the NOT gate module comprises a first inverter and a second inverter, and the first inverter The input terminal of the inverter is used as the first input terminal of the NOT gate module, and its output terminal is used as the first output terminal of the described NOT gate module; the input terminal of the second inverter is used as the second input terminal of the NOT gate module , the output end of which is used as the second output end of the NOT gate module. 5. The XOR gate circuit for reducing the delay of the input signal of the NAND gate according to claim 4, wherein the first drive unit and the second drive unit each comprise two cascaded inverters, The inverter in the NOT gate module and the driving module is composed of MOS tubes, and the size of the MOS tubes in the driving module and the transmission gate module is designed to be consistent with the size of the MOS tubes in the NOT gate module.

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