CN112491411A - XOR gate circuit for reducing delay of input signal of NAND gate - Google Patents
XOR gate circuit for reducing delay of input signal of NAND gate Download PDFInfo
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Abstract
一种减小与非门输入信号延时的异或门电路，包括传输门模块、非门模块、与非门模块和驱动模块，在路径1中输入信号A和B经过传输门模块和非门模块后输入与非门模块，在路径2中输入信号A和B经过驱动模块后输入与非门模块，随后与非门模块利用三个与非门实现异或门逻辑得到异或门电路的输出信号。本发明中驱动模块和传输门模块的延时可调，因此可以通过控制驱动模块和传输门模块的延时，使得输入信号A和B经过传输门模块和非门模块的延时与输入信号A和B经过驱动模块的延时尽可能一致，从而改善由于异或门电路中与非门输入信号延时造成的对输出信号脉宽和延时的影响，同时也增大了对后续电路的驱动能力。
An XOR gate circuit that reduces the delay of an input signal of a NAND gate, comprising a transmission gate module, a NOT gate module, a NAND gate module and a driving module, in path 1, the input signals A and B pass through the transmission gate module and the NOT gate After the module, the NAND gate module is input. In path 2, the input signals A and B are input to the NAND gate module after passing through the driver module. Then the NAND gate module uses three NAND gates to realize the XOR gate logic to obtain the output of the XOR gate circuit. Signal. In the present invention, the delay of the driving module and the transmission gate module is adjustable, so the delay of the driving module and the transmission gate module can be controlled, so that the input signals A and B pass through the delay of the transmission gate module and the not gate module and the input signal A The delay of B and B through the driving module is as consistent as possible, thereby improving the influence on the pulse width and delay of the output signal caused by the delay of the input signal of the NAND gate in the XOR gate circuit, and also increasing the driving of the subsequent circuits. ability.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and relates to an exclusive-OR gate circuit for reducing delay of input signals of a NAND gate.
Background
Fig. 1 shows a conventional xor gate circuit, which operates according to the following principle: the two input signals of the exclusive-or gate circuit are a first input signal a and a second input signal B, the non-operation output a 'of the first input signal a and the second input signal B are input to the first NAND gate NAND1 for NAND operation, the non-operation output B' of the first input signal a and the second input signal B is input to the second NAND gate NAND2 for NAND operation, the outputs of the first NAND gate NAND1 and the second NAND gate 2 are input to the third NAND gate NAND3 for NAND operation, and the obtained output signal Y of the third NAND gate 3 is the exclusive-or (XOR) operation output of the first input signal a and the second input signal B.
However, in the conventional xor gate circuit, due to the inherent delay of the inverter, the first input signal a and the second input signal B are delayed by the NAND gate, so that the delay of the two signals input to the first NAND gate NAND1 is different, the delay of the two signals input to the second NAND gate NAND2 is also different, and further, the pulse width and the delay of the output signal Y are affected.
Disclosure of Invention
Aiming at the problem that the pulse width and the delay of the output signal Y of the XOR gate circuit are influenced by the fact that the two signals input into the NAND gate circuit are different due to the inherent delay of the inverter in the traditional XOR gate circuit, the invention provides the XOR gate circuit which can reduce the delay of the input signal of the NAND gate circuit and enable the delay of the signal reaching the NAND gate module to be consistent as much as possible.
The technical scheme of the invention is as follows:
an XOR gate circuit for reducing the delay of input signals of a NAND gate comprises a NOT gate module and a NAND gate module,
the NAND gate module comprises a first NAND gate, a second NAND gate and a third NAND gate, wherein the first input end of the third NAND gate is connected with the output end of the first NAND gate, the second input end of the third NAND gate is connected with the output end of the second NAND gate, and the output end of the third NAND gate outputs the output signal of the XOR gate circuit;
the signal of the first input end of the NOT gate module is output to the first input end of the first NAND gate from the first output end of the NOT gate module after phase inversion, and the signal of the second input end of the NOT gate module is output to the first input end of the second NAND gate from the second output end of the NOT gate module after phase inversion;
the exclusive-or gate circuit further comprises a transmission gate module and a driving module,
the transmission gate module comprises a first transmission gate and a second transmission gate which are constantly conducted, two connecting ends of the first transmission gate are respectively connected with a first input signal of the XOR gate circuit and a first input end of the NOT gate module, and two connecting ends of the second transmission gate are respectively connected with a second input signal of the XOR gate circuit and a second input end of the NOT gate module;
the driving module comprises a first driving unit and a second driving unit, the input end of the first driving unit is connected with the first input signal of the XOR gate circuit, and the output end of the first driving unit is connected with the second input end of the second NAND gate; the input end of the second driving unit is connected with the second input signal of the XOR gate circuit, and the output end of the second driving unit is connected with the second input end of the first NAND gate;
by adjusting the time delay of the transmission gate module and the driving module, the signals of the two input ends of the first NAND gate and the signals of the two input ends of the second NAND gate have the same time delay as much as possible.
Specifically, the first transmission gate and the second transmission gate have the same structure, the first transmission gate includes a first NMOS transistor and a first PMOS transistor, a gate of the first NMOS transistor and a substrate of the first PMOS transistor are connected to an input power supply, a gate of the first PMOS transistor and a substrate of the first NMOS transistor are grounded, a source of the first NMOS transistor and a source of the first PMOS transistor are connected to each other and serve as one connection end of the first transmission gate, and a drain of the first NMOS transistor and a drain of the first PMOS transistor are connected to each other and serve as the other connection end of the first transmission gate.
Specifically, the first driving unit and the second driving unit each include an even number of cascaded inverters.
Specifically, the not gate module includes a first inverter and a second inverter, an input end of the first inverter is used as a first input end of the not gate module, and an output end of the first inverter is used as a first output end of the not gate module; the input end of the second inverter is used as the second input end of the not gate module, and the output end of the second inverter is used as the second output end of the not gate module.
Specifically, the first driving unit and the second driving unit both comprise two cascaded inverters, the inverters in the inverter module and the driving module are composed of MOS transistors, and the sizes of the MOS transistors in the driving module and the transmission gate module are designed to be the same as the sizes of the MOS transistors in the inverter module.
The working principle of the invention is as follows: the first input signal A and the second input signal B reach the NAND gate module through two paths, a transmission gate module and a NOT gate module are arranged in a path 1, and the first input signal A and the second input signal B pass through a transmission gate structure in the path 1 and then do NOT operation; the path 2 is provided with a driving module, and the first input signal A and the second input signal B in the path 2 are not subjected to non-operation and are input into the NAND gate module after being driven; because the delay of the transmission gate module and the drive module is adjustable, the delay of the first input signal a and the delay of the second input signal B reaching the first NAND gate NAND1 and the second NAND gate NAND2 in the NAND gate module after passing through two paths can be made as same as possible by adjusting the delay of the transmission gate module in the path 1 and the delay of the drive module in the path 2, so that the delay difference of the input signals of the first NAND gate NAND1 and the second NAND gate 2 is reduced.
The invention has the beneficial effects that: the exclusive-OR gate circuit provided by the invention is provided with two paths, input signals A and B respectively reach the NAND gate module through the transmission gate module and the NOR gate module in the path 1, the input signals A and B reach the NAND gate module through the driving module in the path 1, and the time delay of the signals reaching the NAND gate module is made to be as consistent as possible by adjusting the time delay of the driving module of the transmission gate module, so that the time delay of the input signals of the NAND gate is reduced, and the driving capability of a subsequent circuit is also increased.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a schematic connection diagram of a conventional exclusive-or gate circuit.
Fig. 2 is a block diagram of an xor gate circuit for reducing delay of an input signal of a nand gate according to the present invention.
Fig. 3 is a circuit diagram of an implementation of a pass gate module in an xor gate circuit for reducing delay of an input signal of a nand gate according to the present invention.
Fig. 4 is a circuit diagram of an implementation of a nor module in an xor gate circuit for reducing delay of an input signal of a nand according to the present invention.
Fig. 5 is a circuit diagram of an implementation of the driving module in the xor gate circuit for reducing the delay of the input signal of the nand gate according to the present invention.
Fig. 6 is a circuit diagram of an implementation of the nand gate module in the xor gate circuit for reducing the delay of the input signal of the nand gate according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
As shown in fig. 2, the present invention provides an xor gate circuit for reducing delay of nand gate input signals, which includes a nor gate module, a nand gate module, a transmission gate module and a driving module, wherein the xor gate circuit has two input signals, i.e., a first input signal a and a second input signal B, and the first input signal a and the second input signal B reach the nand gate module through a path 1 and a path 2, respectively.
The path 1 includes a transmission gate module and a not gate module, the transmission gate module includes a first transmission gate and a second transmission gate which are constantly turned on, and may be formed by MOS transistors, as shown in fig. 3, the first transmission gate includes a first NMOS transistor MN0 and a first PMOS transistor MP0, a source of the first NMOS transistor MN0 is connected to a source of the first PMOS transistor MP0 and serves as one connection end of the first transmission gate, a drain of the first NMOS transistor MN0 is connected to a drain of the first PMOS transistor MP0 and serves as the other connection end of the first transmission gate, a substrate of the first NMOS transistor MN0 is grounded, a gate of the first NMOS transistor MN0 is connected to an input power supply, a substrate of the first PMOS transistor MP0 is connected to the input power supply, and a gate of the first PMOS transistor MP0 is grounded. The second transmission gate comprises a second NMOS transistor MN1 and a second PMOS transistor MP1, the source electrode of the second NMOS transistor MN1 is connected with the source electrode of the second PMOS transistor MP1 and serves as one connection end of the second transmission gate, the drain electrode of the second NMOS transistor MN1 is connected with the drain electrode of the second PMOS transistor MP1 and serves as the other connection end of the second transmission gate, the substrate of the second NMOS transistor MN1 is grounded, the grid electrode of the second NMOS transistor MN2 is connected with an input power supply, the substrate of the second PMOS transistor MP1 is connected with the input power supply, and the grid electrode of the second PMOS transistor MP2 is grounded.
For example, in the embodiment shown in fig. 3, the connection end of the first transmission gate, to which the source of the first NMOS transistor MN0 and the source of the first PMOS transistor MP0 are connected, may be used as the input end of the transmission gate module to connect the first input signal a, and the connection end of the first transmission gate, to which the drain of the first NMOS transistor MN0 and the drain of the first PMOS transistor MP0 are connected, may be used as the output end of the transmission gate module to output the signal a1 of the first input signal a passing through the first transmission gate; conversely, the connection end of the first transmission gate, where the drain of the first NMOS transistor MN0 is connected to the drain of the first PMOS transistor MP0, serves as the input end of the transmission gate module and is connected to the first input signal a, and the connection end of the first transmission gate, where the source of the first NMOS transistor MN0 is connected to the source of the first PMOS transistor MP0, serves as the output end of the transmission gate module and outputs the signal a1, where the first input signal a passes through the first transmission gate. The second transmission gate is similar and will not be described herein.
Since the input power DVDD and the ground DGND are respectively and constantly input a high level and a low level, the first NMOS transistor MN0 and the second NMOS transistor MN1 are always in an on state, the first PMOS transistor MP0 and the second PMOS transistor MP1 are also always in an on state, and the first input signal a and the second input signal B are always output through the signals a1 and B1 of the first transmission gate and the second transmission gate. By adjusting the width-to-length ratio of the first NMOS transistor MN0, the second NMOS transistor MN1, the first PMOS transistor MP0 and the second PMOS transistor MP1, the delay of the input signals a and B and the transmission gate module output signals a1 and B1 can be adjusted.
Output signals A1 and B1 of the transmission gate module are input into the NOT gate module, the NOT gate module comprises two input ends and two output ends, a first input end of the NOT gate module is connected with the signal A1, a second input end of the NOT gate module is connected with the signal B1, the signal A1 obtains a signal A2 after phase inversion and is output from a first output end of the NOT gate module, and the signal B1 obtains a signal B2 after phase inversion and is output from a second output end of the NOT gate module.
One implementation structure of the not gate module is shown in fig. 4, and includes a first inverter INV1 and a second inverter INV 2; the input end of the first inverter INV1 is connected to the signal a1 output by the transmission gate module, the output end of the first inverter INV1 outputs the signal a2 and is connected to the first input end of the first NAND gate NAND1 in the NAND gate module, the power supply electrode of the first inverter INV1 is connected to the input power supply, and the ground end of the first inverter INV1 is grounded; the input end of the second inverter INV2 is connected to the signal B1 output by the transmission gate module, the output end of the second inverter INV2 outputs the signal B2 and is connected to the first input end of the second NAND gate NAND2 in the NAND gate module, the power supply electrode of the second inverter INV2 is connected to the input power supply, and the ground end of the second inverter INV2 is grounded.
The first inverter INV1 and the second inverter INV2 respectively negate the input signal a1 and signal B1, and output a low level if the input signal is a high level; if the input signal is at low level, then output high level.
In path 2, the driving module includes a first driving unit and a second driving unit, an input end of the first driving unit is connected to the first input signal a, and an output end of the first driving unit is connected to a second input end of a second NAND gate NAND2 in the NAND gate module; the input end of the second driving unit is connected to the second input signal B, and the output end of the second driving unit is connected to the second input end of the first NAND gate NAND1 in the NAND gate module. In some embodiments, the first driving unit and the second driving unit may be formed by an even number of cascaded inverters, as shown in fig. 5, in this embodiment, the first driving unit is formed by cascading a third inverter INV3 and a fourth inverter INV4, the second driving unit is formed by cascading a fifth inverter INV5 and a sixth inverter INV6, an input end of the third inverter INV3 is connected to the first input signal a, and an output end of the third inverter INV3 is connected to an input end of the fourth inverter INV 4; the output end of the fourth inverter INV4 outputs the signal A3 and is connected to the second input end of the second NAND gate NAND2 in the NAND gate module; the input end of the fifth inverter INV5 is connected to the second input signal B, and the output end of the fifth inverter INV5 is connected to the input end of the sixth inverter INV 6; the output end of the sixth inverter INV6 outputs the signal B3 and is connected to the second input end of the first NAND gate NAND1 in the NAND gate module; the power supply electrodes of the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5 and the sixth inverter INV6 are connected to the input power supply, and the ground terminal is grounded.
In this embodiment, the first driving unit and the second driving unit are both composed of 2 cascaded inverters, and taking the first driving unit as an example, if the first input signal a is high, the first input signal a passes through the third inverter INV3 and then outputs a low level, and the first input signal a passes through the fourth inverter INV4 and then becomes a high level; if the first input signal 1 is low, it goes high through the third inverter INV3, and goes low through the fourth inverter INV 4. Since the third inverter INV3 and the fourth inverter INV4 are in an equal-ratio amplification relationship, the inverter chain increases the driving capability of current, and the delay of the signal A3 output after the first input signal a passes through the first driving unit can be adjusted by adjusting the width-to-length ratio of MOS transistors forming the third inverter INV3 and the fourth inverter INV 4. The second driving unit has the same structure, and is not described herein again.
For example, in the embodiment, the driving module is provided with two cascaded inverters to form a driving unit, the inverter is adopted for the NOT module to realize phase inversion, the sizes of the PMOS and the NMOS of the transmission gate module and the driving module can be designed to be consistent with those of the PMOS and the NMOS of the NOT module, and if the sizes of the PMOS and the NMOS of the inverter used by the NOT module and the driving module are set to be 4.4um/60nm and 1.44um/60nm respectively under the 40nm process, the delay of the signal reaching the NOT module can be realized to be consistent as much as possible, and then the logic of an exclusive-OR gate is realized in the NOT module.
The NAND gate module is configured as shown in fig. 6, and includes a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3, wherein a first input terminal of the first NAND gate NAND1 is connected to a signal a2 output by the NAND gate module, a second input terminal of the first NAND gate NAND1 is connected to a signal B3 output by the driving module, an output terminal of the first NAND gate NAND1 is connected to a first input terminal of the third NAND gate 3, a power supply terminal of the first NAND gate 1 is connected to an input power supply, and a ground terminal of the first NAND gate 1 is grounded. The first input end of the second NAND gate NAND2 is connected with the signal B2 output by the NAND gate module, the second input end of the second NAND gate NAND2 is connected with the signal A3 output by the driving module, the output end of the second NAND gate NAND2 is connected with the second input end of the third NAND gate NAND3, the power supply electrode of the second NAND gate NAND2 is connected with the input power supply, and the ground end of the second NAND gate 2 is grounded. The output end of the third NAND gate NAND3 outputs the output signal Y of the xor gate, the power supply electrode of the third NAND gate NAND3 is connected with the input power supply, and the ground end of the third NAND gate NAND3 is grounded.
The connection mode of the three NAND gates forms an XOR gate logic, and the operational logic of the XOR gate is as follows: when the input signal 1 is high and the input signal 2 is low, the output signal is high; when the input signal 1 is low and the input signal 2 is low, the output signal is low; when the input signal 1 is low and the input signal 2 is high, the output signal is high; when input signal 1 is high and input signal 2 is high, the output signal is low.
If the first input signal a is low and the second input signal B is low, the first input signal a passes through the pass gate module to obtain a low-level signal a1, and then passes through the not gate module to obtain a high-level signal a2, which is input to the first input terminal of the first NAND gate NAND1, the second input signal B passes through the driving module to obtain a low-level signal B3, which is input to the second input terminal of the first NAND gate 1, at this time, the signal at the first input terminal of the first NAND gate 1 is high, and the signal at the second input terminal is low, so the output signal is high and is output to the first input terminal of the third NAND gate 3. The second input signal B passes through the pass gate module to obtain a low-level signal B1, and then passes through the not gate module to obtain a high-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, the first input signal a passes through the driving module to obtain a low-level signal A3, which is input to the second input terminal of the second NAND gate NAND2, at this time, the signal at the first input terminal of the second NAND gate NAND2 is high, the signal at the second input terminal is low, so the output signal is high and is output to the second input terminal of the third NAND gate NAND3, and both input signals of the third NAND gate 1 are high, so the output signal Y of the xor gate is low.
If the first input signal a is low and the second input signal B is high, the first input signal a passes through the pass gate module to obtain a low-level signal a1, and then passes through the not gate module to obtain a high-level signal a2, and the high-level signal a2 is input to the first input terminal of the first NAND gate NAND1, and the second input signal B passes through the driving module to obtain a high-level signal B3, and the high-level signal B is input to the second input terminal of the first NAND gate NAND1, at this time, the first input terminal signal of the first NAND gate NAND1 is high and the second input terminal signal is high, so that the output signal is low and is output to the first input terminal of the third NAND gate 3. The second input signal B passes through the pass gate module to obtain a high-level signal B1, and then passes through the not gate module to obtain a low-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, the first input signal a passes through the driving module to obtain a low-level signal A3, which is input to the second input terminal of the second NAND gate NAND2, at this time, the first input terminal signal of the second NAND gate NAND2 is low, the second input terminal signal is low, so that the output signal is high and output to the second input terminal of the third NAND gate NAND3, the first input terminal signal of the third NAND gate 1 is low, the second input terminal signal is high, so that the output signal Y of the xor gate is high.
If the first input signal a is high and the second input signal B is low, the first input signal a passes through the pass gate module to obtain a high-level signal a1, and then passes through the not gate module to obtain a low-level signal a2, and the low-level signal a2 is input to the first input terminal of the first NAND gate NAND1, and the second input signal B passes through the driving module to obtain a low-level signal B3, and the low-level signal B is input to the second input terminal of the first NAND gate NAND1, at this time, the first input terminal of the first NAND gate NAND1 is low and the second input terminal is low, so that the output signal is high and is output to the first input terminal of the third NAND gate 3. The second input signal B passes through the pass gate module to obtain a low-level signal B1, and then passes through the not gate module to obtain a high-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, the first input signal a passes through the driving module to obtain a high-level signal A3, which is input to the second input terminal of the second NAND gate NAND2, at this time, the first input terminal signal of the second NAND gate 2 is high, the second input terminal signal is high, so that the output signal is low and output to the second input terminal of the third NAND gate NAND3, the first input terminal signal of the third NAND gate 1 is high, the second input terminal signal is low, so that the output signal Y of the xor gate is high.
If the first input signal a is high and the second input signal B is high, the first input signal a passes through the transmission gate module to obtain a high-level signal a1, passes through the not gate module to obtain a low-level signal a2, and is input to the first input end of the first NAND gate NAND1, the second input signal B passes through the driving module to obtain a high-level signal B3, and is input to the second input end of the first NAND gate NAND1, at this time, the first input end signal of the first NAND gate NAND1 is low and the second input end signal is high, so that the output signal is high and is output to the first input end of the third NAND gate 3. The second input signal B passes through the pass gate module to obtain a high-level signal B1, and then passes through the not gate module to obtain a low-level signal B2, which is input to the first input terminal of the second NAND gate NAND2, the first input signal a passes through the driving module to obtain a high-level signal A3, which is input to the second input terminal of the second NAND gate NAND2, at this time, the signal at the first input terminal of the second NAND gate NAND2 is low, the signal at the second input terminal is high, so that the output signal is high and output to the second input terminal of the third NAND gate NAND3, and both input signals of the third NAND gate 1 are high, so the output signal Y of the xor gate is low.
According to the analysis, the XOR gate circuit provided by the invention realizes the logic of the XOR gate, and because the transmission gate module is arranged on the path 1 and the driving module is arranged on the path 2, the time delay of the transmission gate module and the driving module can be adjusted, and the time delay of the signal passing through the transmission gate module and the driving module can be adjusted by adjusting the sizes of MOS (metal oxide semiconductor) tubes forming the transmission gate module and the driving module. As shown in fig. 2, signals a and B passing through the pass gate module and the not gate module to reach the nand gate module are a2 and B2, signals a and B passing through the driving module to reach the nand gate module are A3 and B3, and the delays of the pass gate module and the driving module are adjusted, so that the delays of the signals a2 and B2 are as consistent as possible with the delays of the signals A3 and B3, the delay difference is small, and the output signal Y of the xor gate circuit is obtained after the xor gate module performs xor logic operation, so that the adjacent pulse variation of the same signal of Y is reduced; and meanwhile, the driving capability of a subsequent circuit is also increased.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (5)
1. An XOR gate circuit for reducing the delay of input signals of a NAND gate comprises a NOT gate module and a NAND gate module,
the NAND gate module comprises a first NAND gate, a second NAND gate and a third NAND gate, wherein the first input end of the third NAND gate is connected with the output end of the first NAND gate, the second input end of the third NAND gate is connected with the output end of the second NAND gate, and the output end of the third NAND gate outputs the output signal of the XOR gate circuit;
the signal of the first input end of the NOT gate module is output to the first input end of the first NAND gate from the first output end of the NOT gate module after phase inversion, and the signal of the second input end of the NOT gate module is output to the first input end of the second NAND gate from the second output end of the NOT gate module after phase inversion;
characterized in that the XOR gate circuit also comprises a transmission gate module and a driving module,
the transmission gate module comprises a first transmission gate and a second transmission gate which are constantly conducted, two connecting ends of the first transmission gate are respectively connected with a first input signal of the XOR gate circuit and a first input end of the NOT gate module, and two connecting ends of the second transmission gate are respectively connected with a second input signal of the XOR gate circuit and a second input end of the NOT gate module;
the driving module comprises a first driving unit and a second driving unit, the input end of the first driving unit is connected with the first input signal of the XOR gate circuit, and the output end of the first driving unit is connected with the second input end of the second NAND gate; the input end of the second driving unit is connected with the second input signal of the XOR gate circuit, and the output end of the second driving unit is connected with the second input end of the first NAND gate;
by adjusting the time delay of the transmission gate module and the driving module, the signals of the two input ends of the first NAND gate and the signals of the two input ends of the second NAND gate have the same time delay as much as possible.
2. The xor gate circuit of claim 1, wherein the first transmission gate and the second transmission gate have the same structure, the first transmission gate includes a first NMOS transistor and a first PMOS transistor, a gate of the first NMOS transistor and a substrate of the first PMOS transistor are connected to the input power supply, a gate of the first PMOS transistor and a substrate of the first NMOS transistor are grounded, a source of the first NMOS transistor and a source of the first PMOS transistor are connected to each other and serve as one connection terminal of the first transmission gate, and a drain of the first NMOS transistor and a drain of the first PMOS transistor are connected to each other and serve as the other connection terminal of the first transmission gate.
3. The xor gate circuit of claim 1 or 2, wherein the first and second driving units each comprise an even number of cascaded inverters.
4. The xor gate circuit of claim 3, wherein the nor gate module comprises a first inverter and a second inverter, the input of the first inverter is the first input of the nor gate module, and the output thereof is the first output of the nor gate module; the input end of the second inverter is used as the second input end of the not gate module, and the output end of the second inverter is used as the second output end of the not gate module.
5. The XOR gate circuit of claim 4, wherein the first and second driving units each comprise two cascaded inverters, the inverters in the NOR gate module and the driving module are formed by MOS transistors, and the sizes of the MOS transistors in the driving module and the transmission gate module are designed to be the same as the sizes of the MOS transistors in the NOR gate module.
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