CN104967464A - CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter - Google Patents
CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter Download PDFInfo
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Abstract
The invention discloses a CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter, which includes a BPSK modulation module, a time-delay generation module, a pulse sequence generation module and an antenna. The BPSK modulation module processes an input digital signal DATA and a clock signal CLK, and generates a digital signal that meets BPSK modulation requirements. Each time-delay generation circuit of the time-delay generation module delays a modulation signal output from the BPSK modulation module on the basis of the time-delay characteristics of an inverter and then obtains different time delay outputs, and is used for controlling a corresponding pulse sequence generation circuit so that the pulse sequence generation circuit generates a pulse unit identical in time width. Each pulse sequence generation circuit of the pulse sequence generation module generates a monopulse signal, and all pulse signals are combined to form a pulse sequence, which is output by serving as an output signal and emitted by the antenna. Wireless emission signals generated by the transmitter meet the requirements of the frequency spectrum and the work frequency range of UWB.
Description
Technical field
The present invention relates to technical field of ultra wide band, be specifically related to a kind of CMOS digital BPSK modulating pulse radio ultra-wideband transmitter.
Background technology
Since 2002 FCC (Federal CommunicationsCommission, FCC) promulgate the spectrum criterion of ultra broadband (Ultra-Wideband, UWB), and by 3.1GHz～10。6GHz frequency range as civilian ultra-wideband devices exempt from authorized since frequency range, the features such as Ultra-wideband Communication Technology is simple with its system configuration, transmission rate is high, low in energy consumption receive application study and the concern in the fields such as Wireless Personal Network, wireless sensor network, biomedicine.
Current ultra-wideband communication system can be divided three classes: direct sequence spread spectrum (DS-SS), multi-band orthogonal frequency division multiplexing (MB-OFDM), impulse radio (IR).Wherein IR-UWB (impulse radio ultra-wideband) technology mainly utilizes a series of ultra-narrow pulse to carry out transfer of data as the carrier of information, without the need to any carrier signal, and narrow pulse signal can directly or be gone out by antenna transmission after buffer, therefore for other two kinds of modes, its system and circuit structure are more simple, power consumption and cost lower.Current existing many documents are studied IR-UWB transmitter, these IR-UWB transmitters mainly adopt following scheme to realize: scheme one first adopts digital delay circuit to obtain a burst pulse, burst pulse is after shaping network, frequency spectrum is shifted to required frequency range, and it is larger that this scheme needs to use a large amount of electric capacity, inductance and resistance device, therefore chip area and cost; First scheme first utilizes the delay of digital circuit to produce several burst pulses, again these burst pulses are synthesized the impulse waveform that a frequency spectrum meets the demands, this scheme is very strict to the requirement of Waveform composition part, and time of pulse combination, slightly the waveform that then obtains of deviation will distortion completely; In addition a kind of scheme is also had to be utilize the step recovery characteristics of avalanche diode to obtain required narrow pulse signal, the technique of the avalanche diode device that this scheme adopts because of it and the CMOS technology of standard incompatible, so be not suitable for very much carrying out CMOS integrated chip.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of CMOS digital BPSK modulating pulse radio ultra-wideband transmitter, it is for solving the generation of wireless transmission signal in IR-UWB communication system, meet the spectrum requirement of UWB, and pulse signal is operated in 3-5GHz frequency range.
For solving the problem, the present invention is achieved by the following technical solutions:
CMOS digital BPSK modulating pulse radio ultra-wideband transmitter, is made up of BPSK modulation module, time delay generation module, pulse train generation module and antenna; Time delay generation module comprises the time delay generative circuit of more than 2 grades and 2 grades, and pulse train generation module comprises the pulse train generation circuit of more than 2 grades and 2 grades, and every grade of corresponding one-level pulse train of time delay generative circuit produces circuit;
Supplied with digital signal DATA and clock signal clk process by BPSK modulation module, produce the digital signal meeting BPSK modulation and require;
Every grade of time delay generative circuit of time delay generation module utilizes the feature of inverter time delay, the modulation signal that BPSK modulation module exports is postponed, obtain different delays to export, producing circuit for controlling corresponding pulse train, making it generate the pulse unit of equal time width;
Every grade of pulse train of pulse train generation module produces circuit and produces a single pulse signal, and all pulse signals are combined into a pulse train and send via antenna as output signal output.
In such scheme, time delay generation module comprises 3 grades of time delay generative circuits, and pulse train generation module comprises 3 grades of pulse trains and produces circuit.
In such scheme, described BPSK modulation module is by 3 nmos pass transistors NM0, NM1, NM2, and 3 PMOS transistor PM0, PM1, PM2 and 2 inverter INV0, INV1 circuit form; After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module; After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module; Clock signal clk input is formed after the drain electrode of nmos pass transistor NM0, the source electrode of PMOS transistor PM0 and the input of inverter INV1 are connected; The output of inverter INV0, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2 are connected with the grid of nmos pass transistor NM2; Output, the drain electrode of nmos pass transistor NM1 of inverter INV1 are connected with the source electrode of PMOS transistor PM1; The source electrode of nmos pass transistor NM2 connects low level; The source electrode of PMOS transistor PM2 connects high level; After the source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM2, form the output of the output signal Q of BPSK modulation module; After the source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 are connected with the drain electrode of PMOS transistor PM2, form the output of the output signal QN of BPSK modulation module.
In such scheme, every grade of time delay generative circuit is made up of 4 inverters INV2, INV3, INV4, INV5; Inverter INV2 and inverter INV3 is serially connected on the output of the output signal Q of BPSK modulation module; The input of inverter INV2, as the Q side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal A of time delay generative circuit at the corresponding levels simultaneously; The output of inverter INV2 is connected with the input of inverter INV3, forms the output of the time delayed signal B of time delay generative circuit at the corresponding levels; The output of inverter INV3, as the Q side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal C of time delay generative circuit at the corresponding levels simultaneously; The Q side input of first order time delay generative circuit is connected with the output of the output signal Q of BPSK modulation module, the Q side input of second level time delay generative circuit is connected with the Q side output of first order time delay generative circuit, and the Q side input of third level time delay generative circuit is connected with the Q side output of second level time delay generative circuit; Inverter INV4 and inverter IN5 is serially connected on the output of output signal QN; The input of inverter INV4, as the QN side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal a of time delay generative circuit at the corresponding levels simultaneously; The output of inverter INV4 is connected with the input of inverter INV5, forms the output of the time delayed signal b of time delay generative circuit at the corresponding levels; The output of inverter INV5, as the QN side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal c of time delay generative circuit at the corresponding levels simultaneously; The QN side input of first order time delay generative circuit is connected with the output of the output signal QN of BPSK modulation module, the QN side input of second level time delay generative circuit is connected with the QN side output of first order time delay generative circuit, and the QN side input of third level time delay generative circuit is connected with the QN side output of second level time delay generative circuit.
In such scheme, every grade of pulse generative circuit is made up of PMOS transistor PM3, PM4, PM5, PM6 and nmos pass transistor NM3, NM4 and NM5, NM6; The grid of PMOS transistor PM4 connects the output of the time delayed signal A of corresponding time delay generative circuit; The source electrode of PMOS transistor PM4 connects the drain electrode of PMOS transistor PM3; The source electrode of PMOS transistor PM3 connects high level; The grid of nmos pass transistor NM3 connects the output of the time delayed signal a of corresponding time delay generative circuit; The source electrode of nmos pass transistor NM3 connects the drain electrode of nmos pass transistor NM4; The source electrode of nmos pass transistor NM4 connects low level; The grid of PMOS transistor PM3 is connected the output of the time delayed signal B of corresponding time delay generative circuit with the grid of nmos pass transistor NM5; The grid of PMOS transistor PM6 is connected the output of the time delayed signal b of corresponding time delay generative circuit with the grid of nmos pass transistor NM4; The source electrode of PMOS transistor PM6 connects the drain electrode of PMOS transistor PM5; The source electrode of PMOS transistor PM5 connects high level; The grid of PMOS transistor PM5 connects the output of the time delayed signal c of corresponding time delay generative circuit; The source electrode of nmos pass transistor NM5 connects the drain electrode of nmos pass transistor NM6; The source electrode of nmos pass transistor NM6 connects low level; The grid of nmos pass transistor NM6 connects the output of the time delayed signal C of corresponding time delay generative circuit; After the drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, the drain electrode of PMOS transistor PM6 are connected with the drain electrode of nmos pass transistor NM5, form the output of the output signal PG_OUT of pulse generative circuit at the corresponding levels.
In such scheme, between described pulse train generation module and antenna, be serially connected with a buffer circuit.
Compared with prior art, the present invention is mainly made up of BPSK modulation module, time delay generation module and pulse train generation module three part.Digital signal and clock signal, through the process of BPSK modulation module, produce the BPSK digital modulation signals of satisfying the demand.The digital modulation signals that BPSK modulation module produces directly delivers to the time delayed signal needed for the generation of time delay generation module of rear class, produces for driving pulse the pulse train that circuit produces required pulse width.The pulse train frequency bandwidth that UWB pulse transmitter of the present invention produces is 3-5GHz, pulse generation circuit control signal is few, avoid the problem easily producing sequential disorder in traditional circuit, and circuit power consumption is low, structure is simple, chip area is little, be conducive to integrated chip, reduce costs, and be conducive to improving IR-UWB transmitter performance.
Accompanying drawing explanation
Fig. 1 is the system construction drawing that the digital BPSK of CMOS of the present invention modulates IR-UWB transmitter.
Fig. 2 is BPSK modulation module structure chart in the present invention.
Fig. 3 (a) be in the present invention BPSK modulation module in the oscillogram of each time delayed signal point of the output side of output signal Q.
Fig. 3 (b) be in the present invention BPSK modulation module in the oscillogram of each time delayed signal point of the output side of output signal QN.
Fig. 4 (a) is the workflow diagram of pulse generative circuit under DATA=1 state in the present invention.
Fig. 4 (b) is the workflow diagram of pulse generative circuit under DATA=0 state in the present invention.
Fig. 5 is inverter structure figure in the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described further:
A kind of CMOS digital BPSK modulating pulse radio ultra-wideband transmitter, as shown in Figure 1, is formed primarily of BPSK modulation module, time delay generation module, pulse train generation module, inverter and antenna.
BPSK modulation module, as shown in Figure 2, by 3 nmos pass transistors NM0, NM1, NM2,3 PMOS transistor PM0, PM1, PM2 and 2 inverter INV0, INV1 circuit compositions.After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module.After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module.Clock signal clk input is formed after the drain electrode of nmos pass transistor NM0, the source electrode of PMOS transistor PM0 and the input of inverter INV1 are connected.The output of inverter INV0, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2 are connected with the grid of nmos pass transistor NM2.Output, the drain electrode of nmos pass transistor NM1 of inverter INV1 are connected with the source electrode of PMOS transistor PM1.The source electrode of nmos pass transistor NM2 connects low level.The source electrode of PMOS transistor PM2 connects high level.After the source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM2, form the output of the output signal Q of BPSK modulation module.After the source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 are connected with the drain electrode of PMOS transistor PM2, form the output of the output signal QN of BPSK modulation module.
The major function of BPSK modulation module is processed supplied with digital signal DATA and clock signal clk, produces the digital signal meeting BPSK modulation and require.Namely when digital signal DATA is high level " 1 ", output signal Q is clock signal clk, controls the pulse train that late-class circuit produces positive; When digital signal DATA is low level " 0 ", output signal QN is negative clock signal "-CLK ", control the pulse train that late-class circuit produces negative.Fig. 3 (a) be in the present invention BPSK modulation module in the oscillogram of each time delayed signal point of the output side of output signal Q.Fig. 3 (b) be in the present invention BPSK modulation module in the oscillogram of each time delayed signal point of the output side of output signal QN.
The course of work of BPSK modulation module is:
When DATA is high level " 1 ", nmos pass transistor NM0 and PMOS transistor PM0, PM2 are in conducting state, and nmos pass transistor NM1, NM2 and PMOS transistor PM1 are in not on-state, so the circuit network that clock signal clk can be composed in parallel by NM0 and PM0, output signal Q equals CLK signal.And output signal QN and drawn high into high level by direct voltage " 1 ".
When DATA is low level " 0 ", nmos pass transistor NM0 and PMOS transistor PM0, PM2 are in not on-state, and nmos pass transistor NM1, NM2 and PMOS transistor PM1 are in conducting state, so output signal QN equals negative clock signal "-CLK ", and outputs signal Q and be communicated to earth signal " 0 ".
Visible, when data digital signal is " 1 ", there is non-inverting clock signal to export, when data digital signal is " 0 ", have negative clock signal to export, meet the requirement of BPSK modulating mode.
Time delay generation module, as shown in Figure 1, is composed in series by three grades of time delay generative circuits.Every grade of time delay generative circuit comprises 4 inverters INV2, INV3, INV4, INV5.Inverter INV2 and inverter INV3 is serially connected on the output of the output signal Q of BPSK modulation module.The input of inverter INV2, as the Q side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal A of time delay generative circuit at the corresponding levels simultaneously.The output of inverter INV2 is connected with the input of inverter INV3, forms the output of the time delayed signal B of time delay generative circuit at the corresponding levels.The output of inverter INV3, as the Q side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal C of time delay generative circuit at the corresponding levels simultaneously.The Q side input of first order time delay generative circuit is connected with the output of the output signal Q of BPSK modulation module, the Q side input of second level time delay generative circuit is connected with the Q side output of first order time delay generative circuit, and the Q side input of third level time delay generative circuit is connected with the Q side output of second level time delay generative circuit.Inverter INV4 and inverter IN5 is serially connected on the output of output signal QN.The input of inverter INV4, as the QN side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal a of time delay generative circuit at the corresponding levels simultaneously.The output of inverter INV4 is connected with the input of inverter INV5, forms the output of the time delayed signal b of time delay generative circuit at the corresponding levels.The output of inverter INV5, as the QN side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal c of time delay generative circuit at the corresponding levels simultaneously.The QN side input of first order time delay generative circuit is connected with the output of the output signal QN of BPSK modulation module, the QN side input of second level time delay generative circuit is connected with the QN side output of first order time delay generative circuit, and the QN side input of third level time delay generative circuit is connected with the QN side output of second level time delay generative circuit.
The major function of time delay generation module is the feature adopting inverter time delay, the modulation signal that BPSK modulation module exports is postponed, obtaining different delays to export, for controlling corresponding pulse generative circuit, making it generate the pulse unit of equal time width.The breadth length ratio of the inside CMOS transistor of inverter is regulated to regulate the anti-phase delay time of inverter.The structure of inverter is identical, and as shown in Figure 5, each inverter forms by PMOS transistor PM7 and nmos pass transistor NM7.After wherein the grid of PMOS transistor PM7 is connected with the grid of nmos pass transistor NM7, form the input of inverter.The source electrode of PMOS transistor PM7 connects high level, and the source electrode of nmos pass transistor NM7 connects low level.After the drain electrode of PMOS transistor PM7 is connected with the drain electrode of nmos pass transistor NM7, form the output of inverter.By the anti-phase delay time regulating the breadth length ratio of transistor PM7 and NM7 in all time delay generative circuits to regulate inverter.
Pulse train generation module, as shown in Figure 1, is composed in series by three grades of pulse generative circuits (PG-cell).Every one-level pulse generative circuit corresponding one-level time delay generative circuit.Each pulse generative circuit, as shown in Fig. 3 (a) He 3 (b), forms by PMOS transistor PM3, PM4, PM5, PM6 and nmos pass transistor NM3, NM4 and NM5, NM6.The grid of PMOS transistor PM4 connects the output of the time delayed signal A of corresponding time delay generative circuit.The source electrode of PMOS transistor PM4 connects the drain electrode of PMOS transistor PM3.The source electrode of PMOS transistor PM3 connects high level.The grid of nmos pass transistor NM3 connects the output of the time delayed signal a of corresponding time delay generative circuit.The source electrode of nmos pass transistor NM3 connects the drain electrode of nmos pass transistor NM4.The source electrode of nmos pass transistor NM4 connects low level.The grid of PMOS transistor PM3 is connected the output of the time delayed signal B of corresponding time delay generative circuit with the grid of nmos pass transistor NM5.The grid of PMOS transistor PM6 is connected the output of the time delayed signal b of corresponding time delay generative circuit with the grid of nmos pass transistor NM4.The source electrode of PMOS transistor PM6 connects the drain electrode of PMOS transistor PM5.The source electrode of PMOS transistor PM5 connects high level.The grid of PMOS transistor PM5 connects the output of the time delayed signal c of corresponding time delay generative circuit.The source electrode of nmos pass transistor NM5 connects the drain electrode of nmos pass transistor NM6.The source electrode of nmos pass transistor NM6 connects low level.The grid of nmos pass transistor NM6 connects the output of the time delayed signal C of corresponding time delay generative circuit.After the drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, the drain electrode of PMOS transistor PM6 are connected with the drain electrode of nmos pass transistor NM5, form the output of the output signal PG_OUT of pulse generative circuit at the corresponding levels.
Every one-level pulse generative circuit corresponding one-level time delay generative circuit of pulse train generation module.Every one-level produces a single pulse signal, and tertiary vein rushes signal combination and becomes a pulse train to send via antenna as output signal.By the amplitude regulating the breadth length ratio of transistor in every grade of pulse generative circuit to regulate formed single pulse signal, three grades of single pulse signals are combined into one and have the pseudo-Gaussian pulse signal of good spectral characteristic.
The course of work of pulse train generation module is:
When DATA is high level " 1 ", output signal Q is CLK signal, and the inverter group of time delay generative circuit obtains different delays, and output signal QN is high level " 1 ", a=" 1 ", b=" 0 ", c=" 1 ".If initial condition is A=" 1 ", B=" 0 ", C=" 1 ".Nmos pass transistor NM3, NM6 and PMOS transistor PM6, PM6 conducting, nmos pass transistor NM4, NM5 and PMOS transistor PM4, PM5 cut-off, output signal PG_OUT is constant voltage values.As shown in 4 (a), the t1 moment, A point signal becomes low level " 0 " from high level " 1 ", and because the reason of anti-phase time delay, now B point signal is still low level " 0 ", when A=B=" 0 ", PMOS transistor PM3 and PM4 all conductings, and nmos pass transistor NM5 is still in cut-off state, so output signal PG_OUT is communicated to high-level DC voltage signal, magnitude of voltage is driven high.In the t2 moment, time of delay crosses end, and B point signal becomes " 1 " from " 0 ", and PMOS transistor PM3 ends, and output signal voltage stops being driven high.When B point signal becomes high level " 1 ", because inverter time delay reason, C point voltage still time high level " 1 ", so nmos pass transistor NM5, NM6 all conductings.Output signal PG_OUT is communicated to signal ground (low level " 0 "), and magnitude of voltage is dragged down.In the t3 moment, after the inverter delay time terminates, C point signal becomes low level " 0 ".Nmos pass transistor NM6 ends, and output signal voltage stops being dragged down.In the change of this time cycle of t1-t3, output signal defines a little positive single pulse signal.And within the continuous print time, three PG-cell will generate the wide zero crossing positive single pulse signal of three groups of equal times.Fig. 4 (a) is the workflow diagram of pulse generative circuit under DATA=1 state in the present invention.
When DATA is high level " 0 ", output signal Q is low level " 0 ", A=" 0 ", B=" 1 ", C=" 0 ".And QN is inverting clock signal "-CLK ".If initial condition is a=" 0 ", b=" 1 ", c=" 0 ".Nmos pass transistor NM4, NM5 and PMOS transistor PM4, PM5 conducting, nmos pass transistor NM3, NM6 and PMOS transistor PM3, PM6 cut-off, output signal PG_OUT is constant voltage values.As shown in 4 (b), the t1 moment, when a point signal becomes high level " 1 " from low level " 0 ", and because the reason of anti-phase time delay, now b point signal is still low level " 1 ", when a=b=" 1 ", nmos pass transistor NM3 and NM4 all conductings, and PMOS transistor PM6 is still in cut-off state, so output signal PG_OUT is communicated to signal ground (low level " 0 "), magnitude of voltage is dragged down.In the t2 moment, time of delay terminates, and b point signal becomes " 0 " from " 1 ", and nmos pass transistor NM4 ends, and output signal voltage stops being dragged down.When b point signal becomes low level " 0 ", because inverter time delay reason, c point voltage still time high level " 0 ", so PMOS transistor PM5, PM6 all conductings.Output signal PG_OUT is communicated to DC high voltage signal " 1 ", and magnitude of voltage is driven high.In the t3 moment, the inverter delay time terminates, and c point signal becomes low level " 1 ".PMOS transistor PM5 ends, and output signal voltage stops being driven high.In the change of this time cycle of t1-t3, output signal defines a little negative single pulse signal.And within the continuous print time, three PG-cell will generate the wide negative single pulse signal of three groups of equal times.Fig. 4 (b) is the workflow diagram of pulse generative circuit under DATA=0 state in the present invention.
In the process that output signal PG_OUT magnitude of voltage is dragged down or draws high, the amplitude of change in voltage determines by the performance of transistor.When a certain link conducting, when changing the breadth length ratio of this active link all crystals pipe simultaneously, the amplitude of the pulse that can regulation output signal be formed.Such as, as transistor PM3 and PM4 conducting, output signal PG_OUT is communicated to high-level DC voltage signal, and magnitude of voltage is driven high.And the breadth length ratio of debugging PM3 and PM4 can the amplitude that is driven high of regulation output signal PG_OUT.This pulse generate network forms circuit by three pulses, and continues all in time, and three pulses are combined to form a complete pulse train, the similar high-order Gaussian pulse of whole pulse train.This high-order Gaussian pulse has good spectral characteristic, is conducive to the transmission of signal of communication.
A buffer circuit is serially connected with between described pulse train generation module and antenna.
Claims (6)
1.CMOS digital BPSK modulating pulse radio ultra-wideband transmitter, is characterized in that: be made up of BPSK modulation module, time delay generation module, pulse train generation module and antenna; Time delay generation module comprises the time delay generative circuit of more than 2 grades and 2 grades, and pulse train generation module comprises the pulse train generation circuit of more than 2 grades and 2 grades, and every grade of corresponding one-level pulse train of time delay generative circuit produces circuit;
Supplied with digital signal DATA and clock signal clk process by BPSK modulation module, produce the digital signal meeting BPSK modulation and require;
Every grade of time delay generative circuit of time delay generation module utilizes the feature of inverter time delay, the modulation signal that BPSK modulation module exports is postponed, obtain different delays to export, producing circuit for controlling corresponding pulse train, making it generate the pulse unit of equal time width;
Every grade of pulse train of pulse train generation module produces circuit and produces a single pulse signal, and all pulse signals are combined into a pulse train and send via antenna as output signal output.
2. CMOS according to claim 1 digital BPSK modulating pulse radio ultra-wideband transmitter, is characterized in that: time delay generation module comprises 3 grades of time delay generative circuits, and pulse train generation module comprises 3 grades of pulse trains and produces circuit.
3. CMOS according to claim 1 and 2 digital BPSK modulating pulse radio ultra-wideband transmitter, it is characterized in that: described BPSK modulation module is by 3 nmos pass transistors NM0, NM1, NM2, and 3 PMOS transistor PM0, PM1, PM2 and 2 inverter INV0, INV1 circuit form; After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module; After the grid of nmos pass transistor NM0, the grid of PMOS transistor PM1 are connected with the input of inverter INV0, form the digital signal DATA input of BPSK modulation module; Clock signal clk input is formed after the drain electrode of nmos pass transistor NM0, the source electrode of PMOS transistor PM0 and the input of inverter INV1 are connected; The output of inverter INV0, the grid of PMOS transistor PM0, the grid of nmos pass transistor NM1, the grid of PMOS transistor PM2 are connected with the grid of nmos pass transistor NM2; Output, the drain electrode of nmos pass transistor NM1 of inverter INV1 are connected with the source electrode of PMOS transistor PM1; The source electrode of nmos pass transistor NM2 connects low level; The source electrode of PMOS transistor PM2 connects high level; After the source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM2, form the output of the output signal Q of BPSK modulation module; After the source electrode of nmos pass transistor NM1, the drain electrode of PMOS transistor PM1 are connected with the drain electrode of PMOS transistor PM2, form the output of the output signal QN of BPSK modulation module.
4. according to the digital BPSK modulating pulse of the CMOS in claims 1 to 3 described in any one radio ultra-wideband transmitter, it is characterized in that: every grade of time delay generative circuit is made up of 4 inverters INV2, INV3, INV4, INV5; Inverter INV2 and inverter INV3 is serially connected on the output of the output signal Q of BPSK modulation module; The input of inverter INV2, as the Q side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal A of time delay generative circuit at the corresponding levels simultaneously; The output of inverter INV2 is connected with the input of inverter INV3, forms the output of the time delayed signal B of time delay generative circuit at the corresponding levels; The output of inverter INV3, as the Q side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal C of time delay generative circuit at the corresponding levels simultaneously; The Q side input of first order time delay generative circuit is connected with the output of the output signal Q of BPSK modulation module, the Q side input of second level time delay generative circuit is connected with the Q side output of first order time delay generative circuit, and the Q side input of third level time delay generative circuit is connected with the Q side output of second level time delay generative circuit; Inverter INV4 and inverter IN5 is serially connected on the output of output signal QN; The input of inverter INV4, as the QN side input of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal a of time delay generative circuit at the corresponding levels simultaneously; The output of inverter INV4 is connected with the input of inverter INV5, forms the output of the time delayed signal b of time delay generative circuit at the corresponding levels; The output of inverter INV5, as the QN side output of time delay generative circuit at the corresponding levels, forms the output of the time delayed signal c of time delay generative circuit at the corresponding levels simultaneously; The QN side input of first order time delay generative circuit is connected with the output of the output signal QN of BPSK modulation module, the QN side input of second level time delay generative circuit is connected with the QN side output of first order time delay generative circuit, and the QN side input of third level time delay generative circuit is connected with the QN side output of second level time delay generative circuit.
5. according to the digital BPSK modulating pulse of the CMOS in claims 1 to 3 described in any one radio ultra-wideband transmitter, it is characterized in that: every grade of pulse generative circuit is made up of PMOS transistor PM3, PM4, PM5, PM6 and nmos pass transistor NM3, NM4 and NM5, NM6; The grid of PMOS transistor PM4 connects the output of the time delayed signal A of corresponding time delay generative circuit; The source electrode of PMOS transistor PM4 connects the drain electrode of PMOS transistor PM3; The source electrode of PMOS transistor PM3 connects high level; The grid of nmos pass transistor NM3 connects the output of the time delayed signal a of corresponding time delay generative circuit; The source electrode of nmos pass transistor NM3 connects the drain electrode of nmos pass transistor NM4; The source electrode of nmos pass transistor NM4 connects low level; The grid of PMOS transistor PM3 is connected the output of the time delayed signal B of corresponding time delay generative circuit with the grid of nmos pass transistor NM5; The grid of PMOS transistor PM6 is connected the output of the time delayed signal b of corresponding time delay generative circuit with the grid of nmos pass transistor NM4; The source electrode of PMOS transistor PM6 connects the drain electrode of PMOS transistor PM5; The source electrode of PMOS transistor PM5 connects high level; The grid of PMOS transistor PM5 connects the output of the time delayed signal c of corresponding time delay generative circuit; The source electrode of nmos pass transistor NM5 connects the drain electrode of nmos pass transistor NM6; The source electrode of nmos pass transistor NM6 connects low level; The grid of nmos pass transistor NM6 connects the output of the time delayed signal C of corresponding time delay generative circuit; After the drain electrode of PMOS transistor PM4, the drain electrode of nmos pass transistor NM3, the drain electrode of PMOS transistor PM6 are connected with the drain electrode of nmos pass transistor NM5, form the output of the output signal PG_OUT of pulse generative circuit at the corresponding levels.
6. CMOS according to claim 1 digital BPSK modulating pulse radio ultra-wideband transmitter, is characterized in that: be serially connected with a buffer circuit between described pulse train generation module and antenna.
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Application publication date: 20151007 Assignee: Nanning Taisu Semiconductor Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2022450000523 Denomination of invention: CMOS all digital BPSK modulated pulse radio ultra wideband transmitter Granted publication date: 20170620 License type: Common License Record date: 20221229 |