CN106373601A - Self-refreshing pulse generator - Google Patents

Self-refreshing pulse generator Download PDF

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CN106373601A
CN106373601A CN 201610909545 CN201610909545A CN106373601A CN 106373601 A CN106373601 A CN 106373601A CN 201610909545 CN201610909545 CN 201610909545 CN 201610909545 A CN201610909545 A CN 201610909545A CN 106373601 A CN106373601 A CN 106373601A
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connected
self
pulse
output
fet
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CN 201610909545
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Chinese (zh)
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昌越彬
蒋明睿
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成都益睿信科技有限公司
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/145Applications of charge pumps ; Boosted voltage circuits ; Clamp circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The invention provides a self-refreshing pulse generator and relates to the technical field of memorizer refreshing circuits. The technical problems that in the prior art, self refreshing fails due to the fact that leak current exists in adjacent word lines of a memorizer, and a pulse generator is poor in stability are solved. The self-refreshing pulse generator mainly comprises a pulse generation unit, a self-refreshing pulse output unit, a feedback counting unit and an output control unit. The pulse generation unit comprises a phase inverter circuit and is used for generating a first pulse clock and a second pulse clock with the relative phase difference and receiving a first reference clock. The self-refreshing pulse output unit receives the first pulse clock and the second pulse clock output by the pulse generation unit. The feedback counting unit receives self-refreshing pulses output by the self-refreshing pulse output unit and counts the self-refreshing pulses. The output control unit receives counting marking pulses output by the feedback counting unit and a second reference clock and outputs control pulses to the self-refreshing pulse output unit. The self-refreshing pulse output unit selectively outputs relative short-period self-refreshing pulses through the control pulses. The self-refreshing pulse generator is used for a self-refreshing memorizer.

Description

一种自刷新的脉冲发生器 A self-refresh pulse generator

技术领域 FIELD

[0001] 本发明涉及存储器刷新电路技术领域,具体涉及一种自刷新的脉冲发生器。 [0001] The present invention relates to a technical field memory refresh circuit, particularly relates to a self-refresh pulse generator. 背景技术 Background technique

[0002] 当存储器字线激活时,相对高电压将出现在存储器相邻字线间,特别是间隔字线发生激活时,中间字线将受到电磁干扰,此时在中间字线的各个晶体管内将产生漏电流。 [0002] When the word line activating the memory, the relatively high voltage will occur between adjacent word lines in a memory, in particular activation occurs when the word line interval, the intermediate word lines to electromagnetic interference, this time in the middle of each of the transistors of the word line the leakage current. 在这种情况下,脉冲发生器输出自刷新脉冲对字线作用,但是由于漏电流存在,则会进一步出现自刷新失败。 In this case, the output from the pulse generator pulse is applied to the word line refresh, but due to the presence of leakage current, will further appear from the refresh failure. 此外,现有技术脉冲发生器的稳定性和频率特性都有待提高。 In addition, stability and frequency characteristics of the prior art pulse generators are to be improved. 发明内容 SUMMARY

[0003] 针对上述现有技术,本发明目的在于提供,解决现有技术存储器相邻字线存在漏电流导致的自刷新失败和脉冲发生器存在稳定性差等技术问题。 [0003] For the above-described prior art, an object of the present invention to provide, to solve prior art memory exists adjacent word lines the leakage current results in poor stability of the self refresh present technical problems and failures pulse generator.

[0004] 为达到上述目的,本发明采用的技术方案如下: [0004] To achieve the above object, the present invention employs the following technical solutions:

[0005] 一种自刷新的脉冲发生器,包括 [0005] A self-refresh pulse generator, comprising

[0006] 脉冲发生单元,包括反相器电路,用于产生具有相对相位差第一脉冲时钟和第二脉冲时钟,接收第一基准时钟; [0006] The pulse generating unit includes an inverter circuit for generating a clock pulse having a relative phase difference of a first and second clock pulses, receiving a first reference clock;

[0007] 自刷新脉冲输出单元,接收由脉冲发生单元输出的第一脉冲时钟和第二脉冲时钟; [0007] The self-refresh pulse output unit, receiving a first clock pulse and a second clock pulse generated by the pulse output unit;

[0008] 反馈计数单元,接收由自刷新脉冲输出单元输出的自刷新脉冲并计数自刷新脉冲; [0008] Feedback counting unit receives the refresh pulses from the refresh and self refresh pulse count from the pulse output unit;

[0009] 输出控制单元,接收由反馈计数单元输出的计数标记脉冲、接收第二基准时钟,并输出控制脉冲至自刷新脉冲输出单元; [0009] The output control unit, indicated by the received feedback counting unit counting an output pulse, receiving a second reference clock, and outputs the self-refresh control pulse to pulse output means;

[0010] 所述的自刷新脉冲输出单元通过控制脉冲选择地输出相对的短周期自刷新脉冲。 [0010] Since the refresh pulse output means outputs said control pulse by selecting a relatively short period of self refresh pulse.

[0011] 上述方案中,还包括, [0011] In the above embodiment, further comprising,

[0012] 脉冲匹配单元,用于调节短周期自刷新脉冲的频率窗口,接收第一基准时钟和第二基准时钟,并输出同步基准时钟至输出控制单元。 [0012] Pulse matching unit for adjusting the frequency of the self-refresh cycle is short window pulse, receiving the first reference clock and the second reference clock, and outputs the reference clock to synchronize the output control unit.

[0013] 上述方案中,所述的脉冲发生单元,包括由电流源电路、反相器电路和缓冲电路构成的振荡器。 [0013] In the above embodiment, the pulse generating unit includes an oscillator circuit consisting of current source, an inverter circuit, and a buffer circuit.

[0014] 上述方案中,所述的脉冲发生单元,还包括过冲保护电路,接收反相器电路的输出时钟,并选择地泄放电流源电路的输入电源。 [0014] In the above embodiment, the pulse generation unit further includes an overshoot protection circuit to receive the output of the clocked inverter circuit, and selectively input power bleeder current source circuit.

[0015] 上述方案中,所述的电流源电路,包括 [0015] In the above embodiment, the current source circuit comprising

[0016] 第一电源; [0016] a first power supply;

[0017] 第一电流源,其高电势端连接第一电源; [0017] The first current source, which is connected to a first high-potential power supply terminal;

[0018] 第一场效应管,其源极连接第一电流源的低电势端; [0018] The first field effect transistor, whose source is electrically connected to the low potential terminal of a first current source;

[0019] 第二场效应管,其源极连接第一电流源的低电势端且漏极接地; [0019] The second FET, a source electrode electrically connected to the low potential end of the first current source and the drain is grounded;

[0020] 第三场效应管,其漏极连接第一场效应管的漏极; [0020] The third FET having a drain connected to the drain of the first FET;

[0021] 第四场效应管,其源极连接第三场效应管的源极; [0021] The fourth FET, the third FET whose source is connected to the source electrode tube;

[0022] 第二电源,连接第四场效应管的漏极;[〇〇23] 第二电流源,其高电势端连接第三场效应管的源极且低电势端接地; [0022] The second power source connected to the drain of the fourth field-effect transistor; [〇〇23] a second current source connected to the high-potential terminal of the source of the third field-effect transistor is grounded and a low potential;

[0024] 第一电容,用于下位电路的充放电电荷缓冲,其一端连接第一电源且另一端连接第一场效应管的漏极。 [0024] a first capacitor, the charge and discharge for the lower buffer circuit, connected to a first power supply having one end and the other end connected to the drain of the first field-effect transistor.

[0025] 上述方案中,所述的反相器电路,用于形成内环振荡,包括 [0025] In the above embodiment, the inverter circuit, for forming the inner oscillation, comprising

[0026] 第五场效应管,其栅极连接第一场效应管的漏极; [0026] The fifth FET, a gate connected to the drain of the first FET;

[0027] 第六场效应管,其栅极连接第一场效应管的漏极且漏极连接第五场效应管的漏极; [0027] The sixth FET having a gate connected to the drain of the first FET and a drain connected to the drain of the fifth field-effect transistor;

[0028] 第七场效应管,其栅极、漏极均连接第六场效应管的源极且源极接地; [0028] The seventh FET, a gate, a drain connected to the sixth FET are a source electrode tube and a source grounded;

[0029] 第八场效应管,用于作为偏置电压开关,其漏极连接第六场效应管的源极且源极接地;[0〇3〇] 第三电源; [0029] The eighth FET, is used as the bias voltage switching, the drain electrode of the sixth FET source tube and the source is grounded; [0〇3〇] third power supply;

[0031] 第九场效应管,其栅极、漏极均连接第五场效应管的源极且源极连接第三电源;[〇〇32] 第十场效应管,用于作为偏置电压开关,其源极连接第三电源且漏极连接第五场效应管的源极;[〇〇33] 第一反相器,其输入端连接第五场效应管的漏极;[〇〇34] 第二反相器、第三反相器和第二电容,依次串联第一反相器,第二电容还连接至第五反馈回路的栅极,构成反相器电路的反馈回路;[〇〇35] 第三电容,用于提供内环振荡回路充电、放电,其一端连接第一场效应管的漏极且另一端接地; [0031] The ninth FET, a gate, a drain of the fifth FET are connected to the source electrode and the source connected to a third power supply; [〇〇32] tenth FET configured as a bias voltage a switch connected to a third power source and the drain connected to the source electrode of the fifth FET; [〇〇33] a first inverter having an input terminal connected to the drain of the fifth field-effect transistor; [〇〇34 ] second inverter, a third inverter and a second capacitor, a first inverter in series, the second capacitor is also connected to the gate of the fifth feedback loop, the feedback loop constituting the inverter circuit; [square 〇35] the third capacitor, for providing inner tank charging, discharging, one end thereof connected to the drain of the first FET and the other end grounded;

[0036] 所述的第十场效应管、第八场效应管,栅极均连接至第三反相器的输出端,用于输出切换; [0036] FET according to the tenth, eighth FET, the gate is connected to the output of the third inverter for outputting switching;

[0037] 所述的第二场效应管、第四场效应管,栅极均连接至第二反相器的输出端,用于充放电切换。 [0037] The second field-effect transistor, a fourth field-effect transistor, a gate is connected to the output terminal of the second inverter, for charging and discharging switching.

[0038] 上述方案中,所述的缓冲电路,用于获得两路延时输出,包括 [0038] In the above embodiment, the buffer circuit for obtaining two delay output, comprising

[0039] 第四反相器,其输入端连接第二反相器的输出端; [0039] The fourth inverter, the output of which is connected to an input terminal of the second inverter;

[0040] 第五反相器、第六反相器,构成锁存器,锁存器串联第四反相器; [0040] The fifth inverter, a sixth inverter constituting a latch, the latch fourth inverter connected in series;

[0041] 第七反相器,其输入端连接锁存器输出端; [0041] The seventh inverter having an input terminal connected to the latch output terminal;

[0042] 第一缓冲器,串联第七反相器,输出第一脉冲时钟; [0042] The first buffer, serially seventh inverter, the output of a first clock pulse;

[0043] 第二缓冲器,串联第四反相器,输出第二脉冲时钟; [0043] The second buffer, a fourth inverter connected in series, the output of the second clock pulse;

[0044] 所述的第一场效应管、第三场效应管,栅极均连接至第四反相器的输出端,用于充放电切换。 [0044] said first FET, the third FET, the gate is connected to the output of the fourth inverter, for charging and discharging switching.

[0045] 上述方案中,所述的过冲保护电路,用于过振荡时电源快速泄放,包括 [0045] The above-described embodiment, the overshoot protection circuit for power through the rapid bleeder oscillation, comprising

[0046] 比较器,其高电端连接有参考电压且低电端连接第五场效应管的栅极; [0046] The comparator whose end is electrically connected to the high and low reference voltage connected to the gate terminal of the fifth field-effect transistor;

[0047] 与非门,其输入端口连接比较器的输出端且接收一使能信号; [0047] NAND gate having an input port connected to the output terminal of the comparator and receives an enable signal;

[0048] 第十一场效应管,其栅极连接与非门的输出端,漏极连接第一场效应管的漏极且源极接地。 [0048] The eleventh FET, the gate is connected to the output terminal of NAND gate, a source and a drain connected to the drain of the first FET is grounded.

[0049] 上述方案中,所述的第三场效应管,其源极还连接有第四电容,第四电容还接地。 [0049] The above-described embodiment, the third FET whose source is also connected to a fourth capacitor, the fourth capacitor is also grounded.

[0050] 上述方案中,所述的自刷新脉冲输出单元,包括片选控制电路; [0050] In the above embodiment, the self-refresh pulse output unit, comprising a chip select control circuit;

[0051] 所述的反馈计数单元,包括降值计数器;[〇〇52] 所述的输出控制单元,包括置位逻辑电路。 Feedback counting unit [0051], comprising a down counter; [〇〇52] said output control unit comprises a logic circuit is set. [〇〇53]与现有技术相比,本发明的有益效果:利用降值计数,通过建立相对短周期触发自刷新反馈时钟环,解决了因漏电流引起的刷新失败,实现了存储器自刷新补偿;提高了其脉冲发生器的稳定性。 [〇〇53] Compared with the prior art, the beneficial effects of the present invention are: the use of a down counter, the self refresh clock feedback loop, to solve the refresh failure due to leakage current caused by the establishment of a relatively short period trigger to achieve a self refresh memory compensation; improving the stability of the pulse generator. 附图说明 BRIEF DESCRIPTION

[0054] 图1为本发明的模块示意图; [0054] FIG. 1 is a schematic view of the module of the present invention;

[0055] 图2为本发明脉冲发生器的具体电路原理图;[〇〇56]图3为本发明输出控制单元的原理示意图;[〇〇57]图4为本发明自刷新脉冲输出单元;[〇〇58]图5为本发明电容C3和电容C2的电压变化示意图; DETAILED circuit diagram [0055] FIG 2 is a pulse generator of the present invention; [〇〇56] FIG. 3 is a schematic view of the output of the principles of the invention the control unit; [〇〇57] FIG. 4 of the present invention the self refresh pulse output means; [〇〇58] FIG 5 the voltage change of the capacitor C2 and the capacitor C3 a schematic diagram of the present invention;

[0059] 图6为本发明反相器U18和电容C3的电压变化示意图; [0059] FIG. 6 is a schematic of the inverter U18 and the voltage variation of the capacitor C3 of the present invention;

[0060] 图7为本发明电位点A、B、C和D处电压幅值变化示意图; [0060] The potential at the point A in FIG. 7 of the present invention, a schematic view of B, C and D of the voltage amplitude variation;

[0061] 图8为本发明下拉场效应Q7的漏源极电压变化示意图;[〇〇62]图9为本发明下拉场效应Q7连接电容C4后的漏源极电压变化示意图。 [0061] Figure 8 a schematic view of the pull-down change in drain-source voltage of the FET Q7 of the present invention; [〇〇62] FIG. 9 is a schematic view of the invention changes the drain-source voltage of the capacitor C4 is connected to the pull-down FET Q7. 具体实施方式[〇〇63] 本说明书中公开的所有特征,或公开的所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以以任何方式组合。 DETAILED DESCRIPTION All of the features disclosed in the present specification, or all of the method steps [〇〇63] or process disclosed, except the mutually exclusive features and / or steps, can be combined in any manner. [〇〇64]下面结合附图对本发明做进一步说明: [〇〇64] DRAWINGS The present invention is further described:

[0065] 实施例1 [0065] Example 1

[0066] 在图2中,结合图5、图6和图7电压变化,场效应管Q8、Q12等效为二极管,场效应管Q9、Q13作为反馈控制的偏置电压开关,场效应管Q10、Q11构成由场效应管Q9、Q13控制的等效反相器,反相器电路的输出时钟波形为电位点C处时钟波形,电流源电路的输入电源包括电流源11和电流源12;第一基准时钟SCLK可以在电位点A处输入,也可以在场效应管Q5栅极处输入,电路初始条件设置为电位点A为接地电压,场效应管Q5、Q10、Q9处于导通状态,电流源II对电容C1充电,当电容C1电压升到足以使得场效应管Q10截止,等效反相器发生偏转, 电位点D电压从电压VCC变为接地电压,场效应管Q9截止且场效应管Q13导通,场效应管Q4导通,电流源II被泄放,电流源12对电容C1进行放电,直到场效应管Q10再次被导通,不断重复这一过程,进而输出振荡方波。 [0066] In FIG. 2, in conjunction with FIGS. 5, 6 and 7 voltage changes, FET Q8, Q12 is equivalent to a diode, FET Q9, Q13 as a bias voltage feedback control switch, FET Q10 , composed of the FET Q11 Q9, Q13 equivalent inverter control, the output clock waveform inverter circuit the potential at the point C clock waveform, the input supply current source circuit includes a current source 11 and a current source 12; first a reference clock SCLK may be input potential at the point a may be provided at the input FET, the gate circuit initial conditions at the point a potential of transistor Q5 is the ground voltage, the FET Q5, Q10, Q9 in the oN state, current sources II charging the capacitor C1, the capacitor C1 when the voltage rises enough so that the FET Q10 is turned off, the inverter equivalent deflected, the potential of the point D from the voltage VCC becomes the ground voltage, the field effect transistor Q9 is turned off and the FET Q13 turned on, the FET Q4 is turned on, a current source II is vented, the current source 12 discharges the capacitor C1 until the FET Q10 is turned on again, the process is repeated, whereby the output square wave oscillation. 由于脉冲发生器中使用电容和电流源,考虑实际使用器件的完美程度,充放电可能存在重叠的窗口,导致回路中可能有较高的尖峰电压值,并且极可能发生在电位点C处,所以设置比较器进行检测,用于及时对尖峰电压放电,还可以进一步设置与非门逻辑电路,使用处理芯片的使能信号进行驱动。 Since the pulse generator and the current source capacitance, considering the degree of perfection of the actual device, the charge and discharge windows may overlap, resulting in the circuit may have a higher peak voltage value, and highly likely to occur at the potential of the point C, so the comparator is provided to detect a voltage spike timely discharge may be further provided with a NAND logic circuit, the signal processing chip enable use to be driven. [〇〇67]图3,所述的输出控制单元,包括由反相器U1、反相器U2构成的延时器,用于实现相对相位差,延时器接收同步基准时钟MCLK和第二基准时钟BCLK,输出延时后的同步基准时钟和第二基准时钟至场效应管Q1,场效应管Q2直接接收计数标记脉冲FCLK和第二基准时钟BCLK,场效应管Q1、Q2共同选择输出,6个反相器1]3、1]4、1]5、1]7、1]8和1]9串联并构成锁存器,锁存器输入端接收场效应管Q1、Q2的输出,再通过反相器U6输出控制脉冲ICLK。 [〇〇67] FIG. 3, the output control unit including an inverter U1, U2 constituted of the inverter delay for effecting a relative phase difference, delays the received reference clock MCLK, and a second synchronous the BCLK reference clock, the reference clock synchronized output of the delay and the second reference clock to the FET Q1, FET Q2 directly received pulse count indicia and a second reference clock FCLK the BCLK, the FET Q1, Q2 jointly select the output, 6 inverters 1] 3,1] 4,1] 5,1] 7,1] and 1 8] 9 connected in series and constitute a latch, a latch input for receiving FET Q1, Q2 is output, through the inverter U6 output control pulse ICLK. [〇〇68]图4,所述的自刷新脉冲输出单元,包括与非门U10,接收第一脉冲时钟PCLK1和控制脉冲ICLK;反相器U14接收控制脉冲ICLK;与非门U11,连接反相器输出端并接收第二脉冲时钟PCLK2;与非门U12,连接与非门U10、U11的输出端;与门U13,连接与非门U12的输出端; 场效应管Q3,通过使能信号ENBAR控制导通或截止;与非门U12和使能信号ENBAR共同决定相对短周期或正常的自刷新脉冲PCLK。 [〇〇68] FIG 4, the self-refresh pulse output unit includes a NAND gate U10, receives the first clock pulse and a control pulse PCLK1 ICLK; inverter U14 receives a control pulse ICLK; NAND gate U11, ligation reaction phase output terminal and receiving a second clock pulse PCLK2; NAND gate U12, is connected to the NAND gate U10, U11, the output terminal; aND gate U13, connected to the output of NAND gate U12; MOSFET Q3, by an enable signal ENBAR control turned on or off; NAND gate U12 and the enable signal ENBAR together determine a relatively short period or normal self refresh pulse PCLK.

[0069] 图8和图9,图8中可以明显看出,由于不同电容充放电过程,造成回路电压出现短促峰值,如果在现实应用中,叠加电源的波动,甚至可以将部分场效应管反向击穿,造成回路短路,从而损害器件。 [0069] Figures 8 and 9, in Figure 8 it is clear that due to the different charging and discharging the capacitor, resulting in short circuit voltage peak occurs, if the real-world applications, power fluctuations superimposed, even partially FET trans the breakdown, causing a short-circuit loop, to the detriment of the device. 图9为增加安全电容C4后的场效应管Q7的漏源极电压变化波形,使得充放电过程更加平滑,没有短时畸变脉冲峰。 9 is a change to increase the drain-source voltage waveform security FET Q7 of the capacitor C4, so that the charge-discharge process smoother, no peak short pulse distortion.

[0070] 以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何属于本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。 [0070] The above are only specific embodiments of the present invention, but the scope of the present invention is not limited to this, belong to any person skilled in the art within the technical scope of the present invention is disclosed, variations may readily occur to or alternatively, shall fall within the protection scope of the present invention.

Claims (10)

  1. 1.一种自刷新的脉冲发生器,其特征在于,包括脉冲发生单元,包括反相器电路,用于产生具有相对相位差第一脉冲时钟和第二脉冲时钟,接收第一基准时钟;自刷新脉冲输出单元,接收由脉冲发生单元输出的第一脉冲时钟和第二脉冲时钟; 反馈计数单元,接收由自刷新脉冲输出单元输出的自刷新脉冲并计数自刷新脉冲; 输出控制单元,接收由反馈计数单元输出的计数标记脉冲、接收第二基准时钟,并输出控制脉冲至自刷新脉冲输出单元;所述的自刷新脉冲输出单元通过控制脉冲选择地输出相对的短周期自刷新脉冲。 A self-refresh pulse generator, characterized by comprising a pulse generating unit includes an inverter circuit for generating a clock pulse having a relative phase difference of a first and second clock pulses, receiving a first reference clock; from refresh pulse output unit that receives the first clock pulse and a second clock pulse generated by the pulse output unit; feedback counting unit receives the refresh pulse from the output unit and the self refresh pulse counting a self refresh pulse; output control unit receives the feedback counting unit counting the output pulses marker, receiving a second reference clock, and outputs the self-refresh control pulse to pulse output means; self-refresh by said pulse output means for selectively controlling a pulse output from a relatively short period of refresh pulses.
  2. 2.根据权利要求1所述的一种自刷新的脉冲发生器,其特征在于,还包括,脉冲匹配单元,用于调节短周期自刷新脉冲的频率窗口和同步第一基准时钟,接收第一基准时钟和第二基准时钟,并输出同步基准时钟至输出控制单元。 1 2. The one of the self-refresh pulse generator of claim 3, wherein, further comprising, a pulse matching unit for adjusting the self-refresh pulse short period of frequency bins a first reference clock and synchronization, the first receiving a second reference clock and a reference clock, and outputs the reference clock to synchronize the output control unit.
  3. 3.根据权利要求1所述的一种自刷新的脉冲发生器,其特征在于,所述的脉冲发生单元,包括由电流源电路、反相器电路和缓冲电路构成的振荡器。 According to claim 1, wherein one of the self-refresh pulse generator, wherein said pulse generating means includes an oscillator circuit consisting of current source, an inverter circuit, and a buffer circuit.
  4. 4.根据权利要求3所述的一种自刷新的脉冲发生器,其特征在于,所述的脉冲发生单元,还包括过冲保护电路,接收反相器电路的输出时钟,并选择地泄放电流源电路的输入电源。 According to claim 3, wherein one of the self-refresh pulse generator, wherein said pulse generation unit further comprises an overshoot protection circuit, the inverter circuit receives the output clock, and optionally a bleed input supply current source circuit.
  5. 5.根据权利要求3所述的一种自刷新的脉冲发生器,其特征在于,所述的电流源电路, 包括第一电源;第一电流源II,其高电势端连接第一电源;第一场效应管Q5,其源极连接第一电流源11的低电势端;第二场效应管Q4,其源极连接第一电流源II的低电势端且漏极接地;第三场效应管Q7,其漏极连接第一场效应管Q5的漏极;第四场效应管Q6,其源极连接第三场效应管Q7的源极;第二电源,连接第四场效应管Q6的漏极;第二电流源12,其高电势端连接第三场效应管Q7的源极且低电势端接地;第一电容C2,用于下位电路的充放电电荷缓冲,其一端连接第一电源且另一端连接第一场效应管Q5的漏极。 3, according to one of the self-refresh pulse generator of claim 3, wherein said current source circuit comprising a first power source; a first current source II, which end is connected to a first high-potential power source; the first a field effect transistor Q5, a source electrode connected to the low potential terminal of the first current source 11; a second MOSFET Q4, its source connected to a first current source II low-potential terminal and the drain is grounded; third FET Q7, a drain connected to a first drain of the transistor Q5; Q6 fourth FET, the third FET whose source is connected to the source electrode of transistor Q7; a second power supply, connected to the drain of the fourth field-effect transistor Q6 is electrode; 12, its high-potential terminal of the second current source connected to the source of the third field-effect transistor Q7 and the source to a low potential terminal; a first capacitor C2, the charge and discharge for the lower buffer circuit, a first power supply and having one end connected and the other end connected to the drain of the first field-effect transistor Q5.
  6. 6.根据权利要求5所述的一种自刷新的脉冲发生器,其特征在于,所述的反相器电路, 用于形成内环振荡和自反馈电压切换输出,包括第五场效应管Q10,其栅极连接第一场效应管Q5的漏极;第六场效应管Q11,其栅极连接第一场效应管Q5的漏极且漏极连接第五场效应管Q10的漏极;第七场效应管Q12,其栅极、漏极均连接第六场效应管Ql 1的源极且源极接地;第八场效应管Q13,用于作为偏置电压开关,其漏极连接第六场效应管Q11的源极且源极接地;第三电源;第九场效应管Q8,其栅极、漏极均连接第五场效应管Q10的源极且源极连接第三电源; 第十场效应管Q9,用于作为偏置电压开关,其源极连接第三电源且漏极连接第五场效应管Q10的源极;第一反相器U15,其输入端连接第五场效应管Q10的漏极;第二反相器U16、第三反相器U17和第二电容C3,依次串联第一反相器U15,第二电 6. According to one 5 of the self-refresh pulse generator of claim 3, wherein said inverter circuit, for forming an inner ring and an oscillation output from the feedback voltage switch, comprising a fifth FET Q10 a gate connected to a first drain of the transistor Q5; sixth FET Q11, a gate connected to the drain of the first FET and the drain of the transistor Q5 is connected to the drain of the fifth FET Q10; first seven FET Q12, a gate, the drain of the sixth FET Ql are connected to the source electrode 1 and the source is grounded; eighth FET Q13, it is used as a bias voltage switch, a drain connected to the sixth source of the transistor Q11 is grounded and the source electrode; a third power supply; ninth FET Q8, a gate, a drain are connected to the source of the fifth FET Q10 and the source electrode connected to a third power supply; X FET Q9, as the bias voltage for the switch, which is connected to a third power source and the drain connected to the source electrode of the fifth FET Q10; a first inverter U15, an input terminal connected to the fifth FET Q10 drain; a second inverter U16, U17 a third inverter and a second capacitor C3, in series a first inverter U15, the second electrical C3 还连接至第五反馈回路Q10的栅极,构成反相器电路的反馈回路;第三电容C1,用于提供内环振荡回路充电、放电,其一端连接第一场效应管Q5的漏极且另一端接地;所述的第十场效应管Q9、第八场效应管Q13,栅极均连接至第三反相器U17的输出端,用于输出切换;所述的第二场效应管Q4、第四场效应管Q6,栅极均连接至第二反相器U16的输出端,用于充放电切换。 C3 is also connected to the gate of the fifth Q10 of the feedback loop, the feedback loop constituting the inverter circuit; a third capacitor C1, the resonant circuit for providing an inner charging, discharging, one end thereof connected to the drain of the first FET Q5 and the other end is grounded; said tenth FET Q9, eighth FET Q13, the gate is connected to the output of the third inverter U17 for output switching; said second FET Q4, Q6 are fourth FET, the gate is connected to the output of the second inverter U16 for charging and discharging switching.
  7. 7.根据权利要求6所述的一种自刷新的脉冲发生器,其特征在于,所述的缓冲电路,用于获得两路延时输出,包括第四反相器U18,其输入端连接第二反相器U16的输出端;第五反相器U23、第六反相器U24,构成锁存器,锁存器串联第四反相器U18;第七反相器U21,其输入端连接锁存器输出端;第一缓冲器U20,串联第七反相器U21,输出第一脉冲时钟;第二缓冲器U19,串联第四反相器U18,输出第二脉冲时钟;所述的第一场效应管Q5、第三场效应管Q7,栅极均连接至第四反相器U18的输出端,用于充放电切换。 According to one of the claims from 6 to refresh pulse generator, wherein said buffer circuit for obtaining two output delay, including U18, the fourth inverter having an input connected to the first two of the output of the inverter U16; U23 fifth inverter, a sixth inverter U24, constituting latch, latch U18 series fourth inverter; seventh inverter U21, whose input is connected latch output terminal; a first buffer U20, series seventh inverter U21, the output of a first clock pulse; second buffer U19, the series fourth inverter U18, the output of the second clock pulse; said first a field effect transistor Q5, a third field-effect transistor Q7, a gate is connected to the output terminal of the fourth inverter U18 for charging and discharging switching.
  8. 8.根据权利要求6所述的一种自刷新的脉冲发生器,其特征在于,所述的过冲保护电路,用于过振荡时电源快速泄放,包括比较器U22,其高电端连接有参考电压且低电端连接第五场效应管Q10的栅极;与非门U25,其输入端口连接比较器U22的输出端且接收一使能信号;第i^一场效应管Q14,其栅极连接与非门U25的输出端,漏极连接第一场效应管Q5的漏极且源极接地。 6, according to one of the self-refresh pulse generator of claim 3, wherein the overshoot protection circuit for power oscillation quickly bleed through, a comparator U22, which end is electrically connected to a high with the reference voltage and a low electrical terminals connected to the gate of the fifth FET Q10; NAND gate U25, the input port connected to an output terminal of the comparator U22 and receives an enable signal; i ^ first field effect transistor Q14, which an output terminal connected to the gate of the NAND gate U25, the drain connected to the drain of the first field-effect transistor Q5 is grounded and the source.
  9. 9.根据权利要求5所述的一种自刷新的脉冲发生器,其特征在于,所述的第三场效应管Q7,其源极还连接有第四电容C4,第四电容C4还接地。 9. A member according to claim 5 wherein the self-refresh pulse generator, characterized in that said third field-effect transistor Q7, whose source is also connected to a fourth capacitor C4, is also the fourth capacitor C4 is grounded.
  10. 10.根据权利要求1-9中任意一项权利要求所述的一种自刷新的脉冲发生器,其特征在于,所述的自刷新脉冲输出单元,包括片选控制电路;所述的反馈计数单元,包括降值计数器;所述的输出控制单元,包括置位逻辑电路。 Claim 10. A self refresh pulse generator as claimed in any one of the claims 1-9, characterized in that said self refresh pulse output unit including a chip select control circuit; said feedback counter means, including a down counter; said output control unit comprises a logic circuit is set.
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EP0473421B1 (en) * 1990-08-30 1997-10-29 Nec Corporation Semiconductor memory device
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CN103066953A (en) * 2012-12-27 2013-04-24 上海集成电路研发中心有限公司 Continuous pulse generator
CN103093806A (en) * 2011-11-04 2013-05-08 海力士半导体有限公司 Self Refresh Pulse Generation Circuit
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Publication number Priority date Publication date Assignee Title
EP0473421B1 (en) * 1990-08-30 1997-10-29 Nec Corporation Semiconductor memory device
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