A kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width
Technical field
The present invention relates to ultra broadband (UWB:Ultra-wideband) technical field, particularly a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width.
Background technology
According to FCC (FCC) definition, super bandwidth signal is meant in-10dB place bandwidth greater than 500MHz or relative bandwidth greater than 20%, and centre frequency is greater than the signal of 500MHz.Ultra-broadband signal shows as the pulse of fast rise and decline on time domain, the duration of pulse is extremely short, have only the hundreds of psec usually to several nanoseconds, so signal bandwidth is very big, can reach several GHz.Super-broadband tech is applied to radar, wireless communication field, can significantly improve radar resolution and wireless communication rate, has lower system power dissipation simultaneously, becomes the focus of current research.
The generation of ultra-narrow pulse is the key of super-broadband tech.The performance of ultra-narrow pulse generation circuit is relevant with employed high speed device, at present commonly used have devices such as tunnel diode, step recovery diode, avalanche diode, wherein, the pulse that tunnel diode and step recovery diode produced, rise time can reach tens to the hundreds of psec, but its amplitude is little.And the pulse that avalanche transistor produces, the rise time can reach 1~2ns, and output pulse amplitude can reach tens volts, but needs higher supply voltage, is unfavorable for integrated application.For addressing the above problem, notification number is that this generator of the Chinese invention patent specification of CN1202618C disclosed a kind of " the ultra broadband narrow-band impulse generator of subnanosecond duration " produces the square-wave signal input by base band sources, behind differentiator, base stage zero offset amplifier, filter, by the wideband low noise amplifier super narrow bandwidth pulse of output subnanosecond duration.This generator is based on Analogical Circuit Technique, the core is the RC differential circuit, can produce ultra-narrow pulse in theory, but in Project Realization, very high to square wave rising, fall time and level shake requirement that power supply stability, base band sources produce, and the time selection of constant of RC circuit will be very difficult.
Summary of the invention
Technical problem to be solved by this invention provides a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width that a kind of circuit is simple, be easy to integrated realization.
A kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width that the present invention is designed, comprise the digital source module, level conversion and clock distribution module, postpone control module, the pulse generation module, the differential circuit module, low noise broadband power amplification module is in series successively, the clock signal of TTL (transistor-transistor logic level) level of the some cycles that produces by the digital source module, change and be distributed into the clock signal of 3 road ECL (RF-coupled logic) level by level conversion and clock distribution module, postponing control module, to regulate the delay of clock signal of 3 road ECL level poor, signal is sent into the pulse generation module after through different the delay and is produced a ultra-narrow pulse, and ultra-narrow pulse is exported ultra-wideband impulse signal after by differential circuit module and low noise broadband power amplification module.
Improvement as such scheme, postponing serial connection edge sorting module between control module and the pulse generation module, rising edge of clock signal and trailing edge that the edge sorting module will postpone the ECL level of control module output improve, reduce to rise and fall time, can effectively improve the amplitude of the ultra-narrow pulse of output.
In the such scheme, described level conversion and clock distribution module comprise 1 level translator and 3 clock distributors, the clock signal of the Transistor-Transistor Logic level of input exports 3 clock distributors to be converted to the clock signal of a pair of mutually non-ECL level by level translator after simultaneously, clock distributor is exported the clock signal of 3 road ECL level respectively, wherein the clock signal of first via ECL level is identical with the phase place of the clock signal of the second road ECL level, and the clock signal of Third Road ECL level is opposite with the clock signal phase of the clock signal of first via ECL level and the second road ECL level.
In the such scheme, described delay control module comprises the delayer of 2 delay inequalities greater than the transmission delay of pulse generation module, the clock signal of the clock signal of first via ECL level and the second road ECL level is respectively by two delayer outputs, and the clock signal of Third Road ECL level is straight-through to be exported.
The delay inequality of described 2 delayers is fixed, the width of the final ultra-narrow pulse that produces is by the delay difference decision of the clock signal of first and second road ECL level, therefore be adjustable for making the width of the ultra-narrow pulse that is produced, described delayer is preferably the adjustable programmable delay line of time-delay.
In the such scheme, described pulse generation module is 2 High Speed ECL AND circuit, the clock signal of the clock signal of the second road ECL level and Third Road ECL level inserts the input of one-level ECL AND circuit respectively, the clock signal of the output of one-level ECL AND circuit and first via ECL level is connected to an input of secondary ECL AND circuit respectively, and secondary ECL AND circuit is output as the output of pulse generation module.
Design concept of the present invention is to utilize High Speed ECL gate device and programmable delay device to produce super bandwidth pulses.The TTL digital dock pulse of the some cycles that digital source produces becomes the ECL level by level translator with the digital dock level conversion, utilizes two programmable delay control lags poor.Signal is sent into pulse generator after postponing through difference, because time-delay is different, the signal that enters pulse generator just has the regular hour poor, pulse generator can produce a ultra-narrow pulse, the molded breadth of this pulse equated with the time difference of two-way inhibit signal, ultra-narrow pulse just can obtain the super bandwidth pulses of certain power by the low noise wideband power amplifer.
The present invention compared with prior art adopts the ECL digital device to produce the ultra-narrow pulse signal, and lower to the stability requirement on the power supply of circuit and ground, also lower to the required precision of element, strong interference immunity is easy to realize.The ECL circuit working is less in unsaturated state, logic swing, and the transmission delay of circuit only is the hundreds of ps order of magnitude even tens ps, so the burst pulse pulsewidth that the present invention produced is extremely narrow.In addition, circuit of the present invention is simple, be easy to realize that at different application scenarios, the delay that can adjust delayer is poor, changes the pulse duration of ultra broadband ultra-narrow pulse, thereby changes the frequency spectrum of ultra broadband ultra-narrow pulse.
Description of drawings
Fig. 1 is the theory diagram of a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width of the present invention;
Fig. 2 is the realization circuit diagram of a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width of the present invention;
Number in the figure is: 1 is the digital source module, and 2 is level conversion and clock distribution module, and 3 for postponing the controlling models piece, and 4 is the edge sorting module, and 5 are the pulse generation module, and 6 is the differential circuit module, and 7 is low noise broadband power amplification module;
The time domain measurement waveform of a kind of ultra-narrow pulse that Fig. 3 the present invention is produced;
The frequency domain measurement waveform of a kind of ultra-narrow pulse that Fig. 4 the present invention is produced;
A kind of ultra-narrow pulse that Fig. 5 the present invention is produced is through the time domain measurement waveform after the antenna transmission.
Embodiment
The theory diagram of a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width of the present invention as shown in Figure 1, this device mainly by digital source module 1, level conversion and clock distribution module 2, postpone control module 3, edge sorting module 4, pulse generation module 5, differential circuit module 6,7 seven parts of low noise broadband power amplification module and form.During work, the dagital clock signal of the Transistor-Transistor Logic level of the duty ratio 50% of digital source module 1 generation frequency 5~25MHz.The clock signal of Transistor-Transistor Logic level is changed and is distributed into the clock signal of three road ECL level by level conversion and clock distribution module 2, the clock signal of first via ECL level is identical with the clock signal phase of the second road ECL level, and is opposite with the clock signal phase of Third Road ECL level.By postponing two programmable delay lines of control module 3, the Third Road clock signal passes straight through to pulse generation module 5 to the clock signal of the clock signal of first via ECL level and the second road ECL level respectively then.By the programming control lag, the delay of clock signal that makes the clock signal of first and second road ECL level and Third Road ECL level is greater than the transmission delay of pulse generation module 5, and the delay between the clock signal of the clock signal of first via ECL level and the second road ECL level is a picosecond.The delay difference of the clock signal of first and second road of most preferred embodiment of the present invention ECL level and the clock signal of Third Road ECL level can guarantee to guarantee that greater than 3 nanoseconds the Third Road clock signal has become the logical zero level before the trailing edge of first and second road clock signal arrives.So, only can produce extremely narrowly at first via rising edge clock signal constantly in the output with door, trailing edge constantly disturbing pulse can not occur.The delay inequality of first and second road clock signal equals the width of the ultra-narrow pulse that produces in theory.The clock signal of three road ECL level is carried out the edge arrangement through edge sorting module 4 again, improves its rising edge and trailing edge, makes its rise time and fall time less than 1ns.Clock signal through three road ECL level of edge arrangement enters pulse generation module 5.Pulse generation module 5 is High Speed ECL and gate device, and such three road ECL level clock signals enter at a high speed carries out and logical operation with gate device, can produce with the clock signal of first and second road ECL level and delay the identical Gaussian pulse of difference.Gaussian pulse carries out differential through differential circuit again, becomes the single order Gaussian pulse, and again through a low noise wideband power amplifer, output just can obtain the ultra broadband ultra-narrow pulse that is used to launch.
The realization circuit diagram of the most preferred embodiment of a kind of apparatus for generating digital ultra-wideband pulse with adjustable pulse width of the present invention as shown in Figure 2, digital source module 1 is made of an active crystal oscillator, frequency 10MHz, output Transistor-Transistor Logic level, high level 5V, the square-wave signal of low level 0V.The output of digital source module 1 connects the input of level translator M1, indirect pull down resistor R1.The level translator M1 of level conversion and clock distribution module 2 is converted to the clock signal of the Transistor-Transistor Logic level of input the clock signal output of a pair of non-ECL level mutually.The clock signal output of this ECL level meets three clock distributor clk_div1, clk_div2 and clk_div3 again, export the clock signal of three road ECL level respectively, the clock signal of first via ECL level is identical and opposite with the clock signal phase of Third Road ECL level with the clock signal phase of the second road ECL level.The clock signal of three tunnel ECL level connects 1.3V voltage by pull-up resistor R3, R4, R5, R6, R7, R8 respectively.Output with clk_div1 and clk_div2 inserts programmable delay line delay1 and delay2 respectively again, by programming, can regulate the output delay of delay1 and delay2.The output of delay1 and delay2 connects connecting resistance R9, R10, R11, R12 respectively, and then the output of the output of delay2 and clk_div3 connect and a door and1, wherein the anti-phase access of the output of clk_div3 and1 realizes and logical operation that the output of and1 connects draws resistance R 13, R14.The output of delay1 and and1 meets two high-speed comparator cmp1 and cmp2 respectively, and the clock signal of ECL level is carried out the edge arrangement, shortens its rising edge and trailing edge.The output of cmp1 and cmp2 connects draws resistance R 15, R16, R17, R18, the output of cmp1 and cmp2 to connect and a door and2, by with logical operation, and2 is output as Gaussian pulse, its width equals the delay inequality of delay1 and delay2 output.The positive output of and2 connects draws resistance R 19, connects capacitor C 1 again, through the differential of C1, generates the single order Gaussian pulse.C1 output meets wide-band amplifier A1, realize the one-level power amplification, A1 need connect by inductance L 1, L2, the gating matching network that capacitor C 2, C3, C5, C6, C7 and resistance R 20 constitute, the output of A1 connects capacitor C 4 then, C4 meets wide-band amplifier A2, realizes that secondary power amplifies, and A2 need connect by inductance L 3, L4, the coupling gating network that capacitor C 8, C9, C10 constitute, the output of A2 connects capacitor C 11 then, and the output of C11 connects antenna, just the ultra broadband ultra-narrow pulse that is produced can be radiate.Each rising edge of digital source all can produce a ultra-narrow pulse, and the delay of regulating programmable delay line delay1 and delay2 is poor, can change the width of ultra-narrow pulse, thus the frequency spectrum of corresponding adjusting ultra-narrow pulse.
Through oscilloscope actual measurement, the time domain measured waveform that is produced a ultra-narrow pulse by the apparatus for generating digital ultra-wideband pulse with adjustable pulse width of most preferred embodiment of the present invention as shown in Figure 3, wherein the half range pulsewidth is 400ps, the P-to-P voltage value is 3.3V.The spectrum waveform of the ultra-narrow pulse of above-mentioned generation as shown in Figure 4, its-the 10db bandwidth from 150M to 1.5G, meet FCC and define about ultra-broadband signal.The ultra-narrow pulse of above-mentioned generation is after transmission antennas transmit, and the waveform that is received by reception antenna as shown in Figure 5.This shows that the ultra-narrow pulse that apparatus for generating digital ultra-wideband pulse with adjustable pulse width produced of the present invention's design is satisfactory.