CN115021720B

CN115021720B - Width-adjustable high-speed pulse generator circuit and high-speed pulse generation method

Info

Publication number: CN115021720B
Application number: CN202210522960.9A
Authority: CN
Inventors: 盖伟新; 盛凯
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2024-04-30
Anticipated expiration: 2042-05-13
Also published as: CN115021720A

Abstract

The invention relates to a high-speed pulse generator circuit with adjustable width and a high-speed pulse generation method. The width-adjustable high-speed pulse generator circuit comprises transistors M1-M9, wherein the transistors M1, M4 and M6 are PMOS, and the transistors M2, M3, M5, M7, M8 and M9 are NMOS; the branch consisting of M8 and M9 is used as a unit, and n units are connected in parallel; when the input data din=1, no pulse is generated, and the output node POUT remains at 0 all the time; when the input data din=0, a positive pulse is generated in a time when CK0 and CK90 are at the high level. The pulse width of the high-speed pulse generator circuit with adjustable width can be controlled by programming an off-chip control word, so that different speeds can be adjusted to an optimal state; the invention does not introduce extra power consumption, and realizes a pulse generating circuit with low power consumption and high speed.

Description

Width-adjustable high-speed pulse generator circuit and high-speed pulse generation method

Technical Field

The invention belongs to the technical field of integrated circuits, relates to a high-speed serial communication circuit, and in particular relates to a high-speed pulse generator circuit with adjustable width and a high-speed pulse generation method.

Background

The transmitter data path is made up of a pattern Generator (Pattern Generator), a 32:4serializer (32:4 serializer), a shift register (SHIFT REGISTER), a Retimer (Retimer), a Pulse Generator (Pulse Generator), and a Driver (Driver), as shown in fig. 1.

The code pattern generator generates 64 paths of parallel data, the 64 paths of parallel data are divided into two paths of 32-bit data, the two paths enter an MSB (MSB) data path and an LSB (LSB) data path respectively, the MSB path and the LSB path have the same circuit structure, and the sizes of drivers of the last stage are different; in the MSB path, the 32-path parallel data is firstly converted into 4-path parallel data by a 32:4 serializer, each data width is 4 UI (the UI represents the period of the output signal of the transmitter), no relative delay exists among the 4 paths of data, and the data are stored by a shift register; in the retimer, 4-way data are relocated according to four-phase clocks (CK 0, CK90, CK180, CK 270), and adjacent data are separated by a delay of 1 UI; the pulse generator receives four paths of data, generates clock pulse signals with the width of 1UI by using adjacent two-phase clocks, selects the data and generates corresponding data pulse signals; the generated data pulse signals control the grid electrode of a driving circuit (driver), four paths of the driving circuit are parallel, four paths of data pulse signals take effect alternately, corresponding data are driven to an output node, final 4:1 data serialization is completed in a driving stage, the driving stage adopts a current type structure, impedance matching is completed through a 50 ohm resistor, and bandwidth expansion is achieved through an inductor.

In the implementation process of 4:1 data serialization, as shown in fig. 2, the widths of four paths of data (D0 to D3) transmitted from the front-stage circuit are all 4UI, which is 4: four paths of inputs of the serializer are input, each path of data is connected with a pulse generator and a driving circuit (driver), the output of the pulse generator is P0-P3, and the output of the four paths of driving circuits are connected in parallel to form an output node of the whole transmitter; generating four 1UI wide narrow pulses by the four-phase clocks through overlapping relation, wherein each pulse corresponds to one path of data, and in the effective pulse time of the 1UI wide pulse, the corresponding path of data is gated, and the data is transmitted to an output node; the four paths work alternately and sequentially transfer data to the output nodes to form high-speed serial output.

To achieve high-speed low-jitter 4:1 serialization, a high-performance pulse generator is required. The existing pulser design is shown in figure 3. In the scheme (a) of fig. 3, firstly, a clock signal CK90 and a data signal DI are subjected to a combinational logic operation, the operation result is then operated with CK0, and the and logic of three inputs CK0, CK90 and DI is realized through a two-stage logic circuit, so that an output pulse is generated, and the scheme has the advantages of strong driving capability and limited speed of the two-stage logic circuit; the scheme (b) of fig. 3 connects three input signals in series on one path, so that jitter is reduced, but three transistors are connected in series, so that the turnover speed is too low, the driving capability is poor, and the scheme is not suitable for ultra-high speed design; the scheme (c) of fig. 3 implements and logic by means of a transmission gate with a clock signal and a data signal, thereby reducing jitter, but the transmission gate has a poor driving capability, and also has a problem of limited speed.

Disclosure of Invention

In view of the problems in the prior art, an object of the present invention is to provide a high-speed pulse generator circuit and a high-speed pulse generation method, which generate pulses with adjustable width, so that a pulse signal higher than the process speed limit is generated under the condition that the transistor speed is limited.

The technical scheme adopted by the invention is as follows:

The high-speed pulse generator circuit with adjustable width comprises transistors M1-M9, wherein the transistors M1, M4 and M6 are PMOS, and the transistors M2, M3, M5, M7, M8 and M9 are NMOS; the source electrode of M1 is connected with a power supply, the grid electrode is connected with a clock signal CK0, and the drain electrode is connected with a node 1; the source electrode of M2 is connected with the drain electrode of M3, the grid electrode is connected with the clock signal CK0, and the drain electrode is connected with the node 1; the source electrode of M3 is connected with ground, and the grid electrode is connected with a clock signal CK 90; the source electrode of M4 is connected with a power supply, the grid electrode is connected with input data DIN, and the drain electrode is connected with the source electrode of M6; the source electrode of M5 is connected with the ground, the grid electrode is connected with input data DIN, and the drain electrode is connected with the source electrode of M6; the grid electrode of M6 is connected with the node 1, and the drain electrode is connected with the output signal POUT; the source electrode of M7 is connected with the ground, the grid electrode is connected with the node 1, and the drain electrode is connected with the output signal POUT; the source electrode of M8 is connected with the drain electrode of M9, the grid electrode is connected with a control signal SEL, and the drain electrode is connected with the node 1; the source electrode of M9 is connected with the ground, and the grid electrode is connected with the clock signal CK 0; the branch circuit formed by M8 and M9 is used as a unit, and n units are connected in parallel.

Further, among the n units, the gates of M8 are respectively connected with n-bit control signals SEL [1:n ], the values of SEL [1:n ] are mutually independent, and the gates of all M9 are connected with CK 0.

Further, the width of the output pulse signal is adjusted through the control signal SEL [1:n ].

In the high-speed pulse generation method adopting the high-speed pulse generator circuit with adjustable width, when input data DIN=1, no pulse is generated, and the output node POUT is always kept at 0; when the input data din=0, a positive pulse is generated in a time when CK0 and CK90 are at the high level; where CK0 and CK90 are two-phase quadrature clock signals, CK0 leading CK90 by one quarter of a cycle.

Further, when the input data din=0, the gate signal of M6 is 1; when CK0 and CK90 are both 0, a new pulse generation period is started, and the voltage of the output node POUT is 0; when CK0 rises to 1, the voltage of other nodes is unchanged, and the output node POUT is kept to be 0; when CK90 rises to 1, CK0 and CK90 are both 1, M2 and M3 are conducted, node 1 is pulled down to 0 level, M6 is conducted, and output node POUT is charged to 1; when CK0 falls to 0, M1 is turned on, node 1 is charged to 1, so that M6 is turned off, M7 is turned on, and the output node is discharged to 0; CK90 falls to 0 and output node POUT remains at 0, ending the cycle.

Further, when the input data din=1, the gate signal of M6 is 0, and the output node POUT is always 0 throughout the pulse generation period.

Further, the portion SEL [1:n ] is changed from 0 to 1, and the node 1 obtains a discharging branch, so that in the stages of ck0=1 and ck90=0, the node 1 descends in advance, and the charging time of the output node POUT also advances, so that the width of the output pulse signal is equivalently adjusted.

A transmitter comprising a pattern generator, a 32:4 serializer, a shift register, a retimer, a pulse generator comprising the width adjustable high speed pulse generator circuit of the present invention, and a driver.

The invention has the following advantages:

1) The pulse width can be controlled through off-chip control word programming, so that different rates can be adjusted to an optimal state;

2) And no extra power consumption is introduced, so that a pulse generating circuit with low power consumption and high speed is realized.

Drawings

Fig. 1 is a circuit diagram of a transmitter data path.

FIG. 2 shows a circuit structure and sequential logic for 4:1 data serialization, where (a) is the circuit structure and (b) is the sequential logic.

Fig. 3 shows three conventional pulse generators, wherein (a) is a pulse generator based on a two-stage logic circuit, (b) is a pulse generator based on a one-stage logic circuit, and (c) is a pulse generator based on a transmission gate circuit.

Fig. 4 is a circuit configuration diagram of the pulse generator of the present invention.

Fig. 5 is a timing diagram of the operation of the pulse generator of the present invention.

Detailed Description

The structure and operation of the present invention will be described in detail with reference to fig. 4 and 5.

The circuit structure of the pulse generator of the present invention is shown in fig. 4. Transistors M1, M4 and M6 are PMOS, and transistors M2, M3, M5, M7, M8 and M9 are NMOS; the source electrode of M1 is connected with a power supply, the grid electrode is connected with a clock signal CK0, and the drain electrode is connected with a node 1; the source electrode of M2 is connected with the drain electrode of M3, the grid electrode is connected with the clock signal CK0, and the drain electrode is connected with the node 1; the source electrode of M3 is connected with the ground, the grid electrode is connected with the clock signal CK90, and the drain electrode is connected with the source electrode of M2; the source electrode of M4 is connected with a power supply, the grid electrode is connected with input data DIN, and the drain electrode is connected with the source electrode of M6; the source electrode of M5 is connected with the ground, the grid electrode is connected with input data DIN, and the drain electrode is connected with the source electrode of M6; the source electrode of M6 is connected with the drain electrodes of M4 and M5, the grid electrode is connected with the node 1, and the drain electrode is connected with the output signal POUT; the source electrode of M7 is connected with the ground, the grid electrode is connected with the node 1, and the drain electrode is connected with the output signal POUT; the source electrode of M8 is connected with the drain electrode of M9, the grid electrode is connected with a control signal SEL, and the drain electrode is connected with the node 1; the source of M9 is connected to ground, the gate is connected to clock signal CK0, and the drain is connected to the source of M8. The branch circuit formed by M8 and M9 is used as a unit, n units are connected in parallel, M8 and M9 are signs of transistors in one unit, among the n units, the grid electrode of M8 is respectively connected with n-bit control signals of SEL [1:n ], the values of SEL [1:n ] are mutually independent, and the grid electrodes of all M9 are connected with CK 0. Where n may be 1, i.e. at least one unit.

The timing diagram of the operation of the pulse generator is shown in FIG. 5, where CK0 and CK90 are two-phase quadrature clock signals, CK0 leading CK90 by one quarter of a cycle. When the input data din=1, the pulse generator does not generate a pulse, and the output node POUT is always kept at 0; when the input data din=0, the pulse generator generates a positive pulse in a time when CK0 and CK90 are at the high level as shown in fig. 5.

The specific working process is described as follows:

(1) If din=0, the gate signal of M6 is 1; when CK0 and CK90 are both 0, a new pulse generation period is started, and the voltage of the output node POUT is 0; when CK0 rises to 1, the voltage of other nodes is unchanged, and the output node POUT is kept to be 0; when CK90 rises to 1, CK0 and CK90 are both 1, M2 and M3 are conducted, node 1 is pulled down to 0 level, M6 is conducted, and output node POUT is charged to 1; when CK0 falls to 0, M1 is turned on, node 1 is charged to 1, so that M6 is turned off, M7 is turned on, and the output node is discharged to 0; CK90 drops to 0, the output node POUT remains 0, and the cycle ends;

(2) If din=1, the gate signal of M6 is 0; in this case, the output node POUT is always 0 throughout the pulse generation period;

(3) The control signal SEL [1:n ] is used to change the pulse width, and the dashed line signal in fig. 5 indicates that all SEL [1:n ] are 0, and the low level time of the node 1 is short because the charge and discharge speed of the transistors is limited, so that the POUT cannot be fully charged to 1, and an invalid pulse is output; by changing the portion SEL [1:n ] from 0 to 1, the node 1 obtains a discharging branch, so that in the stages of ck0=1 and ck90=0, the node 1 descends in advance, and the charging time of the output node POUT is also advanced, equivalently, the width of the output pulse signal is adjusted; by selecting the appropriate SEL [1:n ] signals, a pulse signal with a full voltage swing and a width of exactly 1UI can be obtained, as shown by the solid line signal in FIG. 5.

The scheme utilizes the advanced decline of the internal node 1 of the logic circuit to lead the rising edge of the output node to be advanced, thereby generating the pulse signal meeting the requirements and breaking through the limit of the charging speed of the process. In addition, the scheme discharges the charge of the node 1 in two stages, and the introduced pull-down transistors M8 and M9 can increase the speed of the pulse generator without consuming additional power consumption.

Another embodiment of the present invention provides a transmitter, as shown in fig. 1, comprising a pattern generator, a 32:4 serializer, a shift register, a retimer, a pulse generator, and a driver, wherein the pulse generator is implemented using the adjustable width high speed pulse generator circuit of the present invention.

The above-disclosed embodiments of the present invention are intended to aid in understanding the contents of the present invention and to enable the same to be carried into practice, and it will be understood by those of ordinary skill in the art that various alternatives, variations and modifications are possible without departing from the spirit and scope of the invention. The invention should not be limited to what has been disclosed in the examples of the specification, but rather by the scope of the invention as defined in the claims.

Claims

1. The high-speed pulse generator circuit with the adjustable width is characterized by comprising transistors M1-M9, wherein the transistors M1, M4 and M6 are PMOS, and the transistors M2, M3, M5, M7, M8 and M9 are NMOS; the source of the transistor M1 is connected with a power supply, the gate of the transistor M1 is connected with a clock signal CK0, and the drain of the transistor M1 is connected with a node 1; the source of the transistor M2 is connected with the drain of the transistor M3, the gate of the transistor M2 is connected with the clock signal CK0, and the drain of the transistor M2 is connected with the node 1; the source of the transistor M3 is connected to ground, and the gate of the transistor M3 is connected to the clock signal CK 90; the source of the transistor M4 is connected with a power supply, the gate of the transistor M4 is connected with input data DIN, and the drain of the transistor M4 is connected with the source of the transistor M6; the source of the transistor M5 is connected to ground, the gate of the transistor M5 is connected to the input data DIN, and the drain of the transistor M5 is connected to the source of the transistor M6; the grid electrode of the transistor M6 is connected with the node 1, and the drain electrode of the transistor M6 is connected with the output signal POUT; the source of the transistor M7 is connected with the ground, the grid of the transistor M7 is connected with the node 1, and the drain of the transistor M7 is connected with the output signal POUT; the source of the transistor M8 is connected to the drain of the transistor M9, the gate of the transistor M8 is connected to the control signal SEL, and the drain of the transistor M8 is connected to the node 1; the source of the transistor M9 is connected to ground, and the gate of the transistor M9 is connected to the clock signal CK 0; the branch circuit formed by the transistor M8 and the transistor M9 is taken as a unit, and n units are connected in parallel; in the n units, the gates of the transistors M8 are respectively connected with n-bit control signals SEL [1:n ], the values of the SEL [1:n ] are mutually independent, and the gates of all the transistors M9 are connected with a clock signal CK 0; and regulating the width of the output pulse signal through the control signal SEL [1:n ].

2. A high-speed pulse generating method using the high-speed pulse generator circuit with adjustable width as claimed in claim 1, characterized in that no pulse is generated when the input data din=1, and the output node POUT is always kept at 0; when the input data din=0, a positive pulse is generated in a time when the clock signal CK0 and the clock signal CK90 are at the high level; where CK0 and CK90 are two-phase quadrature clock signals, clock signal CK0 leads clock signal CK90 by one quarter of a cycle.

3. The high-speed pulse generating method according to claim 2, wherein when the input data din=0, the gate signal of the transistor M6 is 1; when the clock signal CK0 and the clock signal CK90 are both 0, a new pulse generation period is started, and the output node POUT voltage is 0; when the clock signal CK0 rises to 1, the voltage of other nodes is unchanged, and the output node POUT is kept to be 0; when the clock signal CK90 rises to 1, the clock signal CK0 and the clock signal CK90 are both 1, the transistors M2 and M3 are turned on, the node 1 is pulled down to 0 level, the transistor M6 is turned on, and the output node POUT is charged to 1; when the clock signal CK0 falls to 0, the transistor M1 is turned on, the node 1 is charged to 1, so that the transistor M6 is turned off, the transistor M7 is turned on, and the output node is discharged to 0; the clock signal CK90 falls to 0, the output node POUT remains at 0, and the cycle ends.

4. The method of claim 2, wherein when the input data din=1, the gate signal of the transistor M6 is 0, and the output node POUT is always 0 during the entire pulse generation period.

5. The high-speed pulse generating method according to claim 2, wherein the portion SEL [1:n ] is changed from 0 to 1, and the node 1 obtains a discharging branch, so that the node 1 drops in advance at the stage of the clock signal ck0=1 and the clock signal ck90=0, and the charging time of the output node POUT is also advanced, thereby equivalently adjusting the width of the output pulse signal.

6. A transmitter comprising a pattern generator, a 32:4 serializer, a shift register, a retimer, a pulse generator and a driver, wherein the pulse generator comprises the width-adjustable high-speed pulse generator circuit of claim 1.