JP2000101418A - Semiconductor integrated logic circuit and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in a sleep mode by providing a sleep mode control circuit for individually making 1st and 2nd transistors(TR) which supply low-potential and high-potential electric power respectively to 1st and 2nd CMOS logic circuits with power source cutoff functions connected side by side between 1st and 2nd inverter circuits in an active mode and the sleep mode, respectively. SOLUTION: A semiconductor integrated logic circuit 101 comprises 1st and 2nd inverter circuits INV9 and INV12, 1st and 2nd CMOS logic circuits MTC1 and MTC2 with power source cutoff functions and a sleep mode control circuit SMC, which controls the operation of the CMOS logic circuits MTC1 and MTC2. The CMOS logic circuits MTC1 and MTC2 are set as principal circuits comprising CMOS logic circuit groups LGC4 and LGC5 and low-potential and high-potential electric powers VCC and VDD are supplied respectively through n-MOS and p-MOS transistors TS4 and TS5, in which the opening and closing are controlled by a sleep mode control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated logic circuit and a control method thereof, and more particularly, to a semiconductor integrated logic circuit having an active mode for speeding up and a sleep mode for low power consumption. It relates to the control method.

[0002]

2. Description of the Related Art Conventionally, in order to achieve both high speed in an active mode and low power consumption in a sleep mode, a semiconductor integrated logic circuit having a power supply circuit with a power cutoff function has been proposed. Used.

[0003] For example, Japanese Patent No. 2631335 (Japanese Patent Application Laid-Open No. 6-29834) provides a circuit construction method capable of reducing power consumption. According to this method, the semiconductor integrated logic circuit is constituted by low threshold transistors. Thus, even under a low power supply voltage, in the active mode, the semiconductor integrated logic circuit operates at high speed, and by supplying power through the high threshold transistor, the high threshold transistor is cut off in the sleep mode, Cut off the power supply, and
Sub-threshold leakage current can also be cut off to reduce power consumption.

Japanese Patent Application Laid-Open No. 05-210976 discloses a CMO which is a component in a semiconductor integrated logic circuit.
A circuit construction method is described in which power is supplied via a switch element having device parameters such that only a leakage current smaller than the sum of sub-threshold currents leaking from an S logic circuit group flows.

FIG. 10 shows a system diagram of a conventional semiconductor integrated logic circuit 100 provided with a power control circuit.

The semiconductor integrated logic circuit 100 includes an inverter circuit IN composed of CMOS transistors having device parameters with a small sub-threshold leakage current.
CMO composed of V1, INV4 and INV5, and inverter circuits INV2 and INV3 which are composed of CMOS transistors having a low threshold value and operate at high speed.
With the S logic circuit group LGC1 as a main circuit, one high-potential-side power supply VDD is directly supplied with the actual high-potential-side trajectory RVD1 (hereinafter referred to as “real power supply line RVD1”) as a power supply line, and The low-potential-side power supply VSS is connected to the pseudo low-potential side via an n-MOS transistor TS1 for a control switch connected in series to an actual low-potential-side trajectory RVS1 (hereinafter, referred to as an “actual power supply line RVS1”). (Hereinafter referred to as "pseudo power supply line RVSV1") as a power supply line, similarly, an inverter circuit INV6 comprising CMOS transistors having a low threshold value and operating at high speed. CMO composed of INV7
The S logic circuit group LGC2 is a main circuit, one low-potential-side power supply VSS is directly supplied as an actual low-potential-side trajectory RVS1, and the other high-potential-side power supply VDD is an actual high-potential-side trajectory. A pseudo high-potential-side trajectory RVDV1 (hereinafter referred to as a “pseudo power supply line RVD”) is connected via a control switch p-MOS transistor TS2 connected in series to the line RVD1.
V1) as a power supply line. Similarly, a main circuit includes a CMOS logic circuit group LGC3 composed of an inverter circuit INV8 which is composed of a CMOS transistor having a low threshold value and operates at high speed. As a result, one high-potential-side power supply VDD is connected to the actual high-potential-side
D1 is directly supplied as a power distribution line, and the other low-potential-side power supply VSS is connected to the actual low-potential-side trajectory RVS1 in series with a control switch n-MOS transistor TS3.
Through the pseudo low potential side trajectory RVSV2 (hereinafter,
"Pseudo power supply line RVSV2") is supplied as a power distribution line.

Further, the above-mentioned n-MOS for the control switch is used.
The type transistor TS1 has a sleep mode switching inversion signal S
Opening / closing is controlled in response to LB1. Similarly, the control switch p-MOS transistor TS2 outputs the sleep mode switching signal SL1 to the control switch nM
Open / close of the OS type transistor TS3 is controlled in response to the sleep mode switching inversion signal SLB2.

Here, the device parameters of the control switch n-MOS type transistor TS1 correspond to the CMOS logic circuit group LG which is a component of the semiconductor integrated logic circuit 100.
The sum of the sub-threshold currents leaking from the control switch n-MOS transistor TS1 is set to be smaller than the sum of the sub-threshold currents leaking from C1.

Similarly, the device parameter of the control switch p-MOS transistor TS2 is larger than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC2.
The sum of the sub-threshold currents leaking from S2 is set to be smaller.

The device parameter of the control switch n-MOS transistor TS3 is also smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC3.
3 is set so that the sum of the sub-threshold currents leaking from the sub-threshold 3 becomes smaller.

Therefore, in the active mode, that is, the high potential sleep mode switching inversion signal SLB1
When (SLB1 = "1") is applied, the control switch n-MOS transistor TS1 is in a conductive state, and the low-potential-side power supply V is supplied to the CMOS logic circuit group LGC1.
SS can be supplied.

On the other hand, in the sleep mode, that is, the sleep mode switching inversion signal SLB1 (S
LB1 = “0”), the control switch n-MOS transistor TS1 is in the cut-off state, and the low-potential-side power supply VS to the CMOS logic circuit group LGC1 is applied.
S is also cut off, the subthreshold leakage current can be suppressed, and power consumption in the sleep mode can be reduced.

Similarly, in the active mode, that is, the sleep mode switching signal SL1 (SL
1 = “0”), the control switch p-MOS transistor TS2 is in a conductive state,
The high-potential-side power supply VDD can be supplied to the CMOS logic circuit group LGC2.

On the other hand, in the sleep mode, that is, a sleep mode switching signal SL1 (SL1 =
When "1") is applied, the control switch p-MOS transistor TS2 is in a cut-off state, the high-potential power supply VDD to the CMOS logic circuit group LGC2 is also cut off, and the sub-threshold leakage current is suppressed. .

In the active mode, that is, the sleep mode switching inversion signal SLB2 having a high potential
When (SLB2 = “1”) is applied, the control switch n-MOS transistor TS3 is in a conductive state, and the low-potential-side power supply V is supplied to the CMOS logic circuit group LGC3.
SS can be supplied.

On the other hand, in the sleep mode, that is, the sleep mode switching inversion signal SLB2 (S
LB2 = “0”), the control switch n-MOS transistor TS3 is in a cutoff state, and the low potential side power supply VS to the CMOS logic circuit group LGC3 is applied.
S is also cut off, and the subthreshold leakage current can be suppressed.

The inverter circuits INV1, INV4
And INV5 are composed of CMOS transistors having device parameters with a small sub-threshold leakage current as described above.
Even when power is directly supplied from both the power supply DD and the low-potential-side power supply VSS using the actual high-potential-side trajectory RVD1 and the actual low-potential-side trajectory RVS1 as power distribution lines. , No sub-threshold leakage current flows.

However, as described in Japanese Unexamined Patent Application Publication No. 10-0665517, a CMOS transistor having a device parameter with a small sub-threshold leakage current is inevitably slow in operation speed as a trade-off.

[0019]

However, even in the above-described conventional semiconductor integrated logic circuit 100, there is a leakage current that cannot be cut off in the sleep mode. There is a problem that cannot be achieved.

Hereinafter, the background will be described.

In order to respond to the trend of higher speed and higher integration, so-called device parameters such as transistor dimensions of transistors mounted on semiconductor integrated logic circuits have been miniaturized according to a certain proportional reduction rule. As the proportional reduction law, a proportional reduction law with a constant electric field, a proportional reduction law with a constant voltage, and a proportional reduction law with a constant quasi-electric field have been proposed. It is assumed that the same reduction ratio as thickness is applied.

For example, as described in Japanese Patent Application No. 09-313985, when manufacturing a CMOS transistor having a gate length of 0.1 μm according to the proportional reduction rule, the thickness of the gate insulating film is set to 2 It is necessary to reduce the thickness to about 2.5 nm. However, by first reducing the thickness of the gate insulating film by 2 to 2.5 nm, the problem of a tunnel current leaking directly through the gate insulating film starts to appear.

Referring now to FIG. 10, in the above-described semiconductor integrated logic circuit 100, not only in the active mode but also in the sleep mode, the tunnel current leaking directly through the gate insulating film is reduced. The fact that there is a problem that the power cannot be cut off and therefore the power consumption in the sleep mode cannot be reduced will be described.

First, as a first problem example, the first leakage path PS1 of the gate tunnel current shown in FIG. 10 will be described.

This gate-tunnel through current is generated by the p-MOS transistor 10, which is a component of the next-stage inverter circuit INV2, when "1" is applied as an input signal to the inverter circuit INV1.

As described above, the inverter circuits INV1,
INV4 and INV5, n-MOS type transistor TS
1 and TS3, and p-MOS transistor TS
2 is composed of a CMOS transistor having a device parameter having not only a small subthreshold leakage current but also a small gate / tunnel leakage current. However, as described above, a CMOS transistor having a device parameter with a small gate / tunnel leakage current has a trade-off, and the operation speed is slow.

When "1" is applied as an input signal, the output signal of the inverter circuit INV1 is "0", that is, the potential of the lower potential power supply VSS appears. A high-potential-side power supply VDD and a low-potential-side power supply VSS are provided on the gate insulating film between the gate electrode and the source electrode of the MOS transistor 10;
And an electric field corresponding to the potential difference between.

Due to the electric field strength, the first leakage path P
S1 is formed. Along the first leakage path PS1, a tunnel current leaks directly from the source electrode to the gate electrode of the p-MOS transistor 10, and the drain of the n-MOS transistor 20, which is a component of the inverter circuit INV1, Through current flows through the source.

It should be noted here that the gate tunnel current flowing through the leakage path PS1 does not depend at all on the open / close state of the control switch n-MOS transistor TS1, that is, whether it is in the active mode or the sleep mode. Even if it is set to, it keeps leaking. Next, as a second problem example, the second leakage path PS2 of the gate tunnel current shown in FIG.
Will be described.

When the CMOS logic circuit group LGC1 is in the sleep mode, the control switch n-MOS
The low potential signal of the sleep mode switching inversion signal SLB1 is applied to the gate electrode of the type transistor TS1, the control switch n-MOS type transistor TS1 is in the cutoff state, and the sub-threshold current leaking from the CMOS logic circuit group LGC1 For the control switch than the sum of
Since the device parameters of the control switch n-MOS transistor TS1 are set such that the sum of the sub-threshold currents leaking from the MOS transistor TS1 is smaller, the CMOS logic circuit group LGC
N-MOS for control switch than total impedance of 1
Since the impedance of the type transistor TS1 is larger, the potential of the pseudo power supply line RVSV1 is higher than the potential of the higher potential power supply VDD.
By this time, the battery has been charged to a high potential.

Therefore, the output signal of the inverter circuit INV3 exhibits "1". Further, the inverter circuit INV
4, "0" is applied as an input signal to the inverter circuit INV5, and a leakage current is generated by the n-MOS transistor 30, which is a component of the next-stage inverter circuit INV6.

The output signal of the inverter circuit INV5 to which "0" is applied as an input signal is "1", that is,
Since the potential of the high potential power supply VDD appears, the gate insulating film between the gate electrode and the source electrode of the n-MOS transistor 30 which is a component of the inverter circuit INV6 has the high potential power supply VDD and the low potential. An electric field corresponding to a potential difference from the side power supply VSS is applied.

The second leakage path PS2 is formed by the intensity of the electric field. The second leakage path PS2 allows the p-MO, which is a component of the inverter circuit INV5, to be formed.
Via the drain and source of the S-type transistor 40, the n-MO
The tunnel current leaks directly from the gate electrode to the source electrode of the S-type transistor 30, and a through current flows.

It should be noted here that the gate tunnel current flowing through the second leakage path PS2 is controlled by the control switch p-MOS transistor TS2.
Irrespective of the open / closed state of the device, i.e., regardless of whether it is set in the active mode or the sleep mode, the leakage continues.

Next, as a third problem example, a third leakage path PS3 of the gate tunnel current shown in FIG. 10 will be described.

When the CMOS logic circuit group LGC2 is in the sleep mode, the control switch p-MOS
Since the high potential signal of the sleep mode switching signal SL1 is applied to the gate electrode of the type transistor TS2, the control switch p-MOS type transistor TS2 is in the cutoff state. Further, the control switch p-MOS transistor TS2 is configured such that the sum of the sub-threshold currents leaking from the control switch p-MOS transistor TS2 is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC2. Are set, the CMOS logic circuit group L
P-M for control switch than total impedance of GC2
The impedance of the OS type transistor TS2 is larger, and the potential of the pseudo power supply line RVDV1 is lower than the lower potential power supply VSS.
By this time, the battery has been discharged to a low potential.

For this reason, the output signal of the inverter circuit INV7 exhibits "0", and the p-MOS transistor 50, which is a component of the next-stage inverter circuit INV8,
Leakage current occurs.

Since "0", that is, the potential of the low-potential-side power supply VSS appears as the output signal of the inverter circuit INV7, p-
An electric field corresponding to a potential difference between the high-potential-side power supply VDD and the low-potential-side power supply VSS is applied to the gate insulating film between the gate electrode and the source electrode of the MOS transistor 50.

Due to the electric field strength, the third leakage path P
S3 is formed. Through this third leakage path PS3, a tunnel current leaks directly from the source electrode to the gate electrode of p-MOS transistor 50, and the drain and source of n-MOS transistor 60, which is a component of inverter circuit INV7, Will flow through the device.

It should be noted here that the gate tunnel current flowing through the third leakage path PS3 does not depend on the open / close state of the control switch n-MOS transistor TS3 at all, that is, the active state. Whatever the mode or the sleep mode is set, leakage continues.

Next, as a fourth problem example, the leakage path PS4 of the gate tunnel current shown in FIG. 10 will be described.

When the CMOS logic circuit group LGC1 is in the sleep mode, the control switch n-MOS
Since the low potential signal of the sleep mode switching inversion signal SLB1 is applied to the gate electrode of the type transistor TS1, the control switch n-MOS type transistor TS1 is in the cutoff state. Further, the control switch n-MOS transistor TS1 is configured such that the sum of the sub-threshold currents leaking from the control switch n-MOS transistor TS1 is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC1. Is set, the impedance of the control switch n-MOS transistor TS1 is larger than the total impedance of the CMOS logic circuit group LGC1. Therefore, the potential of the pseudo power supply line RVSV1 is charged up to the high potential side power supply VDD, and is in a state of exhibiting a high potential.

However, according to the third leakage path PS3 described above, since the leakage current flows through the drain and the source of the n-MOS transistor 60 constituting the inverter circuit INV7, the pseudo power supply line RVDV1 is at a low potential. It does not fall to the low potential of the power supply VSS.

A similar phenomenon occurs when the CMOS logic circuit group L
When it occurs at GC1, the output signal of the inverter circuit INV3 may exhibit an intermediate potential between the high-potential power supply VDD and the low-potential power supply VSS. Therefore, the n-MOS transistor 70 and the p-MOS transistor 80 constituting the next-stage inverter circuit INV4 are both in a weakly conducting state, and as shown by the leakage path PS4, the high-potential power supply VDD and the low-potential power supply The through current to VSS will leak.

The present invention has been made in view of such a problem in the conventional semiconductor integrated logic circuit. In the sleep mode, not only the sub-threshold current but also the gate tunnel current and thus the over-current generated in the secondary mode. It is an object of the present invention to provide a semiconductor integrated logic circuit capable of blocking all leakage current of the semiconductor integrated logic circuit in a sleep mode by also blocking a wrap through current and reducing power consumption in a sleep mode. And

[0046]

To achieve the above object, according to the present invention, there is provided a first and a second inverter circuit comprising CMOS transistors having device parameters with a small sub-threshold leakage current;
A first CMOS logic circuit group including a CMOS transistor having a low threshold value and performing a high-speed operation; a high-potential-side power supply is directly supplied; a low-potential-side power supply is supplied via the first transistor; A first with a power cutoff function connected in parallel between the first and second inverter circuits;
And a CMOS transistor having a low threshold value, and a second CMOS logic circuit group that performs high-speed operation. The low-potential-side power supply is directly supplied, and the high-potential-side power supply is a second transistor. And a second CMOS logic circuit with a power cutoff function, which is supplied in parallel with the first and second inverter circuits and is connected between the first and second inverter circuits, and independently switches the first and second transistors to the active mode. And a sleep mode control circuit that can be in a sleep mode.

For example, as described in claims 2 and 3, an n-MOS transistor can be used as the first transistor, and a p-MOS transistor can be used as the second transistor.

As set forth in claim 4, the device parameter of the first transistor is the first CMOS.
The sum of the sub-threshold currents leaking from the first transistor is set to be smaller than the sum of the sub-threshold currents leaking from the logic circuit group,
The device parameter of the second transistor is the second C
It is preferable that the sum of the sub-threshold currents leaking from the second transistor be smaller than the sum of the sub-threshold currents leaking from the MOS logic circuit group.

In the semiconductor integrated logic circuit described above, a signal arranged between each of the first and second inverter circuits and the first and second CMOS logic circuits is provided. It is preferable to further include a transmission circuit.

According to a sixth aspect of the present invention, the signal transmission circuit includes a combination of a line dividing circuit for controlling transmission and interruption of a signal and a signal fixing circuit for controlling fixing and release of a signal. Yes, it is preferably controlled by a sleep mode control circuit.

According to a seventh aspect of the present invention, there is provided a first CMOS logic circuit group comprising a CMOS transistor having a low threshold value and performing a high-speed operation. The first supplied through the transistor
And a CMOS transistor having a low threshold value, and a second CMOS logic circuit group that performs high-speed operation. The low-potential-side power supply is directly supplied, and the high-potential-side power supply is a second transistor. And a third CMOS logic circuit group comprising a CMOS transistor having a low threshold value and operating at high speed, and a high-potential-side power supply is directly supplied to the low-potential-side power supply. Power is supplied to a third C supplied through a third transistor.
There is provided a semiconductor integrated logic circuit comprising: a MOS logic circuit; and a sleep mode control circuit capable of setting a first mode, a second mode, and a third mode transistor to an active mode and a sleep mode independently of each other. .

In this case, the first and third transistors are n-MOS transistors, and the second transistor is a p-MOS transistor.
It is preferably a type transistor.

As described in claim 10, the first
The device parameter of the transistor of the first CMO
The sum of the sub-threshold currents leaking from the first transistor is set smaller than the sum of the sub-threshold currents leaking from the S logic circuit group, and the device parameter of the second transistor is
Is set such that the sum of the sub-threshold currents leaking from the second transistor is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group, and the device parameter of the first transistor is the first. It is preferable that the sum of the sub-threshold currents leaking from the first transistor is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group.

As described in claim 11, it is preferable that the first and second signal transmission circuits are arranged between the first, second and third CMOS logic circuits.

For example, each of the first and second signal transmission circuits controls a line disconnection circuit for controlling transmission and interruption of a signal, and controls fixing and release of a signal. It can be composed of a combination with a signal fixing circuit.

According to a thirteenth aspect, the first, second and third CMOS logic circuits may be independently set to an active mode and a sleep mode by a sleep mode control circuit. preferable.

As described in the fourteenth and fifteenth aspects, for example, the line disconnection circuit in one of the first and second signal transmission circuits comprises a make-type switch, and the other in the other signal transmission circuit. The line disconnection circuit is n
-It may be formed of a transfer gate including a MOS transistor and a p-MOS transistor.

A sixteenth aspect of the present invention is an inverter circuit comprising a CMOS transistor having a device parameter with a small sub-threshold leakage current and a C circuit having a low threshold value.
CMOS consisting of MOS transistors and operating at high speed
A logic circuit group, a high-potential-side power supply is supplied directly, a low-potential-side power supply is supplied via a first transistor, and a CMOS logic circuit connected in parallel with the inverter circuit; A signal transmission circuit connected between the semiconductor integrated logic circuit and the logic circuit.

As described in claim 17, for example, the first transistor can be formed of an n-MOS type transistor, and the device parameter of this first transistor is described in claim 18. It is preferable that the sum of the sub-threshold currents leaking from the first transistor is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group.

As described in claim 19, the signal transmission circuit comprises, for example, a combination of a line dividing circuit for controlling transmission and interruption of a signal and a signal fixing circuit for controlling fixing and release of a signal. can do.

As described in the twentieth aspect, the line dividing circuit can be composed of, for example, a make-type switch.

According to a twenty-first aspect, the signal fixing circuit includes a bistable element having a first inverter circuit and a second inverter circuit, and the bistable element includes:
The connection point between the line disconnection circuit and the inverter circuit is one node, the second inverter circuit receives the connection node between the line disconnection circuit and the inverter circuit as an input, and the output of the second inverter circuit is the output of the first inverter circuit. It is preferable that the output of the first inverter circuit is fed back to a connection node between the line dividing circuit and the inverter circuit as an input.

According to a twenty-second aspect, the sleep mode control inversion signal applied to the first transistor from the sleep mode control circuit transitions from a high potential signal to a low potential signal, thereby turning off the first transistor. Supplying power to one CMOS logic circuit group and blocking leakage of subthreshold current from the first CMOS logic circuit group, and converting a signal transmitted from the first inverter circuit to the first CMOS logic circuit. A step of dividing, a step of fixing a signal output to the first CMOS logic circuit group, a step of dividing a signal transmitted from the first CMOS logic circuit to the second CMOS logic circuit, 2 CM
Fixing a signal output to the OS logic circuit group;
A method for controlling the above-described semiconductor integrated logic circuit, comprising:

According to a twenty-third aspect of the present invention, the step of releasing the fixation of the signal applied to the first CMOS logic circuit and the state in which the path for transmitting the signal from the first inverter circuit to the first CMOS logic circuit are cut off. From the first CMOS logic circuit to the conduction state, the step of releasing the fixation of the signal applied to the second CMOS logic circuit, and the path for transmitting the signal from the first CMOS logic circuit to the second CMOS logic circuit. The first transistor is turned on by changing the state from the divided state to the conductive state, and by changing the sleep mode switching inversion signal applied from the sleep mode control circuit to the first CMOS logic circuit from a low potential signal to a high potential signal. State,
Starting the power supply to the first CMOS logic circuit group.

According to a twenty-fourth aspect of the present invention, the sleep mode switching inversion signal applied from the sleep mode control circuit to the first and second transistors is changed from a high potential signal to a low potential signal, so that the first and second transistors are switched. To shut off the power supply to the first and second CMOS logic circuit groups and to cut off the leakage of the subthreshold current from the first and second CMOS logic circuit groups. The signal transmitted to the first CMOS logic circuit, the signal transmitted from the first CMOS logic circuit to the second CMOS
The signal transmitted to the S logic circuit and the second CMO
A step of dividing the signal transmitted from the S logic circuit to the second inverter circuit, and a step of fixing signals output to the first and second CMOS logic circuit groups.
A method for controlling the above semiconductor integrated logic circuit is provided.

A twenty-fifth aspect is a step of releasing the fixation of the signal applied to the first and second CMOS logic circuits, and a path for transmitting the signal from the first inverter circuit to the first CMOS logic circuit. , To the first CMOS logic circuit
Path for transmitting a signal to the CMOS logic circuit of
Transitioning the path for transmitting a signal from the CMOS logic circuit to the second inverter circuit from the divided state to the conductive state, and the first and second CMOs from the sleep mode control circuit.
The transition of the sleep mode switching inversion signal applied to the S logic circuit from the low potential signal to the high potential signal causes the first
And the second transistor are turned on, and the first and second transistors are turned on.
Starting power supply to a group of CMOS logic circuits;
A method for controlling the above-described semiconductor integrated logic circuit, comprising:

[0067]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a system diagram of a semiconductor integrated logic circuit 101 according to a first embodiment of the present invention. Semiconductor integrated logic circuit 1 according to the present embodiment
The power supply circuit 01 includes a power supply circuit with a power supply cutoff function that achieves both high speed in the active mode and low power consumption in the sleep mode.

This semiconductor integrated logic circuit 101 includes a first inverter circuit INV9 and a second inverter circuit INV9.
V12, a first CMOS logic circuit MTC1 with a power cutoff function, a second CMOS logic circuit MTC2 with a power cutoff function, and each of the CMOS logic circuits MTC1 and MTC.
Sleep mode control circuit SMS for controlling operation of TC2
And is composed of

The first and second inverter circuits INV9 and INV12 are each formed of a CMOS transistor having a device parameter with a small sub-threshold leakage current.

The first CMOS logic circuit MTC1 is composed of CMOS transistors having a low threshold value and has as its main circuit a CMOS logic circuit group LGC4 which performs high-speed operation. The high-potential-side trajectory RVD2 (hereinafter, referred to as “real power supply line RVD2”) is directly supplied as a power distribution line, and the other low-potential-side power supply VSS is connected to the real low-potential side trajectory RVS2 (hereinafter, “real power supply line RVD2”). A pseudo low-potential-side trajectory RVSV3 (hereinafter referred to as a pseudo power supply line “RV2”) is connected via a control switch n-MOS transistor TS4 connected in series to a power supply line RVS2.
SV3 ") as the power distribution line.

The second CMOS logic circuit MTC2 is composed of CMOS transistors having a low threshold value, and has a CMOS logic circuit group LGC5 that performs high-speed operation as a main circuit. The low potential side trajectory RVS2 is directly supplied as a power distribution line,
The other high-potential-side power supply VDD is the actual high-potential-side trajectory RVDD2.
Pseudo high potential side trajectory RVDV via a control switch p-MOS transistor TS5 connected in series to
2 (hereinafter referred to as “pseudo power supply line RVDV2”) is supplied as a power distribution line.

Further, the opening and closing of the control switch n-MOS transistor TS4 is controlled in response to a sleep mode switching inversion signal SLB3 transmitted from the sleep mode control circuit SMS.
The S-type transistor TS5 is a sleep mode control circuit SM
Opening / closing is controlled in response to a sleep mode switching signal SL2 transmitted from S.

The device parameters of the control switch n-MOS type transistor TS4 are set in the semiconductor integrated logic circuit 1
The sub-threshold current leaked from the control switch n-MOS type transistor TS4 is set to be smaller than the sum of the sub-threshold current leaked from the CMOS logic circuit group LGC4 which is a component of No. 01. I have.

Similarly, the device parameter of the control switch p-MOS transistor TS5 is smaller than the sum of the sub-threshold currents leaked from the CMOS logic circuit group LGC5 by the sub-threshold leaked from the control switch p-MOS transistor TS5. The sum of the currents is set to be smaller.

Therefore, in the active mode, that is, the high potential sleep mode switching inversion signal SLB3
When (SLB3 = “1”) is applied to the control switch n-MOS transistor TS4, the control switch n-MOS transistor TS4 is in a conductive state, and the CMOS logic circuit group LGC4 has a low potential. The side power VSS is supplied.

On the other hand, in the sleep mode, that is, the sleep mode switching inversion signal SLB3 (S
When (LB3 = "0") is applied to the control switch n-MOS type transistor TS4, the control switch n-MOS type transistor TS4 is in the cutoff state, and the low potential side to the CMOS logic circuit group LGC4 is applied. Power supply V
The supply of SS is cut off, and the sub-threshold leakage current can be suppressed. As a result, low power consumption in the sleep mode can be achieved.

Similarly, in the active mode, that is, the sleep mode switching signal SL2 (SL
2 = “1”) is applied to the control switch p-MOS transistor TS5, the control switch p-MOS transistor TS5 is conductive, and the CMOS logic circuit group LGC5 has a high potential side. Power supply VD
D is supplied.

On the other hand, in the sleep mode, that is, the sleep mode switching inversion signal SL2 (SL
2 = “0”) is applied to the control switch p-MOS transistor TS5, the control switch p-MOS transistor TS5 is cut off, and the low potential side to the CMOS logic circuit group LGC5 is applied. Power supply VS
The supply of S is cut off, and the sub-threshold leakage current can be suppressed.

As described above, the first and second inverter circuits INV9 and INV12 are composed of CMOS transistors having device parameters with a small sub-threshold leakage current.
Even when power is supplied directly from both power sources DD and the low-potential-side power source VSS to the actual high-potential-side trajectory RVD2 and the actual low-potential-side trajectory RVS2, the sub-threshold leakage current does not increase. It does not flow. However, a CMOS transistor having a device parameter with a small subthreshold leakage current has a trade-off, and the operation speed is slow.

Further, a first CMOS having a first inverter circuit INV9 and a power reduction circuit in the sleep mode is provided.
Between the first CMOS logic circuit MT and the logic circuit MTC1
C1 and second C with power reduction circuit in sleep mode
Between the MOS logic circuit MTC2 and the second CMOS logic circuit MTC2 and between the second inverter circuit INV12, there are a first signal transmission circuit TRS1, a second signal transmission circuit TRS2, and a third signal, respectively. A transmission circuit TRS3 is provided.

The first to third signal transmission circuits TR
S1-TRS3 are line dividing circuits CTF1-
It is composed of a combination of CTF3 and signal fixing circuits CLP1 to CLP3, and performs a functional operation in response to signals a1, a3, and a5 from the sleep mode control circuit SMS, respectively.

The sleep mode control circuit SMS also controls the control switch n-MOS transistor TS4 and the control switch p-MOS transistor TS5, and
CMOS logic circuit MTC1 and second CMOS logic circuit MTC2 can be independently controlled between the active mode and the sleep mode.

The operation of the semiconductor integrated logic circuit 101 according to this embodiment shown in FIG. 1 will be described below with reference to the flowcharts shown in FIGS.

First, a control operation in the case where the first CMOS logic circuit MTC1 forming the semiconductor integrated logic circuit 101 shown in FIG. 1 makes a mode transition from the active mode to the sleep mode will be described with reference to FIG. .

As a first stage, the sleep mode control circuit SMS includes a first mode with a power reduction circuit in the sleep mode.
Of the CMOS logic circuit MTC1 from the active mode to the sleep mode, and a mode transition process is started in response to the command (step 101).

In the active mode of the first CMOS logic circuit MTC1, the first CMOS logic circuit MTC1 supplies a high potential signal (SLB3 = “1”) from the sleep mode control circuit SMS as the sleep mode switching inversion signal SLB3. ") Is applied, and the n-MOS transistor TS4 is in a conductive state.

The first signal transmission circuit TRS1 has the first signal transmission circuit TRS1.
Output signal from the inverter circuit INV9 of the first CM
In a state of directly transmitting to the OS logic circuit MTC1,
Similarly, the second signal transmission circuit TRS2 is a first CMOS
The state is such that the output signal from logic circuit MTC1 is directly transmitted to second CMOS logic circuit MTC2.

In the second stage, in response to the mode switching command from the active mode to the sleep mode issued in the first stage, the sleep mode switching inversion signal SLB3 transmitted from the sleep mode control circuit SMS is changed from the high potential signal. A transition is made to a low potential signal (SLB3 = "0").
By the transition of the sleep mode switching inversion signal SLB3, the n-MOS transistor TS4 is turned off, and power supply to the CMOS logic circuit group LGC4 and CM
A transition is made to a sleep mode in which leakage of the subthreshold current from the OS logic circuit group LGC4 can be cut off (step 102).

As a third step, a signal a1 is issued from the sleep mode control circuit SMS to the first signal transmission circuit TRS1 in response to the completion of the operation in the second step. This signal a
1, the first-stage circuit (first inverter circuit INV
The signal path directly transmitted from 9) to the first CMOS logic circuit MTC1 is divided by the line dividing circuit CTF1 together with the leakage current path (step 103).

As a fourth step, in response to the completion of the operation in the third step, the first CMOS circuit is activated by the signal fixing circuit CLP1.
CMOS logic circuit group LGC forming logic circuit MTC1
4 is fixed (step 104).

At the end of the fourth stage, the first signal transmission circuit TRS1 issues a signal a2 to the sleep mode control circuit SMS to transmit the end of the fourth stage.

In this case, in the example of the semiconductor integrated logic circuit 101 shown in FIG. 1, the signal fixing circuit CLP1 needs to output a high potential signal ("1"). This is because the leakage current path assumed in the first CMOS logic circuit MTC1 is the gate-tunnel through current path PS1, which is a problem of the prior art shown in FIG. 10, and avoids the generation of the leakage path PS1. In order to do so, the input signal to the first CMOS logic circuit MTC1 shown in FIG. 1 needs to be a high-potential signal ("1").

As a fifth step, a signal a3 is issued from the sleep mode control circuit SMS to the signal transmission circuit TRS2 in response to the completion of the operation in the second step. By the signal a3, the signal directly transmitted from the preceding circuit (the first CMOS logic circuit MTC1) to the second CMOS logic circuit MTC2 is divided by the line dividing circuit CTF2 together with the leakage current path (Step 105). .

As a sixth step, in response to the completion of the operation in the fifth step, the second CMOS is operated by the signal fixing circuit CLP2.
CMOS logic circuit group LGC forming logic circuit MTC2
5 is fixed (step 106).

In this case, in the example of the semiconductor integrated logic circuit 101 shown in FIG. 1, the signal fixing circuit CLP2 needs to output a low potential signal ("0"). This is because, as a leakage current path assumed in the example of the second CMOS logic circuit MTC2, a gate tunnel through current path PS3 which is a problem of the related art shown in FIG.
This is because, in order to avoid the occurrence of the leakage path PS3, the input signal to the second CMOS logic circuit MTC2 shown in FIG. 1 needs to be a low potential signal ("0").

At the end of the sixth stage, the second signal transmission circuit TRS2 issues a signal a4 to the sleep mode control circuit SMS to transmit the end of the sixth stage.

As a seventh step, the signals a2 respectively generated from the first signal transmission circuit TRS1 and the second signal transmission circuit TRS2 in response to the completion of the operations in the fourth and sixth steps
And a4, the sleep mode control circuit SMS
It is recognized that the mode transition process from the active mode to the sleep mode of the first CMOS logic circuit MTC1 has been completed (step 107).

Next, a control operation when the first CMOS logic circuit MTC1 forming the semiconductor integrated logic circuit 101 shown in FIG. 1 makes a mode transition from the sleep mode to the active mode will be described with reference to FIG. .

As the first stage, the sleep mode control circuit SMS issues a mode switching command for switching the first CMOS logic circuit MTC1 from the sleep mode to the active mode, and the mode transition process is started (step 201). ).

In the sleep mode of the first CMOS logic circuit MTC1, the n-MOS transistor TS4 outputs a low potential signal (S) from the sleep mode control circuit SMS as the sleep mode switching inversion signal SLB3.
LB3 = “0”), and therefore n−M
The OS type transistor TS4 is in a cutoff state.

In the first signal transmission circuit TRS1, the first inverter circuit INV9 switches to the first CMO
Signal transmission to the S logic circuit MTC1 is performed by the line dividing circuit CTF.
Blocked by 1. Further, a high potential signal ("1") is applied to the first CMOS logic circuit MTC1 by the signal fixing circuit CLP1.

Similarly, in second signal transmission circuit TRS2, first CMOS logic circuit MTC1 to second C
The signal transmission to the MOS logic circuit MTC2 is performed by the line dividing circuit C.
Blocked by TF2. Further, the second CMOS
A low potential signal (“0”) is applied to the logic circuit MTC2 by the signal fixing circuit CLP2.

As a second step, a signal a1 is issued from the sleep mode control circuit SMS to the first signal transmission circuit TRS1 in response to the end of the first step. In response to the signal a1, the signal fixing circuit CLP1 releases the fixing of the signal applied to the first CMOS logic circuit MTC1 (step 202).

As the third stage, in response to the end of the second stage, the first circuit (the first inverter circuit INV9), which has been divided by the line dividing circuit CTF1, changes to the first C signal.
The direct transmission path of the signal to the MOS logic circuit MTC1 returns to the conductive state (step 203).

At the end of the third stage, the first signal transmission circuit TRS1 issues a signal a2 to the sleep mode control circuit SMS to transmit the end of the third stage.

As a fourth step, the signal a3 is issued from the sleep mode control circuit SMS to the second signal transmission circuit TRS2 in response to the end of the second step. In response to the signal a3, the signal fixing circuit CLP2 releases the fixing of the signal applied to the second CMOS logic circuit MTC2 (Step 204).

As a fifth step, in response to the end of the fourth step, the circuit at the preceding stage (first CMOS logic circuit MTC1), which has been divided by the line dividing circuit CTF2, changes to the circuit at the next stage (second CMOS logic circuit). The direct transmission path of the signal to MTC2) returns to the conductive state (step 20).
5).

At the end of the fifth stage, second signal transmission circuit TRS2 issues signal a4 to sleep mode control circuit SMS to transmit the end of the fifth stage.

As a sixth step, the sleep mode control is performed by the signals a2 and a4 respectively issued from the first signal transmission circuit TRS1 and the second signal transmission circuit TRS2 in response to the end of the third and fifth steps. The circuit SMS sets the sleep mode switching inversion signal SLB3 issued to the first CMOS logic circuit MTC1 to a low potential (SLB3 = "0").
To a high potential (SLB3 = “1”). As a result, the n-MOS type transistor TS4 is turned on, power supply to the CMOS logic circuit group LGC4 is started, and the mode transition process from the sleep mode to the active mode of the first CMOS logic circuit MTC1 is completed. (Step 206).

Next, referring to FIG. 4, both first CMOS logic circuit MTC1 and second CMOS logic circuit MTC2 forming semiconductor integrated logic circuit 101 shown in FIG. 1 are switched from the active mode to the sleep mode. The control operation in the case of transition will be described.

As a first step, the sleep mode control circuit SMS issues a mode switching command for switching the first CMOS logic circuit MTC1 and the second CMOS logic circuit MTC2 from the active mode to the sleep mode. Correspondingly, a mode transition process is started (step 301).

As in the case of mode switching shown in FIG. 2, in the active mode of the first CMOS logic circuit MTC1, the first CMOS logic circuit MTC1 includes:
As the sleep mode switching inversion signal SLB3, the high potential signal (SLB3 =
"1") is applied, and the n-MOS transistor TS4 is in a conductive state.

Similarly, the second CMOS logic circuit MTC2
In the active mode, the second CMOS logic circuit MTC2 supplies the sleep mode switching signal SL2 to the low potential signal (S
L2 = "0") is applied, and the p-MOS transistor TS5 is in a conductive state.

Further, the first signal transmission circuit TRS1 is
Output signal from the inverter circuit INV9 of the first CM
In a state of directly transmitting to the OS logic circuit MTC1,
Similarly, the second signal transmission circuit TRS2 is a first CMOS
The state is such that the output signal from logic circuit MTC1 is directly transmitted to second CMOS logic circuit MTC2.

In the second stage, in response to the mode switching command from the active mode to the sleep mode issued in the first stage, the sleep mode switching inversion signal SLB3 transmitted from the sleep mode control circuit SMS is changed from the high potential signal. The transition is made to the low potential signal (SLB3 = "0"), and the sleep mode inversion signal SL2 transmitted from the sleep mode control circuit SMS is transited from the low potential signal to the high potential signal (SL2 = "1"). The sleep mode switching inversion signal SLB3 and the sleep mode inversion signal SL
By the transition of 2, the n-MOS transistor TS4 and the p-MOS transistor TS5 are cut off,
CMOS logic circuit group LGC4 and CMOS logic circuit group L
Power supply to GC5 and CMOS logic circuit group LG
A transition is made to a sleep mode in which leakage of subthreshold current from C4 and CMOS logic circuit group LGC5 can be cut off (step 302).

As a third step, in response to the completion of the operation in the second step, the sleep mode control circuit SMS sends the signals to the first signal transmission circuit TRS1, the second signal transmission circuit TRS2, and the third signal transmission circuit TRS3, respectively. Signals a1, a3 and a5 are emitted. These signals a1, a3 and a5
As a result, the first inverter circuit INV9 switches to the first C
The signal path directly transmitted to the MOS logic circuit MTC1, the signal path from the first CMOS logic circuit MTC1 to the second CM
The signal path directly transmitted to the OS logic circuit MTC2 and the signal path directly transmitted from the second CMOS logic circuit MTC2 to the second inverter circuit INV12 are line dividing circuits CTF1, CTF2 and CTF3.
(Step 3)
03).

As a fourth stage, in response to the completion of the operation in the third stage, the signal fixing circuits CLP1, CLP2 and CLP3
Thus, the signal output to the CMOS logic circuit group LGC4 forming the first CMOS logic circuit MTC1 and the second
A signal output to CMOS logic circuit group LGC5 constituting CMOS logic circuit MTC2 is fixed (step 304).

At the end of the fourth stage, the first signal transmission circuit TRS1, the second signal transmission circuit TRS2, and the third
Of the sleep mode control circuit S
Issue signals a2, a4 and a6 to the MS to signal the end of the fourth stage.

As a fifth step, the first signal transmission circuit TRS1 and the second signal transmission circuit T respond to the end of the third step.
The sleep mode control circuit SMS switches the active mode of the first CMOS logic circuit MTC1 and the second CMOS logic circuit MTC2 from the active mode to the sleep mode by the signals a2, a4 and a6 respectively issued from the RS2 and the third signal transmission circuit TRS3. It is recognized that the mode transition process has been completed (step 305).

Next, referring to FIG. 5, both first CMOS logic circuit MTC1 and second CMOS logic circuit MTC2 forming semiconductor integrated logic circuit 101 shown in FIG. 1 are switched from the sleep mode to the active mode. The control operation in the case of transition will be described.

As a first step, the sleep mode control circuit SMS issues a mode switching command for switching the first CMOS logic circuit MTC1 and the second CMOS logic circuit MTC2 from the sleep mode to the active mode. Then, a mode transition process is started (step 401).

As described above, in the sleep mode of the first CMOS logic circuit MTC1, the n-MOS
The low potential signal (SLB3 = "0") from the sleep mode control circuit SMS is applied to the type transistor TS4 as the sleep mode switching inversion signal SLB3, and therefore, the n-MOS type transistor TS4 is in the cutoff state. .

Similarly, the second CMOS logic circuit MTC2
In the sleep mode, the p-MOS transistor TS5 receives the sleep mode switching signal SL2 as the sleep mode switching signal SL2.
From the sleep mode control circuit SMS, a high potential signal (SL2
= “1”), and the p-MOS transistor TS5 is in a cut-off state.

In the first signal transmission circuit TRS1, the first inverter circuit INV9 switches the first CMO
Signal transmission to the S logic circuit MTC1 is performed by the line dividing circuit CTF.
Blocked by 1. Further, a high potential signal ("1") is applied to the first CMOS logic circuit MTC1 by the signal fixing circuit CLP1.

Similarly, in second signal transmission circuit TRS2, first CMOS logic circuit MTC1 to second C
The signal transmission to the MOS logic circuit MTC2 is performed by the line dividing circuit C.
Blocked by TF2. Further, the second CMOS
A low potential signal (“0”) is applied to the logic circuit MTC2 by the signal fixing circuit CLP2.

In the second stage, in response to the end of the first stage, the sleep mode control circuit SMS sends the signal a1 to the first signal transmission circuit TRS1, the second signal transmission circuit TRS2 and the third signal transmission circuit TRS3. , A3 and a5 are emitted. By these signals a1, a3 and a5, the signal fixing circuits CLP1, CLP2 and CLP3 cause the first C
MOS logic circuit MTC1 and second CMOS logic circuit M
The fixation of the signal applied to TC2 is released (step 402).

As a third stage, in response to the end of the second stage, the signal of the signal from the first inverter circuit INV9 to the first CMOS logic circuit MTC1, which has been divided by the line dividing circuits CTF1, CTF2 and CTF3, is output. A direct transmission path, a signal transmission path from the first CMOS logic circuit MTC1 to the second CMOS logic circuit MTC2, and
The signal transmission paths from the second CMOS logic circuit MTC2 to the second inverter circuit INV12 return to the conductive state, respectively (step 403). As a fourth step, the first signal transmission circuit TRS1,
Second signal transmission circuit TRS2 and third signal transmission circuit T
By the signals a2, a4 and a6 respectively issued from R3, the sleep mode control circuit SMS changes the sleep mode switching inversion signal SLB3 issued to the first CMOS logic circuit MTC1 from the low potential (SLB3 = “0”) to the high potential. (SLB3 = “1”), and at the same time, the second C
The sleep mode switching signal SL2 issued to the MOS logic circuit MTC2 is changed from a high potential (SL2 = “1”) to a low potential (SL2 = “0”) (Step 40).
4).

As a result, both the n-MOS transistor TS4 and the p-MOS transistor TS5 become conductive, and the CMOS logic circuit groups LGC4 and CMO
Power supply to the S logic circuit group LGC5 is started, and the process of mode transition from the sleep mode to the active mode of the first CMOS logic circuit MTC1 and the second CMOS logic circuit MTC2 is completed (step 405). (Second Embodiment) FIG. 6 is another system diagram of a semiconductor integrated logic circuit 102 according to a second embodiment of the present invention. The semiconductor integrated logic circuit 102 according to the present embodiment includes a power supply circuit with a power cutoff function that achieves both high speed in the active mode and low power consumption in the sleep mode.

The semiconductor integrated logic circuit 10 according to the present embodiment
2 is a first C with a power reduction circuit in sleep mode.
MOS logic circuit MTC3, second CMOS logic circuit MTC4 with power reduction circuit in sleep mode, third CMOS logic circuit MTC5 with power reduction circuit in sleep mode, sleep mode control circuit (not shown) )
And these three CMOS logic circuits MT
C3, MTC4 and MTC5 are connected to each other in parallel.

The first CMOS logic circuit MTC3 is composed of a CMOS logic circuit group LGC6 which is composed of CMOS transistors having a low threshold value and operates at high speed, and one end of which is directly connected to the high potential side power supply VDD. The terminal is connected to the low-potential power supply VSS via an n-MOS transistor TS6 for a control switch connected in series to the low-potential power supply VSS, and the low-potential power supply VSS is supplied from the low-potential-side pseudo power supply line. It has become so.

The second CMOS logic circuit MTC4 is composed of a CMOS transistor having a low threshold value, has a CMOS logic circuit group LGC6 operating at high speed as a main circuit, and has one end directly connected to the low potential power supply VSS and the other end. P-M for a control switch connected in series to the high-potential-side power supply VDD
High-potential-side power supply VDD via OS-type transistor TS7
To the high-potential-side power supply V from the high-potential-side pseudo power supply line.
DD is supplied.

The third CMOS logic circuit MTC5 is composed of a CMOS transistor having a low threshold value, has a CMOS logic circuit group LGC8 operating at high speed as a main circuit, and has one end directly connected to the high potential side power supply VDD and the other end. N-M for a control switch connected in series to the low potential side power supply VSS
The low-potential-side power supply VSS via the OS-type transistor TS8
To the low-potential-side power supply V
The power is supplied to the SS.

The opening and closing of the control switch n-MOS transistor TS6 is controlled in response to the sleep mode switching inversion signal SLB4 issued from the sleep mode control circuit. Similarly, the opening and closing of the control switch p-MOS transistor TS7 is controlled in response to a sleep mode switching signal SL3 issued from the sleep mode control circuit.
The opening and closing of the control switch n-MOS transistor TS8 is controlled in response to the sleep mode switching inversion signal SLB5 issued from the sleep mode control circuit.

The device parameters of the control switch n-MOS transistor TS6 are set in the semiconductor integrated logic circuit 1
02, so that the sum of the sub-threshold currents leaking from the control switch n-MOS transistor TS6 is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC6, which is a constituent element of the N.02.
Is set.

Similarly, the device parameter of the control switch p-MOS transistor TS7 is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC7.
The setting is such that the sum of the sub-threshold currents leaking from S7 is smaller.

Similarly, the device parameter of the control switch n-MOS transistor TS8 is larger than the sum of the sub-threshold currents leaked from the CMOS logic circuit group LGC8.
The setting is such that the sum of the sub-threshold currents leaking from S8 is smaller.

Therefore, in the active mode, that is, the control switch n-MOS type transistor TS
6, the sleep mode switching inversion signal SLB4 (S
When LB4 = “1”) is applied, the control switch n-MOS transistor TS6 is in a conductive state, and the low-potential-side power supply VSS is supplied to the CMOS logic circuit group LGC6.

On the other hand, in the sleep mode, that is, the low potential sleep mode switching inversion signal SLB4 (SLB) is supplied to the control switch n-MOS transistor TS6.
4 = “0”), the control switch n-MOS transistor TS6 is in a cutoff state, and the low-potential-side power supply V to the CMOS logic circuit group LGC6 is
The supply of the SS is also cut off, the sub-threshold leakage current is suppressed, and low power consumption in the sleep mode can be achieved.

Similarly, in the active mode, that is, the control switch p-MOS transistor TS
7, a low-potential sleep mode switching signal SL3 (SL3 =
When “0”) is applied, the control switch p-MOS transistor TS7 is in a conductive state, and the low-potential-side power supply VS is supplied to the CMOS logic circuit group LGC7.
S is supplied.

On the other hand, in the sleep mode, that is, a high potential sleep mode switching signal SL3 (SL3 =
When "1") is applied, the control switch p-MOS transistor TS7 is in a cut-off state, and the low potential side power supply VS to the CMOS logic circuit group LGC7 is supplied.
The supply of S is cut off, and the sub-threshold leakage current can be suppressed.

Similarly, in the active mode, that is, the control switch n-MOS type transistor TS
8, the sleep mode switching inversion signal SLB5 (S
When LB5 = “1”) is applied, the control switch n-MOS transistor TS8 is in a conductive state, and the low-potential-side power supply VSS is supplied to the CMOS logic circuit group LGC8.

On the other hand, in the sleep mode, that is, the low potential sleep mode switching inversion signal SLB5 (SLB) is supplied to the control switch n-MOS transistor TS8.
5 = “0”) is applied, the control switch n-MOS transistor TS8 is in the cutoff state, and the low potential side power supply V to the CMOS logic circuit group LGC8 is applied.
The supply of the SS is also cut off, the sub-threshold leakage current can be suppressed, and the power consumption in the sleep mode can be reduced. Furthermore, the first CM
OS logic circuit MTC3 and second CMOS logic circuit MTC
4 and between the second CMOS logic circuit MTC4 and the third CMOS logic circuit MTC5, a first signal transmission circuit TRS4 and a second signal transmission circuit TRC, respectively.
S5 is arranged.

The first signal transmission circuit TRS4 is composed of a combination of a line dividing circuit CTF4 and a signal fixing circuit CLP4, and the second signal transmission circuit TRS5 is composed of a combination of a line dividing circuit CTF5 and a signal fixing circuit CLP5. ing.

The first to third CMOS logic circuits M
Each of TC3, MTC4 and MTC5 is a sleep mode switching inversion signal SLB4 and a sleep mode inversion signal SL
3. The mode setting can be independently set between the active mode and the sleep mode by each of the sleep mode switching inversion signals SLB5.

Signal fixing circuits CLP4 and CLP5 are controlled to fix and release signals by control signals EQ1 and EQ2 issued from a sleep mode control circuit (not shown).

The control signals EQ1 and EQ2 are inverted by inverter circuits INV13 and INV14, respectively, and the line disconnection circuits CTF4 and CTF5 control the transmission and cutoff of the signals by the inverted signals.

The line disconnecting circuit CTF4 constituting the first signal transmission circuit TRS4 is formed of a make-type switch having characteristics such that the sub-threshold current leakage and the gate tunnel current leakage are small.

The line disconnecting circuit CTF5 constituting the second signal transmission circuit TRS5 has an n-M characteristic in which sub-threshold current leakage and gate / tunnel current leakage are small.
It comprises a transfer gate composed of OS type and p-MOS type transistors.

Note that a transistor with less subthreshold current leakage and gate / tunnel current leakage can be realized by increasing the threshold value, increasing the gate length, or increasing the thickness of the gate insulating film.

The signal fixing circuit CLP4 constituting the first signal transmission circuit TRS4 realizes signal fixing, particularly, fixing of a low potential signal by a pull-down type circuit having a make-type switch element. On the other hand, the second signal transmission circuit TRS
The signal fixing circuit CLP5 constituting the circuit 5 realizes signal fixing, in particular, fixing of a high potential signal by a pull-up type circuit including a p-MOS transistor.

The operation of the semiconductor integrated logic circuit 102 according to the present embodiment shown in FIG. 6 will be described below with reference to the timing chart shown in FIG.

First, as the first half of the timing chart shown in FIG. 7, a control operation in the case where the second CMOS logic circuit MTC4 makes a mode transition from the active mode to the sleep mode will be described.

In the initial state, the sleep mode switching signal SL3 (SL3 = "0") of the low potential signal and the sleep mode switching inversion signal SLB4 (SLB4) of the high potential signal
= "1") and SLB5 (SLB5 = "1")
First to third CMOS logic circuits MTC3, MTC4,
Assume that MTCs 5 are all in active mode.

At this time, the control signals EQ1 and EQ2 are both low potential signals (EQ1 = EQ2 = “0”).
The make switch forming the line dividing circuit CTF4 and the CMOS transfer gate forming the line dividing circuit CTF5 are both conductive. On the other hand, the signal fixing circuit CLP4
Is in the cut-off state, and the pull-up circuit of the p-MOS transistor forming the signal fixing circuit CLP5 is also in the cut-off state. Therefore, the signal N1 from the first CMOS logic circuit MTC3 to the second CMOS logic circuit MTC4 and the signal N2 from the second CMOS logic circuit MTC4 to the third CMOS logic circuit MTC5 are transmitted as usual. Is available.

Here, the transition of the sleep mode switching signal SL3 from the low potential to the high potential causes the control switch p-MOS transistor TS7 to shift to the cutoff state, thereby switching the mode of the second CMOS logic circuit MTC4. Execute. That is, the second CMOS logic circuit M
The TC4 is shifted from the active mode to the sleep mode.

After an arbitrary hold time,
By making the control signals EQ1 and EQ2 transition from the low potential to the high potential, both the make-type switch forming the line dividing circuit CTF4 and the CMOS transfer gate forming the line dividing circuit CTF5 are cut off. On the other hand, the make switch forming the signal fixing circuit CLP4 is turned on, and the pull-up circuit of the p-MOS transistor forming the signal fixing circuit CLP5 is turned on. For this reason, the CMO constituting the first CMOS logic circuit MTC3
S logic circuit group LGC6 and third CMOS logic circuit MT
The input signals N1 and N2 to the LGC8 constituting C5 are fixed to a low potential signal and a high potential signal, respectively, after an arbitrary delay time.

Therefore, the first CMOS logic circuit MTC3
In addition, the generation of a leakage current path assumed in second CMOS logic circuit MTC4, that is, a leakage current path corresponding to gate tunnel through current path PS1, which is a problem of the prior art shown in FIG. 10, can be avoided. .

Next, a method of transitioning the second CMOS logic circuit MTC4 from the sleep mode to the active mode will be described below.

By causing the control signals EQ1 and EQ2 to transition from the high potential to the low potential, the line disconnecting circuit CTF4
And the CMOS transfer gate forming the line disconnecting circuit CTF5 are both conductive.

On the other hand, the make switch forming the signal fixing circuit CLP4 is turned off, and the pull-up circuit of the p-MOS transistor forming the signal fixing circuit CLP5 is also turned off. Therefore, the first CMOS logic circuit MTC
3 to the second CMOS logic circuit MTC4 and the signal N1 from the second CMOS logic circuit MTC4 to the third CMOS logic circuit MTC4.
Since the signal N2 to the logic circuit MTC5 can be transmitted in a normal state, these signals N1 and N2 are in their original signal states after an arbitrary delay time, that is, the states of the high potential and the low potential, respectively. Return to.

Then, after an arbitrary set-up time has elapsed, the sleep mode switching signal SL3 is changed from a high potential to a low potential, whereby the control switch p-MOS
The type transistor TS7 is turned on, and the second C
The mode switching of the MOS logic circuit MTC4 from the sleep mode to the active mode is executed, and the operation is completed.

Next, as the second half of the timing chart shown in FIG. 7, the first CMOS logic circuit MTC3 and the third CMOS
Control operation when the CMOS logic circuit MTC5 of FIG.

In the initial state, the sleep mode switching signal SL3 (SL3 = "0") of the low potential signal and the sleep mode switching inversion signal SLB4 (SLB4) of the high potential signal
= "1") and SLB5 (SLB5 = "1")
The first CMOS logic circuit MTC3 and the third CMOS logic circuit MTC5 are all in the active mode.

At this time, the control signals EQ1 and EQ2 are both at a low potential (EQ1 = EQ2 = "0"), and the make-type switch forming the line dividing circuit CTF4 and the CMOS transfer gate forming the line dividing circuit CTF5 are both conductive. It is in. On the other hand, the make switch forming the signal fixing circuit CLP4 is in the cutoff state, and the signal fixing circuit CL
The pull-up circuit of the p-MOS transistor forming P5 is also in the cut-off state. Therefore, the signal N1 from the first CMOS logic circuit MTC3 to the second CMOS logic circuit MTC4 and the signal N1 from the second CMOS logic circuit MTC4 to the third C
Signal N2 to MOS logic circuit MTC5 is in a state where it can be transmitted as usual.

Here, the sleep mode switching inversion signal SL
B4 and SLB5 are transitioned from the high potential to the low potential, so that the control switch n-MOS transistor TS
6 and the n-MOS transistor TS8 are turned off, and the first CMOS logic circuit MTC3 and the second CMOS
The mode of the MOS logic circuit MTC5 is switched.
That is, the first CMOS logic circuit MTC3 and the second CMOS logic circuit MTC5 are shifted from the active mode to the sleep mode.

After an arbitrary hold time,
By making the control signals EQ1 and EQ2 transition from the low potential to the high potential, both the make-type switch forming the line dividing circuit CTF4 and the CMOS transfer gate forming the line dividing circuit CTF5 are cut off. On the other hand, the make switch forming the signal fixing circuit CLP4 is turned on, and the pull-up circuit of the p-MOS transistor forming the signal fixing circuit CLP5 is turned on.

The input signal N1 to the CMOS logic circuit group LGC6 forming the first CMOS logic circuit MTC3 is shifted from a high potential to a low potential during the active mode, and similarly, the third CMOS logic circuit MTC5 is formed. The input signal N2 to the CMOS logic circuit group LGC8 changes from a low potential to a high potential during the active mode. These input signals N1 and N2 are fixed to low and high potential signals, respectively.

Therefore, the first CMOS logic circuit MTC4
In addition, it is possible to avoid the generation of a leakage current path assumed in the third CMOS logic circuit MTC5, that is, a leakage current path corresponding to the gate tunnel through current path PS3 which is a problem of the prior art shown in FIG. .

Next, a method of transitioning the first CMOS logic circuit MTC3 and the third CMOS logic circuit MTC5 from the sleep mode to the active mode will be described below.

First, by causing the control signals EQ1 and EQ2 to transition from high potential to low potential, the line disconnection circuit C
Make-type switch and line disconnecting circuit CTF forming TF4
5, the CMOS transfer gates are both conductive.

On the other hand, the make switch forming the signal fixing circuit CLP4 is turned off, and the pull-up circuit of the p-MOS transistor forming the signal fixing circuit CLP5 is also turned off. Therefore, the first CMOS logic circuit MTC
3 to the second CMOS logic circuit MTC4 and the signal N1 from the second CMOS logic circuit MTC4 to the third CMOS logic circuit MTC4.
Since the signal N2 to the logic circuit MTC5 can be transmitted as usual, these signals return to the low potential state and the high potential state after an arbitrary delay time.

After an arbitrary setup time has passed, the sleep mode switching inversion signals SLB4 and SLB5
Is changed from a low potential to a high potential, thereby turning on the control switch n-MOS transistors TS6 and TS8. Thereby, the first CMOS
Logic circuit MTC3 and third CMOS logic circuit MTC5
Is switched from the sleep mode to the active mode.

At this stage, similarly to the initial state, the first to third CMOS logic circuits MTC3, MTC4, MTC
5 are all in the active mode.

After an arbitrary removal time has elapsed from the transition of the sleep mode switching inversion signals SLB4 and SLB5 from the low potential to the high potential, the signals N1 and N2 transition to the low potential and the high potential, respectively.

Note that while the first CMOS logic circuit MTC3 and the third CMOS logic circuit MTC5 shift from the sleep mode to the active mode, the sleep mode switching signal SL3 remains at a low potential. Third Embodiment FIG. 8 is a system diagram of a semiconductor integrated logic circuit 103 according to a third embodiment of the present invention.
The semiconductor integrated logic circuit 103 according to the present embodiment includes a power supply circuit with a power cutoff function that achieves both high speed in the active mode and low power consumption in the sleep mode.

This semiconductor integrated logic circuit 103 includes an inverter circuit INV16, a CMOS logic circuit MTC6,
It comprises a signal transmission circuit TSR6 and a sleep mode control circuit (not shown) similar to that of the first embodiment. Inverter circuit INV16 and CMOS logic circuit M
The signal transmission circuit TSR is connected in parallel with TC6.
6 is an inverter circuit INV16 and a CMOS logic circuit MT
It is connected in series with C6.

The CMOS logic circuit MTC6 is composed of a CMOS logic circuit group LGC9 which is composed of a CMOS transistor having a low threshold value and operates at high speed, and one end is directly connected to the high potential power supply VDD, and the other end is connected to the low potential power supply VDD. N-M for a control switch connected in series to the potential side power supply VSS
The low-potential-side power supply VSS via the OS-type transistor TS9
And a low-potential-side power supply VSS is supplied via a low-potential-side pseudo power supply line.

The opening and closing of the control switch n-MOS transistor TS9 is controlled in response to the sleep mode switching inversion signal SLB6 issued from the sleep mode control circuit.

The device parameters of the control switch n-MOS transistor TS9 are set in the semiconductor integrated logic circuit 1
03, so that the sum of the sub-threshold currents leaking from the control switch n-MOS transistor TS9 is smaller than the sum of the sub-threshold currents leaking from the CMOS logic circuit group LGC9, which is a component of No. 03.
Is set.

Therefore, in the active mode, that is, the control switch n-MOS type transistor TS
9, the sleep mode switching inversion signal SLB6 (S
LB6 = “1”) is applied, the control switch n-MOS transistor TS9 is in a conductive state, and the low-potential-side power supply VS is supplied to the CMOS logic circuit group LGC9.
S is supplied.

On the other hand, in the sleep mode, that is, the low potential sleep mode switching inversion signal SLB6 (SLB) is supplied to the control switch n-MOS transistor TS9.
6 = “0”), the control switch n-MOS transistor TS9 is in a cutoff state. Therefore, the supply of the low-potential-side power supply VSS to the CMOS logic circuit group LGC9 is cut off, the sub-threshold leakage current can be suppressed, and the power consumption in the sleep mode can be reduced. Has become.

Since the inverter circuit INV16 is composed of CMOS transistors having device parameters with small sub-threshold leakage current, power is directly supplied from both the high-potential power supply VDD and the low-potential power supply VSS. No sub-threshold leakage current flows.

However, a CMOS transistor having a device parameter with a small subthreshold leakage current has a trade-off, and the operation speed is slow.

Further, a signal transmission circuit TRS is provided between the CMOS logic circuit MTC6 and the inverter circuit INV16.
6 are arranged. This signal transmission circuit TRS6 is composed of a combination of a line dividing circuit CTF6 and a signal fixing circuit CLP6.

The signal fixing circuit CLP6 receives the control signal EQ3
, The signal is fixed and released, and the line disconnecting circuit CTF6 controls signal transmission and cutoff in response to the control signal EQ3 sent via the inverter circuit INV15.

The line disconnecting circuit CTF6 is composed of a make-type switch having a characteristic that the leakage of the subthreshold current and the leakage of the gate tunnel current are small. In order to reduce the sub-threshold leakage current and the gate / tunnel current leakage, the threshold value may be increased, the gate length may be increased, or the gate insulating film may be increased.

The signal fixing circuit CLP6 includes a first inverter circuit INV17 and a second inverter circuit INV18.
And a bistable element including a make-type switch SW disposed between the two inverter circuits.
The signal fixing circuit CLP6 has one node as a connection point between the line dividing circuit CTF6 and the next-stage inverter circuit INV16.

The output of the second inverter circuit INV18, which receives the connection node between the line disconnecting circuit CTF6 and the next-stage inverter circuit INV16, is supplied to the first inverter circuit INV.
17 and the first inverter circuit IN
The output of V17 is fed back to the connection node between the line dividing circuit CTF6 and the next-stage inverter circuit INV16 via the make switch SW responsive to the control signal EQ3.

The operation of the semiconductor integrated logic circuit 103 according to the present embodiment shown in FIG. 8 will be described below with reference to the timing chart shown in FIG.

First, as the first half of the timing chart shown in FIG. 9, a control operation when the CMOS logic circuit MTC6 makes a mode transition from the active mode to the sleep mode will be described.

In the initial state, the CMOS logic circuit MTC6 is in the active mode because the sleep mode switching inversion signal SLB6 (SLB = “1”) of the high potential signal is applied to the control switch n-MOS transistor TS9. Suppose that

At this time, the control signal EQ3 is a low-potential signal (EQ3 = "0"), and the make-type switch forming the line disconnecting circuit CTF6 is turned on, while the make-up switch which is a component of the signal fixing circuit CLP6 is made. Type switch SW
Is in the shut-off state. Therefore, the signal from logic circuit MTC6 to inverter circuit INV16 can be transmitted as usual. The output of the CMOS logic circuit MTC6 in this case is a high potential signal ("1").

Here, the sleep mode switching inversion signal SL
By shifting B6 from the high potential to the low potential, the control switch n-MOS transistor TS9 is shifted to the cutoff state, and the mode of the CMOS logic circuit MTC6 is shifted from the active mode to the sleep mode.

After an arbitrary hold time,
By making the control signal EQ3 transition from the low potential to the high potential, the make switch forming the line dividing circuit CTF6 is turned off, while the make switch SW which is a component of the signal fixing circuit CLP6 is turned on. I do. For this reason, the bistable element including the first inverter circuit INV17 and the second inverter circuit INV18 stores the output signal state of the CMOS logic circuit MTC6 immediately before changing the control signal EQ3 from the low potential to the high potential. The input signal to the inverter circuit INV16 of the stage is fixed.

Therefore, a leakage current path assumed in the CMOS logic circuit MTC6 and the inverter circuit INV16, that is, a leakage current path corresponding to the overlap through current path PS4 which is a problem of the prior art shown in FIG. Can be avoided.

Next, a method of transitioning the CMOS logic circuit MTC6 from the sleep mode to the active mode will be described.

By making the control signal EQ3 transition from the high potential to the low potential, the make switch forming the line disconnecting circuit CTF6 becomes conductive, while the signal fixing circuit C
Make-type switch SW constituting LP6 shifts to the cutoff state. Therefore, the signal N3 from the CMOS logic circuit MTC6 to the inverter circuit INV16 can be transmitted as usual, and the signal state returns to the original state after an arbitrary delay time. That is, when transitioning from the sleep mode to the active mode, the internal state of the active mode existing before the sleep mode is completely reproduced.

After an arbitrary set-up time has elapsed, the sleep mode switching inversion signal SLB6 is changed from a low potential to a high potential, thereby providing the control switch n-
The MOS transistor TS9 is turned on, and C
The mode transition of the MOS logic circuit MTC6 from the sleep mode to the active mode is performed, and the operation is completed.

Next, a method of causing the CMOS logic circuit MTC6 to make a mode transition from the active mode to the sleep mode again will be described.

In the initial state, the sleep mode switching inversion signal SLB6 (SLB = “1”) of the high potential signal is applied to the control switch n-MOS transistor TS9.

At this time, the control signal EQ3 is a low-potential signal (EQ3 = "0"), and the make-type switch forming the line disconnecting circuit CTF6 is turned on, while the make-up switch which is a component of the signal fixing circuit CLP6 is made. Type switch SW
Is in the shut-off state. Therefore, the signal from logic circuit MTC6 to inverter circuit INV16 can be transmitted as usual. The output of the CMOS logic circuit MTC6 in this case is a high potential signal ("1").

The output signal N3 of the CMOS logic circuit MTC6 changes from a high potential ("1") to a low potential ("0") during the active mode.

Here, the sleep mode switching inversion signal SL
By shifting B6 from the high potential to the low potential, the control switch n-MOS transistor TS9 is shifted to the cutoff state, and the mode of the CMOS logic circuit MTC6 is shifted from the active mode to the sleep mode.

Then, after an arbitrary hold time,
By making the control signal EQ3 transition from the low potential to the high potential, the make switch forming the line dividing circuit CTF6 is turned off, while the make switch SW which is a component of the signal fixing circuit CLP6 is turned on. I do. For this reason, the bistable element including the first inverter circuit INV17 and the second inverter circuit INV18 stores the output signal state of the CMOS logic circuit MTC6 immediately before changing the control signal EQ3 from the low potential to the high potential. The input signal to the inverter circuit INV16 of the stage is fixed.

Next, a method of causing the CMOS logic circuit MTC6 to make a mode transition from the sleep mode to the active mode again will be described.

First, by making the control signal EQ3 transition from the high potential to the low potential, the make switch forming the line dividing circuit CTF6 is turned on, and the make switch SW forming the signal fixing circuit CLP6 is turned off. Move to Therefore, the signal N3 from the CMOS logic circuit MTC6 to the inverter circuit INV16 can be transmitted as usual, and after an arbitrary delay time,
Signal N3 initiates a transition from a low potential to a high potential.

Then, after an arbitrary set-up time has elapsed, the sleep mode switching inversion signal SLB6 is changed from the low potential to the high potential, so that the control switch n-
The MOS transistor TS9 is turned on, and C
The mode transition of the MOS logic circuit MTC6 from the sleep mode to the active mode is performed, and the operation is completed.

After an arbitrary removal time has elapsed from the transition of the sleep mode switching inversion signal SLB6 from the low potential to the high potential, the signal N3 transitions from the high potential to the low potential.

[0209]

As described above, according to the present invention, in the sleep mode of the semiconductor integrated logic circuit, not only the subthreshold current but also the gate tunnel current and, consequently, the overlap through current generated as a subsidiary. It is possible to shut off. Therefore, any leakage current in the sleep mode can be cut off, and power consumption in the sleep mode can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated logic circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a control method of the semiconductor integrated logic circuit illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating a control method of the semiconductor integrated logic circuit illustrated in FIG. 1;

FIG. 4 is a flowchart illustrating a control method of the semiconductor integrated logic circuit illustrated in FIG. 1;

FIG. 5 is a flowchart showing a control method of the semiconductor integrated logic circuit shown in FIG. 1;

FIG. 6 is a block diagram of a semiconductor integrated logic circuit according to a second embodiment of the present invention.

7 is a timing chart of signals for controlling the semiconductor integrated logic circuit shown in FIG. 6;

FIG. 8 is a block diagram of a semiconductor integrated logic circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart of signals for controlling the semiconductor integrated logic circuit shown in FIG. 8;

FIG. 10 is a block diagram of a conventional semiconductor integrated logic circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Conventional semiconductor integrated logic circuit INV1-INV8 Inverter circuit 10, 40, 50, 80 p-MOS transistor 20, 30, 60, 70 n-MOS transistor 101 Semiconductor integrated logic circuit according to first embodiment INV9 1 inverter circuit INV12 2nd inverter circuit MTC1 1st CMOS logic circuit MTC2 2nd CMOS logic circuit SMS sleep mode control circuit LGC4 CMOS logic circuit group TS4 n-MOS type transistor LGC5 CMOS logic circuit group TS5 p-MOS type Transistor VDD High-potential-side power supply VSS Low-potential-side power supply SLB3 Sleep mode switching inversion signal SL2 Sleep mode switching signal TRS1 First signal transmission circuit TRS2 Second signal transmission circuit TRS3 Third signal transmission circuit CTF , CTF2, CTF3 Line disconnecting circuit CLP1, CLP2, CLP3 Signal fixing circuit 102 Semiconductor integrated logic circuit according to second embodiment MTC3 First CMOS logic circuit MTC4 Second CMOS logic circuit MTC5 Third CMOS logic circuit LGC6, LGC7, LGC8 CMOS logic circuit group TS6, TS8 n-MOS type transistor TS7 p-MOS type transistor SLB4, SLB5 Sleep mode switching inversion signal SL3 Sleep mode switching signal TRS4 First signal transmission circuit TRS5 Second signal transmission circuit CTF4, CTF5 Line disconnection circuit CLP4, CLP5 Signal fixing circuit 103 Semiconductor integrated logic circuit according to the third embodiment MTC6 CMOS logic circuit LGC9 CMOS logic circuit group TS9 n-MOS transistor INV15 INV16 Inverter circuit INV17 First inverter circuit INV18 Second inverter circuit SLB6 Sleep mode switching inversion signal TRS6 Signal transmission circuit CTF6 Line disconnection circuit CLP6 Signal fixing circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/00

Claims (25)

[Claims] 1. A first CMOS logic circuit group comprising a CMOS transistor having a device parameter with a small sub-threshold leakage current and having a low threshold value and a CMOS transistor having a low threshold value and operating at a high speed. A high-potential-side power supply is supplied directly, and a low-potential-side power supply is supplied via a first transistor, and is connected in parallel with the first and second inverter circuits. And a second CMOS logic circuit group comprising a CMOS transistor having a low threshold value and operating at a high speed. The low-potential-side power supply is directly supplied, and the high-potential-side power supply is And a second power-supply function-supplied second power supply, which is supplied through two transistors and is connected in parallel with the first and second inverter circuits. MOS logic circuit and a semiconductor integrated logic circuit, characterized in that and a sleep mode control circuit which can be an active mode and a sleep mode independently of said first and second transistors. 2. The semiconductor integrated logic circuit according to claim 1, wherein said first transistor is an n-MOS type transistor. 3. The semiconductor integrated logic circuit according to claim 1, wherein said second transistor is a p-MOS type transistor. 4. The device parameter of the first transistor, wherein the sum of sub-threshold currents leaking from the first transistor is smaller than the sum of sub-threshold currents leaking from the first CMOS logic circuit group. The device parameter of the second transistor is such that the sum of the sub-threshold currents leaking from the second transistor is greater than the sum of the sub-threshold currents leaking from the second CMOS logic circuit group. The semiconductor integrated logic circuit according to claim 1, wherein the setting is made smaller. 5. The semiconductor device according to claim 1, further comprising a signal transmission circuit disposed between each of said first and second inverter circuits and each of said first and second CMOS logic circuits. 13. The semiconductor integrated logic circuit according to claim 1. 6. The signal transmission circuit includes a combination of a line disconnection circuit that controls transmission and interruption of a signal and a signal fixing circuit that controls fixing and release of a signal. The semiconductor integrated logic circuit according to claim 5, wherein the semiconductor integrated logic circuit is controlled. 7. A high-potential-side power supply is directly supplied, and a low-potential-side power supply is supplied through a first transistor. The first CMOS logic circuit group includes a CMOS transistor having a low threshold value and operates at high speed. First CMOS supplied by
A second CMOS logic circuit group including a logic circuit and a CMOS transistor having a low threshold value and performing high-speed operation; a low-potential-side power supply is directly supplied; A second CMOS logic circuit to be supplied and a third CMOS logic circuit group comprising a CMOS transistor having a low threshold value and operating at a high speed, and a high-potential-side power supply is directly supplied, and a low-potential-side power supply is A third CMOS logic circuit supplied through a third transistor, a sleep mode control circuit capable of setting the first, second, and third transistors to an active mode and a sleep mode independently of each other; A semiconductor integrated logic circuit comprising: 8. The method according to claim 1, wherein the first and third transistors are n-
8. A MOS type transistor.
4. The semiconductor integrated logic circuit according to claim 1. 9. The semiconductor integrated logic circuit according to claim 7, wherein said second transistor is a p-MOS transistor. 10. A device parameter of the first transistor, wherein the sum of sub-threshold currents leaking from the first transistor is smaller than the sum of sub-threshold currents leaking from the first CMOS logic circuit group. The device parameter of the second transistor is such that the sum of the sub-threshold currents leaking from the second transistor is greater than the sum of the sub-threshold currents leaking from the second CMOS logic circuit group. The device parameter of the first transistor is smaller than the sum of sub-threshold currents leaking from the first CMOS logic circuit group, and the sum of the sub-threshold currents leaking from the first transistor is smaller than the sum of the sub-threshold currents leaking from the first CMOS logic circuit group. Is set to be smaller The semiconductor integrated logic circuit according to any one of claims 7 to 9, characterized in that. 11. The circuit according to claim 7, further comprising first and second signal transmission circuits disposed between each of said first, second and third CMOS logic circuits. The semiconductor integrated logic circuit according to claim 1. 12. Each of the first and second signal transmission circuits includes a combination of a line dividing circuit for controlling transmission and interruption of a signal and a signal fixing circuit for controlling fixing and release of a signal. The semiconductor integrated logic circuit according to claim 11, wherein: 13. The sleep mode control circuit according to claim 7, wherein said first, second and third CMOS logic circuits are independently set to an active mode and a sleep mode, respectively. 13. The semiconductor integrated logic circuit according to claim 12. 14. The circuit according to claim 1, wherein the line dividing circuit in one of the first and second signal transmission circuits comprises a make switch.
3. The semiconductor integrated logic circuit according to 2. 15. The line dividing circuit in the other signal transmission circuit of the first and second signal transmission circuits, wherein the n-M
13. The semiconductor integrated logic circuit according to claim 12, comprising a transfer gate including an OS transistor and a p-MOS transistor. 16. An inverter circuit comprising a CMOS transistor having a device parameter with a small sub-threshold leakage current and a CMOS logic circuit group comprising a CMOS transistor having a low threshold value and operating at a high speed. And a low-potential-side power supply is supplied via a first transistor, and a CMOS logic circuit connected in parallel with the inverter circuit; and a signal connected between the inverter circuit and the CMOS logic circuit. A semiconductor integrated logic circuit, comprising: a transmission circuit; 17. The method according to claim 17, wherein the first transistor is an n-MOS.
17. The semiconductor integrated logic circuit according to claim 16, wherein the semiconductor integrated logic circuit is a type transistor. 18. The device parameter of the first transistor is set such that the sum of sub-threshold currents leaking from the first transistor is smaller than the sum of sub-threshold currents leaking from the CMOS logic circuit group. 2. The method according to claim 1, wherein
18. The semiconductor integrated logic circuit according to 6 or 17. 19. The signal transmission circuit according to claim 1, wherein the signal transmission circuit comprises a combination of a line dividing circuit for controlling transmission and interruption of the signal and a signal fixing circuit for controlling fixing and release of the signal. 19. The semiconductor integrated logic circuit according to any one of 16 to 18. 20. The semiconductor integrated logic circuit according to claim 19, wherein said line dividing circuit comprises a make switch. 21. The signal fixing circuit includes a bistable element having a first inverter circuit and a second inverter circuit, and the bistable element has a connection point between the line dividing circuit and the inverter circuit. The second inverter circuit receives a connection node between the line dividing circuit and the inverter circuit as an input, an output of the second inverter circuit becomes an input of the first inverter circuit, and 20. The semiconductor integrated logic circuit according to claim 19, wherein an output of the inverter circuit is fed back to a connection node between the line dividing circuit and the inverter circuit. 22. The sleep mode switching inversion signal applied from the sleep mode control circuit to the first transistor is changed from a high potential signal to a low potential signal, so that the first transistor is turned off. Supplying power to a first CMOS logic circuit group and blocking leakage of a sub-threshold current from the first CMOS logic circuit group; and transmitting the power to the first CMOS logic circuit from the first inverter circuit. Dividing the signal that has been output, fixing the signal output to the first CMOS logic circuit group, and transmitting the signal from the first CMOS logic circuit to the second CMOS logic circuit. 7. The method according to claim 1, further comprising: dividing the output of the second CMOS logic circuit group; and fixing the signal output to the second CMOS logic circuit group. Method of controlling the semiconductor integrated logic circuit according to an item. 23. A step of releasing the fixation of a signal applied to the first CMOS logic circuit, and a state in which a path for transmitting a signal from the first inverter circuit to the first CMOS logic circuit is disconnected. From the first CMOS logic circuit to the second CMOS logic circuit, and from the first CMOS logic circuit to the second CMOS logic circuit. Shifting the path to be switched from the disconnected state to the conductive state, and changing the sleep mode switching inversion signal applied from the sleep mode control circuit to the first CMOS logic circuit from a low potential signal to a high potential signal. First
7. The method of controlling a semiconductor integrated logic circuit according to claim 1, further comprising: turning on a transistor of the first embodiment, and starting power supply to the first CMOS logic circuit group. 8. 24. The first and second transistors by transitioning a sleep mode switching inversion signal applied from the sleep mode control circuit to the first and second transistors from a high potential signal to a low potential signal. Turning off the power supply to the first and second CMOS logic circuit groups and blocking leakage of subthreshold current from the first and second CMOS logic circuit groups; and A signal transmitted from the circuit to the first CMOS logic circuit, a signal transmitted from the first CMOS logic circuit to the second CMOS logic circuit, and a signal transmitted from the second CMOS logic circuit to the first CMOS logic circuit. Dividing the signal transmitted to the second inverter circuit, and fixing the signal output to the first and second CMOS logic circuit groups. Comprising the steps that, the method of controlling the semiconductor integrated logic circuit according to any one of claims 1 to 6. 25. A process for releasing the fixation of a signal applied to the first and second CMOS logic circuits, and a path for transmitting a signal from the first inverter circuit to the first CMOS logic circuit. A path for transmitting a signal to the first CMOS logic circuit to the second CMOS logic circuit, and a path for transmitting a signal from the second CMOS logic circuit to the second inverter circuit are switched from a disconnected state. Transitioning to the first and second states from the sleep mode control circuit.
By changing the sleep mode switching inversion signal applied to the MOS logic circuit from a low potential signal to a high potential signal,
7. The method according to claim 1, further comprising: turning on the first and second transistors to start supplying power to the first and second CMOS logic circuits. 8. A method for controlling a semiconductor integrated logic circuit.