TWI381644B - Circuit for detecting clock and apparatus for porviding clock - Google Patents
Circuit for detecting clock and apparatus for porviding clock Download PDFInfo
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本發明涉及一種時脈偵測電路,特別是涉及一種用來偵測時脈信號是否正常運作的時脈偵測電路。The present invention relates to a clock detection circuit, and more particularly to a clock detection circuit for detecting whether a clock signal is operating normally.
圖1繪示為習知的一種共用時脈源的系統方塊圖。請參照圖1,習知共用時脈源系統100中,包括裝置102、104、106和108,其共同耦接至一時脈源110。藉此,時脈源110就可以同時供給裝置102、104、106和108所需的時脈信號,以使其能夠正常運作。然而,萬一任一裝置102、104、106和108無法接收時脈源110之時脈信號時,則這些裝置就無法正常運作,僅可使用本身之時脈頻率而無法與其他裝置溝通。FIG. 1 is a block diagram of a conventional shared clock source. Referring to FIG. 1 , a conventional shared clock source system 100 includes devices 102 , 104 , 106 , and 108 that are commonly coupled to a clock source 110 . Thereby, the clock source 110 can simultaneously supply the clock signals required by the devices 102, 104, 106 and 108 to enable it to operate normally. However, in the event that any of the devices 102, 104, 106, and 108 are unable to receive the clock signal of the clock source 110, then the devices will not function properly and only use their own clock frequency to communicate with other devices.
本發明提供一種時脈偵測電路,可以偵測一時脈源是否正常供應一預設時脈信號。The invention provides a clock detection circuit capable of detecting whether a pulse source is normally supplied with a preset clock signal.
本發明提供一種時脈供應裝置,可以確保一電子裝置在外接的時脈源無法提供時脈信號時,仍可以正常的運作。The invention provides a clock supply device, which can ensure that an electronic device can still operate normally when an external clock source cannot provide a clock signal.
一種時脈偵測電路,包括多個第一傳輸元件、多個第一互斥或閘和一第一及閘。其中,每一第一傳輸元件都可以耦接上一級第一傳輸元件,以接收其輸出的資料,並且依據一本地時脈信號,而將所接收到的資料傳送至下一級第一傳輸元件的輸入端。另外,第一個第一傳輸元件的輸入端,則可以耦接至時脈源,以接收預設時脈信號,而此預設時脈信號的頻率小於一本地時脈信號的頻率。此外,第k個第一互斥或閘的第一輸入端和第二輸入端,可以分別耦接第k個第一傳輸元件和第k+1個第一傳輸元件的輸出端,而k為大於0且小於所述多個第一傳輸元件總數的整數。A clock detection circuit includes a plurality of first transmission elements, a plurality of first mutually exclusive gates and a first AND gate. Each of the first transmission elements may be coupled to the first transmission element of the first stage to receive the data of the output, and transmit the received data to the first transmission element of the next stage according to a local clock signal. Input. In addition, the input end of the first first transmission component can be coupled to the clock source to receive the preset clock signal, and the frequency of the preset clock signal is less than the frequency of a local clock signal. In addition, the first input end and the second input end of the kth first mutex or gate may be respectively coupled to the output ends of the kth first transmission element and the k+1th first transmission element, and k is An integer greater than 0 and less than the total number of the plurality of first transmission elements.
在本發明之一實施例中,上述的第一傳輸元件可以是多個第一D型正反器,分別具有一時脈端,可以接收本地時脈信號。In an embodiment of the invention, the first transmission component may be a plurality of first D-type flip-flops each having a clock terminal for receiving a local clock signal.
另外,本發明所提供的時脈偵測電路更包括多個多個第二D型正反器,分別具有一時脈端,可以接收本地時脈信號。而這些第二D型正反器可以與第一D型正反器分別利用本地時脈信號的負緣和正緣來觸發。本發明的時脈偵測電路還包括多個第二互斥或閘、一第二及閘和一或閘。其中,每一第二D型正反器也可以耦接上一級第二D型正反器的輸出端,以接收其輸出的資料,並且依據本地時脈信號,而將接收到的資料傳送至下一級第二D型正反器的輸入端。此外,第一個第二D型正反器的輸入端也可以耦接所述時脈源,以接收所述預設時脈信號,而第k個第二D型正反器和第k+1個第二D型正反器的輸出端則分別耦接第k個第二互斥或閘的第一輸入端和第二輸入端。另外,所有互斥或們的輸出都可以耦接至第二及閘,而第二及閘的輸出則可以和第一及閘分別耦接至或閘的輸入端。In addition, the clock detection circuit provided by the present invention further includes a plurality of second D-type flip-flops each having a clock terminal for receiving a local clock signal. These second D-type flip-flops can be triggered with the first D-type flip-flops using the negative and positive edges of the local clock signal, respectively. The clock detection circuit of the present invention further includes a plurality of second mutually exclusive gates, a second gate and a gate. Each second D-type flip-flop can also be coupled to the output of the second-stage D-type flip-flop of the previous stage to receive the data of the output, and transmit the received data to the local clock signal according to the local clock signal. The input of the second D-type flip-flop of the next stage. In addition, the input end of the first second D-type flip-flop can also be coupled to the clock source to receive the preset clock signal, and the k-th second D-type flip-flop and the k+ The output ends of the one second D-type flip-flop are respectively coupled to the first input end and the second input end of the kth second mutex or gate. In addition, all of the mutually exclusive outputs may be coupled to the second AND gate, and the output of the second AND gate may be coupled to the input of the OR gate respectively.
從另一觀點來看,本發明也提供一種時脈供應裝置,可以提供一工作時脈信號給一電子裝置。本發明的時脈供應裝置包括多個第一傳輸元件、多個第一互斥或閘、一第一及閘和一多工器。其中,每一第一傳輸元件都可以耦接上一級第一傳輸元件,以接收其輸出的資料,並且依據一本地時脈信號,而將所接收到的資料傳送至下一級第一傳輸元件的輸入端。另外,第一個第一傳輸元件的輸入端,則可以耦接至時脈源,以接收預設時脈信號,而此預設時脈信號的頻率小於所述本地時脈信號的頻率。此外,第k個第一互斥或閘的第一輸入端和第二輸入端,可以分別耦接第k個第一傳輸元件和第k+1個第一傳輸元件的輸出端,而k為大於0且小於所述多個第一傳輸元件總數的整數。而多工器則可以耦接外部時脈源和本地時脈源,並且依據第一及閘的輸出,而選擇外部時脈源和本地時脈源二者其中之一的當作工作時脈信號,以輸出給電子裝置。From another point of view, the present invention also provides a clock supply device that can provide a working clock signal to an electronic device. The clock supply device of the present invention includes a plurality of first transmission elements, a plurality of first mutually exclusive gates, a first gate and a multiplexer. Each of the first transmission elements may be coupled to the first transmission element of the first stage to receive the data of the output, and transmit the received data to the first transmission element of the next stage according to a local clock signal. Input. In addition, the input end of the first first transmission component can be coupled to the clock source to receive the preset clock signal, and the frequency of the preset clock signal is less than the frequency of the local clock signal. In addition, the first input end and the second input end of the kth first mutex or gate may be respectively coupled to the output ends of the kth first transmission element and the k+1th first transmission element, and k is An integer greater than 0 and less than the total number of the plurality of first transmission elements. The multiplexer can be coupled to the external clock source and the local clock source, and select one of the external clock source and the local clock source as the working clock signal according to the output of the first gate. To output to an electronic device.
由於本發明是利用或閘來偵測時脈源態樣(Pattern),因此本發明可以精確地偵測時脈源是否正常運作。另外,本發明所提供的時脈供應裝置還配置有多工器,以分別耦接本地時脈源和外部時脈源。藉此,本發明可以在外部時脈源無法正常運作時,利用本地時脈源來供應電子裝置。Since the present invention utilizes a gate or a gate to detect a clock source pattern, the present invention can accurately detect whether the clock source is functioning properly. In addition, the clock supply device provided by the present invention is further configured with a multiplexer to respectively couple the local clock source and the external clock source. Thereby, the present invention can utilize the local clock source to supply the electronic device when the external clock source is not operating normally.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2繪示為依照本發明之一較佳實施例的一種時脈供應裝置的電路方塊圖。請參照圖2,本實施例所提供的時脈供應裝置200,包括時脈偵測電路202、多工器204和本地時脈源。時脈偵測電路202可以耦接多工器204和本地時脈源206。此外,時脈偵測電路202還可以耦接外部時脈源212。類似地,多工器204的輸入端也可以耦接本地時脈源206和外部時脈源212,而其輸出端則可以耦接一電子裝置214。2 is a circuit block diagram of a clock supply device in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the clock supply device 200 provided in this embodiment includes a clock detection circuit 202, a multiplexer 204, and a local clock source. The clock detection circuit 202 can couple the multiplexer 204 and the local clock source 206. In addition, the clock detection circuit 202 can also be coupled to the external clock source 212. Similarly, the input of the multiplexer 204 can also be coupled to the local clock source 206 and the external clock source 212, and the output of the multiplexer 204 can be coupled to an electronic device 214.
本地時脈源206可以輸出本地時脈信號CLK1及採樣時脈信號CLK3,外部時脈源212可以輸出外部時脈信號CLK2,給時脈偵測電路202和多工器204。在本實施例中,採樣時脈信號CLK3的頻率高於外部時脈信號CLK2的頻率。換句話說,採樣時脈信號CLK3的週期小於外部時脈信號CLK2的週期。藉此,時脈偵測電路202就可以依據採樣時脈信號CLK3,而對外部時脈信號CLK2進行取樣,以偵測時脈供應裝置200是否接收正常外部時脈信號CLK2。而在本實施例中,本地時脈信號CLK1之頻率為外部時脈信號CLK2頻率之兩倍,本地時脈源206例如將本地時脈信號CLK1經過除頻以產生採樣時脈信號CLK3。The local clock source 206 can output the local clock signal CLK1 and the sampling clock signal CLK3, and the external clock source 212 can output the external clock signal CLK2 to the clock detection circuit 202 and the multiplexer 204. In the present embodiment, the frequency of the sampling clock signal CLK3 is higher than the frequency of the external clock signal CLK2. In other words, the period of the sampling clock signal CLK3 is smaller than the period of the external clock signal CLK2. Thereby, the clock detection circuit 202 can sample the external clock signal CLK2 according to the sampling clock signal CLK3 to detect whether the clock supply device 200 receives the normal external clock signal CLK2. In the present embodiment, the frequency of the local clock signal CLK1 is twice the frequency of the external clock signal CLK2, and the local clock source 206, for example, divides the local clock signal CLK1 to generate the sampling clock signal CLK3.
時脈偵測電路202可以依據外部時脈信號CLK2的狀態而輸出一選擇信號SEL給多工器204。藉此,多工器204就可以依據選擇信號SEL,而選擇外部時脈信號CLK2或採樣時脈信號CLK3當作工作時脈信號OUT_CLK給電子裝置214。即時脈偵測電路所接收之採樣時脈信號及外部時脈源,例如分別16MHz及8MHz,而最後提供至電子裝置之工作時脈信號非取上述之本地時脈信號,而是取1/2倍頻之本地時脈信號及外部時脈源皆為8MHz提供至電子裝置使用即1/2倍頻之本地時脈信號及外部時脈源之頻率相同,僅相位不同。The clock detection circuit 202 can output a selection signal SEL to the multiplexer 204 according to the state of the external clock signal CLK2. Thereby, the multiplexer 204 can select the external clock signal CLK2 or the sampling clock signal CLK3 as the working clock signal OUT_CLK to the electronic device 214 according to the selection signal SEL. The sampling clock signal and the external clock source received by the real-time pulse detecting circuit, for example, 16 MHz and 8 MHz, respectively, and the working clock signal finally provided to the electronic device does not take the local clock signal, but takes 1/2 The local clock signal of the multiplier and the external clock source are both provided to the electronic device using the local clock signal of 1/2 multiplier and the external clock source at the same frequency, only the phase is different.
圖3繪示為依照本發明之一較佳實施例的一種時脈偵測電路的電路圖。請參照圖3,時脈偵測電路202可以包括多個第一傳輸元件,例如302、304和306。每一第一傳輸元件302、304和306都可以具有一輸入端D和輸出端Q。其中,各級第一傳輸元件的輸入端D可以耦接至上一級傳輸元件的輸出端Q,而第一個第一傳輸元件302的輸入端D則接收外部時脈信號CLK2。3 is a circuit diagram of a clock detection circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the clock detection circuit 202 can include a plurality of first transmission elements, such as 302, 304, and 306. Each of the first transmission elements 302, 304, and 306 can have an input terminal D and an output terminal Q. The input terminal D of the first transmission element of each stage may be coupled to the output terminal Q of the upper transmission element, and the input D of the first first transmission element 302 receives the external clock signal CLK2.
另外,時脈偵測電路202還可以包括多個第一互斥或閘,例如308和310,以及第一及閘312。其中,第k個第一互斥或閘的輸入端分別耦接第k個傳輸元件和第k+1個傳輸元件的輸出端Q。其中,k為大於0而小於傳輸元件總數的正整數。例如,第一個互斥或閘308的輸入端,則分別耦接第一個傳輸元件302的輸出端Q和第二個傳輸元件304的輸出端Q。另外,第一及閘312的輸入端分別接收互斥或閘308和310的輸入端。In addition, the clock detection circuit 202 can also include a plurality of first mutually exclusive gates, such as 308 and 310, and a first AND gate 312. The input ends of the kth first mutex or gate are respectively coupled to the output terminal Q of the kth transmission element and the k+1th transmission element. Where k is a positive integer greater than 0 and less than the total number of transmission elements. For example, the input of the first mutex or gate 308 is coupled to the output Q of the first transmission element 302 and the output Q of the second transmission element 304, respectively. Additionally, the inputs of the first AND gate 312 receive the inputs of the mutually exclusive or gates 308 and 310, respectively.
在本實施例中,每一第一傳輸元件302、304和306可以利用D型正反器來實現,然而本發明並不以此為限。另外,每一D型正反器302、304和306都分別具有一時脈端C,並且分別接收採樣時脈信號CLK3。藉此,各級D型正反器可以依據採樣時脈信號CLK3的狀態,而將輸入端D所接收到的信號,從輸出端Q傳送至下一級傳輸元件的輸入端D。在本實施例中,D型正反器302、304和306為正緣觸發的正反器。In this embodiment, each of the first transmission elements 302, 304, and 306 can be implemented by using a D-type flip-flop, but the invention is not limited thereto. In addition, each of the D-type flip-flops 302, 304, and 306 has a clock terminal C, and receives the sampling clock signal CLK3, respectively. Thereby, the D-type flip-flops of each stage can transmit the signal received by the input terminal D from the output terminal Q to the input terminal D of the next-stage transmission component according to the state of the sampling clock signal CLK3. In the present embodiment, the D-type flip-flops 302, 304, and 306 are positive-edge-triggered flip-flops.
另外,時脈偵測電路202還可以包括處理器322和警示模組324。其中,處理器322可以依據選擇信號SEL的狀態而控制警示模組324是否產生一警示資訊。In addition, the clock detection circuit 202 can also include a processor 322 and a warning module 324. The processor 322 can control whether the warning module 324 generates an alert information according to the state of the selection signal SEL.
圖4繪示為依照本發明第一實施例的一種採樣時脈信號與外部時脈信號的時序圖。請合併參照圖3和圖4,在本實施中,假設採樣時脈信號CLK3是外部時脈信號CLK2的兩倍頻。另外,假設在時間t0時,採樣時脈信號CLK3和外部時脈信號CLK2的狀態都為低位元,並且被分別送至第一D型正反器302的時脈端C和輸入端D。然而,由於第一D型正反器302為正緣觸發,因此外部時脈信號CLK2的狀態會被拴鎖至第一D型正反器302的輸入端D。4 is a timing diagram of a sample clock signal and an external clock signal in accordance with a first embodiment of the present invention. Referring to FIG. 3 and FIG. 4 together, in the present embodiment, it is assumed that the sampling clock signal CLK3 is twice the frequency of the external clock signal CLK2. In addition, it is assumed that at time t0, the states of the sampling clock signal CLK3 and the external clock signal CLK2 are both low bits, and are respectively sent to the clock terminal C and the input terminal D of the first D-type flip-flop 302. However, since the first D-type flip-flop 302 is a positive edge trigger, the state of the external clock signal CLK2 is latched to the input terminal D of the first D-type flip-flop 302.
而在時間t1時,採樣時脈信號CLK3從低位元元切換至高位,而在本地時脈信號CLK2上造成一正緣狀態,以致於第一D型正反器302將輸入端D的狀態從輸出端Q輸出至第一D型正反器304的輸入端D。此時,第一D型正反器302的輸出端Q的狀態為低位元,而第一D型正反器304和306輸出端Q的狀態為未知。接著,在t2時,外部時脈信號CLK2從低位元元切換至高位,而採樣時脈信號CLK3則是從高位切換回低位元元。此時,第一D型正反器302和304都不會有動作。At time t1, the sampling clock signal CLK3 is switched from the lower bit to the upper bit, and a positive edge state is caused on the local clock signal CLK2, so that the first D-type flip-flop 302 takes the state of the input D from The output terminal Q is output to the input terminal D of the first D-type flip-flop 304. At this time, the state of the output terminal Q of the first D-type flip-flop 302 is a low bit, and the state of the output terminal Q of the first D-type flip-flops 304 and 306 is unknown. Next, at t2, the external clock signal CLK2 is switched from the lower bit to the upper bit, and the sampling clock signal CLK3 is switched from the upper bit to the lower bit. At this time, the first D-type flip-flops 302 and 304 do not operate.
而在t3時,採樣時脈信號CLK3又從低位元元切換至高位,致使第一D型正反器302和304會分別將輸入端的狀態傳送至下一級的第一D型正反器。此時,第一D型正反器302和304的輸出端Q的狀態分別為高位和低位元元,而第一D型正反器306輸出端Q的狀態為未知。而在t4時,採樣時脈信號CLK3和外部時脈信號CLK2都從高位切回低位元元,因此第一D型正反器302、304和306都不會有動作。At t3, the sampling clock signal CLK3 is switched from the lower bit to the upper bit again, so that the first D-type flip-flops 302 and 304 respectively transfer the state of the input to the first D-type flip-flop of the next stage. At this time, the states of the output terminals Q of the first D-type flip-flops 302 and 304 are high-order and low-order elements, respectively, and the state of the output terminal Q of the first D-type flip-flop 306 is unknown. At t4, both the sampling clock signal CLK3 and the external clock signal CLK2 are switched back from the high bit to the lower bit, so that the first D-type flip-flops 302, 304, and 306 do not operate.
接著,在t5時,採樣時脈信號CLK3又從低位元元切換至高位,此時第一D型正反器302、304和306都分別將輸入端D的狀態從輸出端Q輸出。此時,第一D型正反器302、304和306輸出端Q的狀態分別為低位元元、高位和低位元,也代表互斥或閘308和310的每一輸入端都是不同的狀態。因此,互斥或閘308和310都的輸入端都是高位的狀態,以致於及閘的狀態312也是高位的狀態。此時,選擇信號SEL就可以是高位的狀態。藉此,圖2中的多工器204就可選擇外部時脈信號CLK2當作工作時脈信號OUT_CLK而送給電子裝置214。另外,處理器322也會因為選擇信號SEL為高位狀態,而使警示模組324在禁能的狀態。Next, at t5, the sampling clock signal CLK3 is switched from the lower bit to the upper bit again, at which time the first D-type flip-flops 302, 304 and 306 respectively output the state of the input terminal D from the output terminal Q. At this time, the states of the output terminals Q of the first D-type flip-flops 302, 304, and 306 are low-order elements, high-order bits, and low-order elements, respectively, and also represent different states of each of the mutually exclusive or gates 308 and 310. . Therefore, the inputs of the mutex or gates 308 and 310 are both high, so that the state 312 of the gate is also a high state. At this time, the selection signal SEL may be in a high state. Thereby, the multiplexer 204 in FIG. 2 can select the external clock signal CLK2 to be sent to the electronic device 214 as the working clock signal OUT_CLK. In addition, the processor 322 also causes the alert module 324 to be in an disabled state because the selection signal SEL is in a high state.
相對地,若是外部時脈信號CLK2失能時,則互斥或閘308和310至少有其中之一的輸出為低位元的狀態,導致及閘312的輸出也會是低位元的狀態。此時,選擇信號SEL的狀態也會連帶是低位,使得多工器204選擇本地時脈信號CLK1當作工作時脈信號OUT_CLK送給電子裝置214。藉此,電子裝置214並不會因為外部時脈源212無法正常運作而連帶著停擺。另一方面,處理器322也可以依據選擇訊號SEL在低位,而控制警示模組324產生警示資訊告知使用者。在本實施例中,警示模組324所產生的警示資訊可以是聲音或是亮光。In contrast, if the external clock signal CLK2 is disabled, the mutex or the gates 308 and 310 have at least one of the outputs being in the low bit state, and the output of the AND gate 312 is also in the low bit state. At this time, the state of the selection signal SEL is also associated with the low bit, so that the multiplexer 204 selects the local clock signal CLK1 as the working clock signal OUT_CLK to be sent to the electronic device 214. Thereby, the electronic device 214 does not have a stoppage due to the external clock source 212 not functioning properly. On the other hand, the processor 322 can also control the alert module 324 to generate a warning message to inform the user according to the selection signal SEL being in the low position. In this embodiment, the warning information generated by the warning module 324 may be sound or bright light.
圖5則繪示為依照本發明第二實施例的一種本地時脈信號與外部時脈信號的時序圖。請合併參照圖5,在一些實施例中,採樣時脈信號CLK3可能會因為雜訊或是抖動的影響,而導致時脈偵測電路202錯誤的運作。例如,在時間t6和t7,採樣時脈信號CLK3都是處於正緣的狀態,但是所取樣到的外部時脈信號CLK2則都是高位的狀態。這代表互斥或閘308和310二者其中之一的輸入會是相同,導致及閘312的輸出為低位。此時,選擇信號SEL連帶會產生錯誤的狀態。FIG. 5 is a timing diagram of a local clock signal and an external clock signal according to a second embodiment of the present invention. Referring to FIG. 5 in combination, in some embodiments, the sampling clock signal CLK3 may cause the clock detection circuit 202 to operate incorrectly due to noise or jitter. For example, at times t6 and t7, the sampling clock signal CLK3 is in a positive edge state, but the sampled external clock signal CLK2 is in a high state. This represents that the inputs of one of the mutex or gates 308 and 310 will be the same, resulting in the output of the AND gate 312 being low. At this time, the selection signal SEL is associated with an error state.
請繼續參照圖3,為確保選擇信號SEL的狀態維持正確,在一些實施例中,時脈偵測電路202更包括多個第二傳輸元件,例如332、334和336。這些傳輸元件332、334和336也可以利用D型正反器來實現,並且耦接方式也可以參照傳輸元件302、304和306。不同的是,在本實施例中,這些第二D型正反器302、304和306為負緣觸發。With continued reference to FIG. 3, to ensure that the state of the select signal SEL remains correct, in some embodiments, the clock detect circuit 202 further includes a plurality of second transmission elements, such as 332, 334, and 336. These transmission elements 332, 334 and 336 can also be implemented with D-type flip-flops, and the coupling means can also refer to transmission elements 302, 304 and 306. The difference is that in the present embodiment, these second D-type flip-flops 302, 304 and 306 are triggered by a negative edge.
相對應地,時脈偵測電路202還可以包括多個第二互斥或閘,例如338和340,以及第二及閘342。其中,第二互斥或閘338、340、以及第二及閘342的耦接關係,可以參照第一互斥或閘308、310、以及第一及閘312,本發明不再為文贅述。另外,或閘344的輸入端則分別耦接及閘312和342的輸入端。Correspondingly, the clock detection circuit 202 can also include a plurality of second mutually exclusive gates, such as 338 and 340, and a second AND gate 342. For the coupling relationship of the second mutually exclusive or gates 338 and 340 and the second gate 342, reference may be made to the first mutually exclusive gates 308 and 310 and the first gate 312, and the present invention is not described again. In addition, the input terminals of the OR gates 344 are coupled to the inputs of the gates 312 and 342, respectively.
由於第一D型正反器302、304和306,以及第二D型正反器332、334和336分別為正緣觸發和負緣觸發。因此,即便採樣時脈信號CLK3因為雜訊或是抖動而造成相位或是時間週期漂動,然而時脈偵測電路202還是可以對外部時脈信號CLK2進行正確的取樣。例如,在圖5中,雖然第一D型正反器302、304和306會取樣錯誤,但是第二D型正反器332、334和336會因為是負緣觸發而仍然可以取樣到正確的態樣。而在本實施例中,只要及閘312和342二者其中之一的輸出狀態為正確,或閘344就可以輸出正確的選擇信號SEL。藉此,就可以確保選擇信號SEL保持在正確的狀態。Since the first D-type flip-flops 302, 304, and 306, and the second D-type flip-flops 332, 334, and 336 are the positive edge trigger and the negative edge trigger, respectively. Therefore, even if the sampling clock signal CLK3 causes phase or time period wander due to noise or jitter, the clock detecting circuit 202 can correctly sample the external clock signal CLK2. For example, in FIG. 5, although the first D-type flip-flops 302, 304, and 306 may sample errors, the second D-type flip-flops 332, 334, and 336 may still be sampled correctly because they are negative-edge triggers. Aspect. In the present embodiment, as long as the output state of one of the gates 312 and 342 is correct, or the gate 344 can output the correct selection signal SEL. Thereby, it is ensured that the selection signal SEL is maintained in the correct state.
圖6繪示為依照本發明另一實施例的一種時脈供應裝置的電路圖。請參照圖6,本實施例與圖3的實施例不同處在於,本實施例利用D型正反器602、604和606來取代D型正反器332、334和336當作第二傳輸元件。其中,D型正反器602、604和606可以是正緣觸發。另外,在本實施例中,時脈偵測電路202還可以包括反向器608,其輸入端可以耦接D型正反器302的時脈端,以接收採樣時脈信號CLK3,而反向器608的輸出端則可以耦接D型正反器602、604和606的時脈端C。藉此,本實施例所提供的時脈偵測電路202也可以與圖3中的時脈偵測電路202具有相同的功能。6 is a circuit diagram of a clock supply device in accordance with another embodiment of the present invention. Referring to FIG. 6, the difference between this embodiment and the embodiment of FIG. 3 is that the present embodiment uses D-type flip-flops 602, 604 and 606 instead of D-type flip-flops 332, 334 and 336 as the second transmission element. . Wherein, the D-type flip-flops 602, 604, and 606 can be positive-edge triggers. In addition, in this embodiment, the clock detection circuit 202 can further include an inverter 608, and the input end of the clock detection circuit 202 can be coupled to the clock terminal of the D-type flip-flop 302 to receive the sampling clock signal CLK3. The output of the 608 can then be coupled to the clock terminal C of the D-type flip-flops 602, 604 and 606. Therefore, the clock detection circuit 202 provided in this embodiment can also have the same function as the clock detection circuit 202 in FIG.
綜上所述,由於發明例可以利用D型正反器對外部時脈信號取樣,並且利用互斥或閘來進行樣態的判斷。因此,本發明可以精確地偵測外部時脈信號的狀態。另外,本發明還可以包括多工器,並且可以依據選擇信號而選擇外部時脈信號或是本地時脈信號當作工作時脈信號。因此,本發明可以讓電子裝置在外部時脈信號施能時仍然可以正常運作。In summary, since the invention example can use the D-type flip-flop to sample the external clock signal, and use the mutual exclusion or gate to judge the state. Therefore, the present invention can accurately detect the state of the external clock signal. In addition, the present invention may further include a multiplexer, and may select an external clock signal or a local clock signal as the working clock signal according to the selection signal. Therefore, the present invention allows the electronic device to still operate normally when the external clock signal is energized.
此外,在本發明中由於可以配置有正緣觸發和負緣觸發的D型正反器,因此本發明可以排除本地時脈信號因為雜訊或是抖動而造成的錯誤動作。In addition, in the present invention, since the D-type flip-flops with the positive edge trigger and the negative edge trigger can be configured, the present invention can eliminate the erroneous action of the local clock signal due to noise or jitter.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
102、104、106、108...裝置102, 104, 106, 108. . . Device
110...時脈源110. . . Clock source
200...時脈供應裝置200. . . Clock supply device
202...時脈偵測電路202. . . Clock detection circuit
204...多工器204. . . Multiplexer
206...本地時脈源206. . . Local clock source
212...外部時脈源212. . . External clock source
214...電子裝置214. . . Electronic device
302、304、306、332、334、336、602、604、606...D型正反器302, 304, 306, 332, 334, 336, 602, 604, 606. . . D-type flip-flop
308、310、338、340...互斥或閘308, 310, 338, 340. . . Mutual exclusion or gate
312、342...及閘312, 342. . . Gate
322...處理器322. . . processor
324...警示模組324. . . Warning module
C...時脈端C. . . Clock end
CLK1...本地時脈信號CLK1. . . Local clock signal
CLK2...外部時脈信號CLK2. . . External clock signal
D...輸入端D. . . Input
SEL...選擇信號SEL. . . Selection signal
Q...輸出端Q. . . Output
圖1繪示為習知的一種共用時脈源的系統方塊圖。FIG. 1 is a block diagram of a conventional shared clock source.
圖2繪示為依照本發明之一較佳實施例的一種時脈供應裝置的電路方塊圖。2 is a circuit block diagram of a clock supply device in accordance with a preferred embodiment of the present invention.
圖3繪示為依照本發明之一較佳實施例的一種時脈偵測電路的電路圖。3 is a circuit diagram of a clock detection circuit in accordance with a preferred embodiment of the present invention.
圖4繪示為依照本發明第一實施例的一種本地時脈信號與外部時脈信號的時序圖。4 is a timing diagram of a local clock signal and an external clock signal in accordance with a first embodiment of the present invention.
圖5繪示為依照本發明第二實施例的一種本地時脈信號與外部時脈信號的時序圖。FIG. 5 is a timing diagram of a local clock signal and an external clock signal according to a second embodiment of the present invention.
圖6繪示為依照本發明另一實施例的一種時脈供應裝置的電路圖。6 is a circuit diagram of a clock supply device in accordance with another embodiment of the present invention.
202...時脈偵測電路202. . . Clock detection circuit
302、304、306、602、604、606...D型正反器302, 304, 306, 602, 604, 606. . . D-type flip-flop
308、310、338、340...互斥或閘308, 310, 338, 340. . . Mutual exclusion or gate
312、342...及閘312, 342. . . Gate
322...處理器322. . . processor
324...警示模組324. . . Warning module
C...時脈端C. . . Clock end
CLK1...本地時脈信號CLK1. . . Local clock signal
CLK2...外部時脈信號CLK2. . . External clock signal
D...輸入端D. . . Input
SEL...選擇信號SEL. . . Selection signal
Q...輸出端Q. . . Output
Claims (12)
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US5642380A (en) * | 1992-06-03 | 1997-06-24 | Data Radio Inc. | Data communication system and modem therefor |
US6002733A (en) * | 1995-12-23 | 1999-12-14 | Lg Semicon Co., Ltd. | Universal asynchronous receiver and transmitter |
TW414893B (en) * | 1996-12-31 | 2000-12-11 | Hyundai Electronics Ind | Device and method for automatically setting status of dynamic random access memory through control of clock enable signal |
US7042250B1 (en) * | 2004-11-03 | 2006-05-09 | Texas Instruments Incorporated | Synchronization of clock signals in a multi-clock domain |
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