TWI381644B - Circuit for detecting clock and apparatus for porviding clock - Google Patents

Description

Clock detection circuit and clock supply device

The present invention relates to a clock detection circuit, and more particularly to a clock detection circuit for detecting whether a clock signal is operating normally.

FIG. 1 is a block diagram of a conventional shared clock source. Referring to FIG. 1 , a conventional shared clock source system 100 includes devices 102 , 104 , 106 , and 108 that are commonly coupled to a clock source 110 . Thereby, the clock source 110 can simultaneously supply the clock signals required by the devices 102, 104, 106 and 108 to enable it to operate normally. However, in the event that any of the devices 102, 104, 106, and 108 are unable to receive the clock signal of the clock source 110, then the devices will not function properly and only use their own clock frequency to communicate with other devices.

The invention provides a clock detection circuit capable of detecting whether a pulse source is normally supplied with a preset clock signal.

The invention provides a clock supply device, which can ensure that an electronic device can still operate normally when an external clock source cannot provide a clock signal.

A clock detection circuit includes a plurality of first transmission elements, a plurality of first mutually exclusive gates and a first AND gate. Each of the first transmission elements may be coupled to the first transmission element of the first stage to receive the data of the output, and transmit the received data to the first transmission element of the next stage according to a local clock signal. Input. In addition, the input end of the first first transmission component can be coupled to the clock source to receive the preset clock signal, and the frequency of the preset clock signal is less than the frequency of a local clock signal. In addition, the first input end and the second input end of the kth first mutex or gate may be respectively coupled to the output ends of the kth first transmission element and the k+1th first transmission element, and k is An integer greater than 0 and less than the total number of the plurality of first transmission elements.

In an embodiment of the invention, the first transmission component may be a plurality of first D-type flip-flops each having a clock terminal for receiving a local clock signal.

In addition, the clock detection circuit provided by the present invention further includes a plurality of second D-type flip-flops each having a clock terminal for receiving a local clock signal. These second D-type flip-flops can be triggered with the first D-type flip-flops using the negative and positive edges of the local clock signal, respectively. The clock detection circuit of the present invention further includes a plurality of second mutually exclusive gates, a second gate and a gate. Each second D-type flip-flop can also be coupled to the output of the second-stage D-type flip-flop of the previous stage to receive the data of the output, and transmit the received data to the local clock signal according to the local clock signal. The input of the second D-type flip-flop of the next stage. In addition, the input end of the first second D-type flip-flop can also be coupled to the clock source to receive the preset clock signal, and the k-th second D-type flip-flop and the k+ The output ends of the one second D-type flip-flop are respectively coupled to the first input end and the second input end of the kth second mutex or gate. In addition, all of the mutually exclusive outputs may be coupled to the second AND gate, and the output of the second AND gate may be coupled to the input of the OR gate respectively.

From another point of view, the present invention also provides a clock supply device that can provide a working clock signal to an electronic device. The clock supply device of the present invention includes a plurality of first transmission elements, a plurality of first mutually exclusive gates, a first gate and a multiplexer. Each of the first transmission elements may be coupled to the first transmission element of the first stage to receive the data of the output, and transmit the received data to the first transmission element of the next stage according to a local clock signal. Input. In addition, the input end of the first first transmission component can be coupled to the clock source to receive the preset clock signal, and the frequency of the preset clock signal is less than the frequency of the local clock signal. In addition, the first input end and the second input end of the kth first mutex or gate may be respectively coupled to the output ends of the kth first transmission element and the k+1th first transmission element, and k is An integer greater than 0 and less than the total number of the plurality of first transmission elements. The multiplexer can be coupled to the external clock source and the local clock source, and select one of the external clock source and the local clock source as the working clock signal according to the output of the first gate. To output to an electronic device.

Since the present invention utilizes a gate or a gate to detect a clock source pattern, the present invention can accurately detect whether the clock source is functioning properly. In addition, the clock supply device provided by the present invention is further configured with a multiplexer to respectively couple the local clock source and the external clock source. Thereby, the present invention can utilize the local clock source to supply the electronic device when the external clock source is not operating normally.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a circuit block diagram of a clock supply device in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the clock supply device 200 provided in this embodiment includes a clock detection circuit 202, a multiplexer 204, and a local clock source. The clock detection circuit 202 can couple the multiplexer 204 and the local clock source 206. In addition, the clock detection circuit 202 can also be coupled to the external clock source 212. Similarly, the input of the multiplexer 204 can also be coupled to the local clock source 206 and the external clock source 212, and the output of the multiplexer 204 can be coupled to an electronic device 214.

The local clock source 206 can output the local clock signal CLK1 and the sampling clock signal CLK3, and the external clock source 212 can output the external clock signal CLK2 to the clock detection circuit 202 and the multiplexer 204. In the present embodiment, the frequency of the sampling clock signal CLK3 is higher than the frequency of the external clock signal CLK2. In other words, the period of the sampling clock signal CLK3 is smaller than the period of the external clock signal CLK2. Thereby, the clock detection circuit 202 can sample the external clock signal CLK2 according to the sampling clock signal CLK3 to detect whether the clock supply device 200 receives the normal external clock signal CLK2. In the present embodiment, the frequency of the local clock signal CLK1 is twice the frequency of the external clock signal CLK2, and the local clock source 206, for example, divides the local clock signal CLK1 to generate the sampling clock signal CLK3.

The clock detection circuit 202 can output a selection signal SEL to the multiplexer 204 according to the state of the external clock signal CLK2. Thereby, the multiplexer 204 can select the external clock signal CLK2 or the sampling clock signal CLK3 as the working clock signal OUT_CLK to the electronic device 214 according to the selection signal SEL. The sampling clock signal and the external clock source received by the real-time pulse detecting circuit, for example, 16 MHz and 8 MHz, respectively, and the working clock signal finally provided to the electronic device does not take the local clock signal, but takes 1/2 The local clock signal of the multiplier and the external clock source are both provided to the electronic device using the local clock signal of 1/2 multiplier and the external clock source at the same frequency, only the phase is different.

3 is a circuit diagram of a clock detection circuit in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the clock detection circuit 202 can include a plurality of first transmission elements, such as 302, 304, and 306. Each of the first transmission elements 302, 304, and 306 can have an input terminal D and an output terminal Q. The input terminal D of the first transmission element of each stage may be coupled to the output terminal Q of the upper transmission element, and the input D of the first first transmission element 302 receives the external clock signal CLK2.

In addition, the clock detection circuit 202 can also include a plurality of first mutually exclusive gates, such as 308 and 310, and a first AND gate 312. The input ends of the kth first mutex or gate are respectively coupled to the output terminal Q of the kth transmission element and the k+1th transmission element. Where k is a positive integer greater than 0 and less than the total number of transmission elements. For example, the input of the first mutex or gate 308 is coupled to the output Q of the first transmission element 302 and the output Q of the second transmission element 304, respectively. Additionally, the inputs of the first AND gate 312 receive the inputs of the mutually exclusive or gates 308 and 310, respectively.

In this embodiment, each of the first transmission elements 302, 304, and 306 can be implemented by using a D-type flip-flop, but the invention is not limited thereto. In addition, each of the D-type flip-flops 302, 304, and 306 has a clock terminal C, and receives the sampling clock signal CLK3, respectively. Thereby, the D-type flip-flops of each stage can transmit the signal received by the input terminal D from the output terminal Q to the input terminal D of the next-stage transmission component according to the state of the sampling clock signal CLK3. In the present embodiment, the D-type flip-flops 302, 304, and 306 are positive-edge-triggered flip-flops.

In addition, the clock detection circuit 202 can also include a processor 322 and a warning module 324. The processor 322 can control whether the warning module 324 generates an alert information according to the state of the selection signal SEL.

4 is a timing diagram of a sample clock signal and an external clock signal in accordance with a first embodiment of the present invention. Referring to FIG. 3 and FIG. 4 together, in the present embodiment, it is assumed that the sampling clock signal CLK3 is twice the frequency of the external clock signal CLK2. In addition, it is assumed that at time t0, the states of the sampling clock signal CLK3 and the external clock signal CLK2 are both low bits, and are respectively sent to the clock terminal C and the input terminal D of the first D-type flip-flop 302. However, since the first D-type flip-flop 302 is a positive edge trigger, the state of the external clock signal CLK2 is latched to the input terminal D of the first D-type flip-flop 302.

At time t1, the sampling clock signal CLK3 is switched from the lower bit to the upper bit, and a positive edge state is caused on the local clock signal CLK2, so that the first D-type flip-flop 302 takes the state of the input D from The output terminal Q is output to the input terminal D of the first D-type flip-flop 304. At this time, the state of the output terminal Q of the first D-type flip-flop 302 is a low bit, and the state of the output terminal Q of the first D-type flip-flops 304 and 306 is unknown. Next, at t2, the external clock signal CLK2 is switched from the lower bit to the upper bit, and the sampling clock signal CLK3 is switched from the upper bit to the lower bit. At this time, the first D-type flip-flops 302 and 304 do not operate.

At t3, the sampling clock signal CLK3 is switched from the lower bit to the upper bit again, so that the first D-type flip-flops 302 and 304 respectively transfer the state of the input to the first D-type flip-flop of the next stage. At this time, the states of the output terminals Q of the first D-type flip-flops 302 and 304 are high-order and low-order elements, respectively, and the state of the output terminal Q of the first D-type flip-flop 306 is unknown. At t4, both the sampling clock signal CLK3 and the external clock signal CLK2 are switched back from the high bit to the lower bit, so that the first D-type flip-flops 302, 304, and 306 do not operate.

Next, at t5, the sampling clock signal CLK3 is switched from the lower bit to the upper bit again, at which time the first D-type flip-flops 302, 304 and 306 respectively output the state of the input terminal D from the output terminal Q. At this time, the states of the output terminals Q of the first D-type flip-flops 302, 304, and 306 are low-order elements, high-order bits, and low-order elements, respectively, and also represent different states of each of the mutually exclusive or gates 308 and 310. . Therefore, the inputs of the mutex or gates 308 and 310 are both high, so that the state 312 of the gate is also a high state. At this time, the selection signal SEL may be in a high state. Thereby, the multiplexer 204 in FIG. 2 can select the external clock signal CLK2 to be sent to the electronic device 214 as the working clock signal OUT_CLK. In addition, the processor 322 also causes the alert module 324 to be in an disabled state because the selection signal SEL is in a high state.

In contrast, if the external clock signal CLK2 is disabled, the mutex or the gates 308 and 310 have at least one of the outputs being in the low bit state, and the output of the AND gate 312 is also in the low bit state. At this time, the state of the selection signal SEL is also associated with the low bit, so that the multiplexer 204 selects the local clock signal CLK1 as the working clock signal OUT_CLK to be sent to the electronic device 214. Thereby, the electronic device 214 does not have a stoppage due to the external clock source 212 not functioning properly. On the other hand, the processor 322 can also control the alert module 324 to generate a warning message to inform the user according to the selection signal SEL being in the low position. In this embodiment, the warning information generated by the warning module 324 may be sound or bright light.

FIG. 5 is a timing diagram of a local clock signal and an external clock signal according to a second embodiment of the present invention. Referring to FIG. 5 in combination, in some embodiments, the sampling clock signal CLK3 may cause the clock detection circuit 202 to operate incorrectly due to noise or jitter. For example, at times t6 and t7, the sampling clock signal CLK3 is in a positive edge state, but the sampled external clock signal CLK2 is in a high state. This represents that the inputs of one of the mutex or gates 308 and 310 will be the same, resulting in the output of the AND gate 312 being low. At this time, the selection signal SEL is associated with an error state.

With continued reference to FIG. 3, to ensure that the state of the select signal SEL remains correct, in some embodiments, the clock detect circuit 202 further includes a plurality of second transmission elements, such as 332, 334, and 336. These transmission elements 332, 334 and 336 can also be implemented with D-type flip-flops, and the coupling means can also refer to transmission elements 302, 304 and 306. The difference is that in the present embodiment, these second D-type flip-flops 302, 304 and 306 are triggered by a negative edge.

Correspondingly, the clock detection circuit 202 can also include a plurality of second mutually exclusive gates, such as 338 and 340, and a second AND gate 342. For the coupling relationship of the second mutually exclusive or gates 338 and 340 and the second gate 342, reference may be made to the first mutually exclusive gates 308 and 310 and the first gate 312, and the present invention is not described again. In addition, the input terminals of the OR gates 344 are coupled to the inputs of the gates 312 and 342, respectively.

Since the first D-type flip-flops 302, 304, and 306, and the second D-type flip-flops 332, 334, and 336 are the positive edge trigger and the negative edge trigger, respectively. Therefore, even if the sampling clock signal CLK3 causes phase or time period wander due to noise or jitter, the clock detecting circuit 202 can correctly sample the external clock signal CLK2. For example, in FIG. 5, although the first D-type flip-flops 302, 304, and 306 may sample errors, the second D-type flip-flops 332, 334, and 336 may still be sampled correctly because they are negative-edge triggers. Aspect. In the present embodiment, as long as the output state of one of the gates 312 and 342 is correct, or the gate 344 can output the correct selection signal SEL. Thereby, it is ensured that the selection signal SEL is maintained in the correct state.

6 is a circuit diagram of a clock supply device in accordance with another embodiment of the present invention. Referring to FIG. 6, the difference between this embodiment and the embodiment of FIG. 3 is that the present embodiment uses D-type flip-flops 602, 604 and 606 instead of D-type flip-flops 332, 334 and 336 as the second transmission element. . Wherein, the D-type flip-flops 602, 604, and 606 can be positive-edge triggers. In addition, in this embodiment, the clock detection circuit 202 can further include an inverter 608, and the input end of the clock detection circuit 202 can be coupled to the clock terminal of the D-type flip-flop 302 to receive the sampling clock signal CLK3. The output of the 608 can then be coupled to the clock terminal C of the D-type flip-flops 602, 604 and 606. Therefore, the clock detection circuit 202 provided in this embodiment can also have the same function as the clock detection circuit 202 in FIG.

In summary, since the invention example can use the D-type flip-flop to sample the external clock signal, and use the mutual exclusion or gate to judge the state. Therefore, the present invention can accurately detect the state of the external clock signal. In addition, the present invention may further include a multiplexer, and may select an external clock signal or a local clock signal as the working clock signal according to the selection signal. Therefore, the present invention allows the electronic device to still operate normally when the external clock signal is energized.

In addition, in the present invention, since the D-type flip-flops with the positive edge trigger and the negative edge trigger can be configured, the present invention can eliminate the erroneous action of the local clock signal due to noise or jitter.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

102, 104, 106, 108. . . Device

110. . . Clock source

200. . . Clock supply device

202. . . Clock detection circuit

204. . . Multiplexer

206. . . Local clock source

212. . . External clock source

214. . . Electronic device

302, 304, 306, 332, 334, 336, 602, 604, 606. . . D-type flip-flop

308, 310, 338, 340. . . Mutual exclusion or gate

312, 342. . . Gate

322. . . processor

324. . . Warning module

C. . . Clock end

CLK1. . . Local clock signal

CLK2. . . External clock signal

D. . . Input

SEL. . . Selection signal

Q. . . Output

FIG. 1 is a block diagram of a conventional shared clock source.

2 is a circuit block diagram of a clock supply device in accordance with a preferred embodiment of the present invention.

3 is a circuit diagram of a clock detection circuit in accordance with a preferred embodiment of the present invention.

4 is a timing diagram of a local clock signal and an external clock signal in accordance with a first embodiment of the present invention.

FIG. 5 is a timing diagram of a local clock signal and an external clock signal according to a second embodiment of the present invention.

6 is a circuit diagram of a clock supply device in accordance with another embodiment of the present invention.

202. . . Clock detection circuit

302, 304, 306, 602, 604, 606. . . D-type flip-flop

308, 310, 338, 340. . . Mutual exclusion or gate

312, 342. . . Gate

322. . . processor

324. . . Warning module

C. . . Clock end

CLK1. . . Local clock signal

CLK2. . . External clock signal

D. . . Input

SEL. . . Selection signal

Q. . . Output

Claims (12)

A clock detection circuit is configured to detect whether a clock source normally supplies a predetermined clock signal, wherein the clock detection circuit comprises: a plurality of first transmission components, and each of the plurality of Each of the first transmission components is coupled to the first transmission component of the first stage to receive the data of the output, and transmits the received data to the input end of the first transmission component of the next stage according to a sampling clock signal, and The input end of the first first transmission element of the plurality of first transmission elements is coupled to the clock source to receive the preset clock signal, wherein the preset clock signal The frequency is less than the frequency of the sampling clock signal; the plurality of first mutually exclusive or gates, wherein the first input end and the second input end of the kth first mutually exclusive or gate are respectively coupled to the kth first transmission An output of the element and the k+1th first transmission element, and k is an integer greater than 0 and less than the total number of the plurality of first transmission elements; and a first AND gate receiving the plurality of first mutually exclusive Or the output of the gate. The clock detection circuit of claim 1, wherein the plurality of first transmission elements are a plurality of first D-type flip-flops each having a clock terminal for receiving Sampling the clock signal. The clock detection circuit of claim 2, wherein each of the plurality of first D-type flip-flops is triggered by a positive edge of the sampling clock signal, and The received data is transmitted to the next-stage first D-type flip-flop. The clock detection circuit of claim 1, wherein the clock detection circuit further comprises: a plurality of second D-type flip-flops each having a clock terminal for receiving Sampling a clock signal, and each of the plurality of second D-type flip-flops is coupled to an output of the second-stage D-type flip-flop of the first stage to receive the data of the output thereof, and according to the sampling clock Transmitting the received data to the input of the second D-type flip-flop of the second stage, wherein the input of the first second D-type flip-flop of the plurality of second D-type flip-flops The first clock input or the second input end of the kth second mutually exclusive switch An output of the kth second D-type flip-flop and the k+1th second D-type flip-flop; a second AND gate receiving the output of the plurality of second mutually exclusive or gates; Or a gate receiving an output of the first gate and the second gate; a processor coupled to the output of the gate; and a warning module coupled to the processor, The processor state according to the OR gate while controlling the alarm module determines whether to issue a warning information. The clock detection circuit of claim 4, wherein each of the plurality of second D-type flip-flops is triggered by a negative edge of the sampling clock signal, and The received data is transmitted to the next-stage second D-type flip-flop. The clock detection circuit of claim 4, further comprising an inverter, wherein the input end receives the sampling clock signal, and the output end thereof is coupled to the plurality of The clock terminal of the second D-type flip-flop. A clock supply device adapted to provide a working clock signal to an electronic device, wherein the supply device comprises: a plurality of first transmission components, and each of the plurality of first transmission components are coupled a first transmission element of the upper stage to receive the data of the output thereof, and to transmit the received data to the input end of the first transmission element of the next stage according to a sampling clock signal, and the plurality of first transmission elements The input end of the first first transmission component is coupled to an external clock source, wherein the frequency of the external clock source is less than the frequency of the sampling clock signal; the plurality of first mutually exclusive or gates The first input end and the second input end of the kth first mutex or gate are respectively coupled to the output ends of the kth first transmission element and the k+1th first transmission element, and k is greater than 0 and less than an integer of the total number of the plurality of first transmission elements; a first AND gate receiving an output of the plurality of first mutex or gates; and a multiplexer coupling the external clock source and a local clock source, and selecting according to the output of the first gate One of the external clock source and the local clock source is used as the working clock signal to output to the electronic device, the frequency of the external clock source is equal to the local clock The frequency of the source. The clock supply device of claim 7, wherein the plurality of first transmission elements are a plurality of first D-type flip-flops, each having a clock end for coupling Sampling the clock source. The clock supply device of claim 8, wherein each of the plurality of first D-type flip-flops is triggered by a positive edge of the clock signal, and is to be received The data is transferred to the next stage first D-type flip-flop. The clock supply device of claim 7, wherein the clock detection circuit further comprises: a plurality of second D-type flip-flops each having a clock terminal coupled to the sampling a clock terminal, and each of the plurality of second D-type flip-flops is coupled to an output of the second-stage D-type flip-flop of the first stage to receive the data of the output thereof, and according to the sampling clock end Transmitting the received data to the input of the second D-type flip-flop of the second stage, wherein the input of the first second D-type flip-flop of the plurality of second D-type flip-flops Is coupled to the external clock source; a plurality of second mutually exclusive gates, wherein the first input end and the second input end of the kth second mutually exclusive or gate are respectively coupled to the kth second D type An output of the flip-flop and the k+1th second D-type flip-flop, and k is an integer greater than 0 and smaller than the total number of the plurality of first transmission elements; and a second AND gate receiving the plurality of An output of the second mutex or gate; and an OR gate receiving an output of the first AND gate and the second gate, and an output of the OR gate is coupled to the multiplexer Controlling the multiplexer to select the one of the external clock source and the local clock source as the working clock signal to the electronic device. The clock supply device of claim 10, wherein each of the plurality of second D-type flip-flops is triggered by a negative edge of the clock signal, and is received The data is transferred to the next-stage second D-type flip-flop. The clock supply device of claim 10, further comprising an inverter, wherein the input end receives the local clock signal, and the output end thereof is coupled to the plurality of The clock terminal of the two D-type flip-flops.