SU1510014A1 - Device for correcting errors in memory blocks with serial access - Google Patents

Abstract

The invention relates to computing technology, in particular, to devices for correcting errors in memory devices with sequential access. The aim of the invention is to simplify the device and increase speed by providing coding of information when recording it in a memory device. The device for error correction in the sequential access memory contains an error detection block 1, an error address memory block 2, an error code memory block 3, a buffer memory block 4, a counter 5, an address selection block 6, a inverter 7, a correction block 8, bus driver 9, comparison unit 10, element OR 11, encoder 12, first 13 and second 14 switches, and first 15 and second 16 shift registers. Introducing a bus driver, a second shift register, and a second switch into the encoder device allows encoding and decoding to be implemented in a single device. 5 il.

Description

WITH

WITH

g

SP

error recovery 1, error address memory block 2, error code memory block 3, buffer memory block A, counter 5, address selection block 6, form. inverter 7, correction unit 8, bus driver 9, comparison unit 10, element OR 11, encoder 12, first 13 and second 14 switches, and first 15 and second 16 shift registers. Introducing a bus driver, a second shift register, and a second switch into the encoder device allows coding and decoding to be implemented in one device, 5 or more.

The invention relates to computing technology, in particular, to error correction devices in memory-storage devices (sequential access memory), and can be used to increase reliability by correcting packet errors.

The purpose of the invention is to simplify the device for error correction and increase its speed due to the coding of information when recording it in a sequential access memory,

Fig, 1 shows a block diagram of the device; on Fig.2 is a structural scheme of the encoder; Fig. 3 is a block diagram of the inversion signal generator; FIG. 4 is a block diagram of a second shift register; Fig. 5 is a structural block comparison circuit.

A device for error correction in memory units with sequential access (FIG. 1) contains an error detection unit 1, an error address memory block 2, an error code memory block 3, a buffer memory block 4, a counter 5, an address selection block 6, shaper 7 of inversion signals, correction block 8, bus driver 9, comparison block 10, element OR It-, encoder 12, first 13 and second 14 switches, first 15 and second 16 shift registers, information input 17 and output 18 of the device, first synchronous input 19, setup input 20, circulation input 21, control input 22 operation mode, the second synchronization input 23, the information input 24 writing to the device buffer memory block, device information inputs-outputs 25, device address addresses 26, error output 27 and output 28 uncorrectable

mistakes. FIG. 1 also shows a startup unit 29 comprising an inverter 30, a pulse generator 31, an AND 32 element and a trigger 33.

 Encoder 12 (FIG. 2) contains triggers 34-51, adders 52-60 modulo two, counter 61, trigger 62, elements AND 63, 64 and OR 65, and also encodes the incoming information in accordance with the code set by polynomial

P (X) (X + 1) (X + 1) (X +

(four

four

+ X + 1) X + X + X

+ + X + X + X + X +

+ X + 1,

The number of triggers 34-51 corresponds to the greatest degree X and is equal to 18, Adders 52-60 modulo two are located behind those triggers that correspond to non-zero powers X,

The inverter signal generator 7 (FIG. 3) contains AND elements 66, 67, switch 68, element OR-NE 69, inverters 70, 71, element OR 72, delay element 73, and inverter signal generator 74.

a buffer memory unit that must be turned on at the output of switch 68 to receive a non-standard signal at input 21,

The second shift register 16 (FIG. 4) contains the element IL 75 and register 76 on the IC K155IR13.

Comparison unit 10 (FIG. 5) contains an AND 77 element and comparison elements 78, 79 on the IC K555SP1, the number of which is determined by the digit of the comparison codes. Unintended information inputs can be grounded.

Counter 5 can be executed on IC K155IE6, correction block 8 on IC K155LP5, bus driver 9 on IC .K589AP16, shift register 15 on IC K155IR13, switch 13 on IC K155LR4, switch 14 on IC K531KP11G1. The buffer memory unit 4 can be implemented on the RAM RAM. The device input 22 controls the write-read mode in the buffer memory unit 4. The access signal to the buffer block 4 of the memory is supplied from the driver 7. The driver 74 of the circulation pulses can be executed on the IC K155AG1, at the input of which it is necessary to connect a differentiating chain. The delay element can be performed using a delay line such as OMS or similar.

The device works as follows.

Before starting the encoding and decoding modes, blocks 1, 5, 6, 7 and 12 are zeroed out.

The coding mode involves two steps.

At the first stage, information is received into the buffer — memory block 4. A control signal is fed to input 24, which allows information. Tsyi on the inputs-outputs 25 through the bus driver 9 and the switch 14 to arrive at the information inputs of the buffer block 4 memory. Input 22 is supplied with a write control signal in the buffer memory unit 4. Then, by sequentially applying the address codes to the inputs 26 and synchronously with them the codes of the numbers to the inputs 25, as well as the call signal from block 7, information is recorded in the buffer memory block 4.

At the second stage, information is encoded in encoder 12o. At input 22, a read control signal from buffer memory 4 is set. If the block stores byte words, then the sync signals are input to the device 19, which are used to shift the read from block 4 to the register .16 MB. The shifted bits are fed to the input of the encoder at the 12.no end of every eighth / second pulse arriving at the input 19, in block 6, the address is changed, which allows access to the buffer memory block 4 following the next

your address. In this case, in the shaper 7, the inversion signal is generated, which allows to read the next byte and write it to the register 16. This sequentially reads the entire information block and passes it through the encoder 12, resulting in 18 check digits of the code. From this moment on, the signal from counter 61 through trigger 62 and element And 63 opens the feedback in the register formed by triggers g 34-51 and C5 with moduli 52-60 modulo two. The obtained check bits are shifted through the element AND 64 and the element 65 to the output 18 of the device, on which all information bits had passed before. Thus, the output of the device receives the entire information sequence in a sequential code, which is written to one or another external memory. Depending on the speed of the external memory, the frequency of the pulses at the input 19 should be selected.

0

five

The decoding mode involves two steps.

At the first stage, information is received in the buffer block 4 of the memory and error detection in block 1. Input 24 is supplied with a control signal, which opens the switch

14 to transfer information to the buffer memory unit 4 from the register 15, bus driver 9 to transfer information from the buffer memory unit 4 through the output correction unit 8

25. Input 22 is supplied with a write control signal in the buffer memory unit 4. The input 17 from the external memory in the serial code receives information, followed by the sync signals on input 19. After every eighth pulse, the access signal to the buffer memory block 4 is processed by the driver 7 of the reference signals, and the information from the register

15 through the switch .14 in the parallel code is recorded in block 4, then in block 6 of the address selection, the address is changed to, disconnected, so it repeats until

All information will not be received in block 4.

At the same time, the information enters the error detection unit 1. By-

Unless all 1155 bits are received, block 1 will generate signals Opshk on output 27, No error on output, and on output 28 - Correctable error, Uncorrected error. The Error Error at output 27 starts block 29, which, through the OR 11 element, continues to send clock signals, the frequency of which can be much higher. After block 1 generates an error signal fixed, arriving at block 2 and switch 13, the error correction stage begins.

At the second stage, information is transferred from the buffer memory unit 4 to the output of the device. At the device input 22, a read control signal from block 4 is set. At the input 21, turn signals are supplied, synchronously with which the dres codes are sent to the inputs 26. At the output of block 4, there are data bytes transmitted to outputs 25 "In the case of a correctable error in block 10 of the comparison, the address signals containing the error are generated, the comparison signals are generated, through the switch 13 the error vector codes are transmitted to the correction block 8, where This is a bug fix. The proposed device in the correction mode works similarly to the known.

Thus, by introducing four new blocks and changing the design of the two known ones, the functionality of the proposed device is enhanced by implementing the information coding procedure. This creates a positive technical and economic effect. The latter is achieved due to the fact that the implementation of a separate code would lead to an increase in hardware costs by about 1.7 times, whereas a design change is associated only with a 20% increase in similar costs.

Claims (1)

Invention Formula - A device for error correction in memory blocks with sequential access, comprising an error detection block, an error address memory block, an error code memory block, a buffer 0 5 p 5 50 five 0 memory unit, counter, address selection unit, reverse signal conditioner, correction unit, OR element, comparison unit, first switch, first shift register, the first control input of the reverse signal generator connected to the first shift register control input the input of the address selection block and is the first synchronous input of the device, the second control input of the counter is connected to the second control input of the address selection block, the first control input of the detecting unit and the input In the device setup, the second control input of the reference signal generator is the input of the device, the first control input of the buffer memory block is connected to the third control input of the address selection block, the third control input of the reference signal generator and is the input of the operation mode setting device, the output of the inverter signal generator is connected to the second control input of the buffer memory block, whose address inputs are connected to the outputs of the address selection block. Address inputs of the first group The sensors of which are connected to the address inputs of the reference signal generator and the outputs of the counter, the address inputs of the second group of the address selection block are connected to the address inputs of the first group of the comparison block and are the address inputs of the device, the outputs of the buffer memory block are connected to the information inputs of the first groups of the correction block, the information inputs of the second group of which are connected to the outputs of the first switch, the information inputs of the first and second groups of which are connected respectively to the outputs of the block of an error code memory block, information inputs of the first and second groups of which are respectively connected to the outputs of the second block group — error detection, outputs of the error address memory block and information inputs of the second comparison block group, information inputs of the error address memory block connected to the outputs of the first group of the error detection block, the first output which is connected to the control input of the error address memory block and the control input of the first switch, the second control input of the error detection block is connected to the output of the OR element, the second input of which is the second synchronous input of the device, the second and third outputs of the error detection block are, respectively, the output of the sign of the presence of an error and the output of the sign of an uncorrectable device error, the information input of the first shift register is connected to the information input of the error detection block and is Formation input of the device, characterized in that, in order to simplify the device and speed up, it contains an encoder, a second switch, a second CD register, a bus driver, the information inputs of the buffer memory block are connected to the outputs of the second switch, information inputs of the first and the second group of which is connected to the outputs of the first shift register and the tire driver, respectively, the inputs of which are connected to the outputs From 5 FIG. five the correction unit, the input-outputs of the bus driver are information inputs-outputs of the device, the information inputs of the second shift register are connected to the outputs of the buffer memory block, the first control input of the second shift register is connected to the output callback generator, The second control input of the second shift register is connected to the first control input of the counter and the first control input of the encoder, the second control 1st input of which is connected to the second control input of the counter, the information input of the encoder is connected to the output of the second shift register, the information output of the encoder is the information output of the device, the control input of the second switch is connected to the fourth control input of the conversion signal generator, the control input of the bus driver AND is the signal a break of recording information into a buffer storage unit; the fifth control, a YushJ input of the reference signal generator, is connected to the second control  counter input. FI.2 Kif.K Fiel 25 over R From g / -s: fig 5 7J L