KR950012070B1 - Interface between 32-bit unit telecom module and a.t.m disassemblekey - Google Patents

Abstract

The interface comprises a counter for counting 53 notation so as to couple ATM cell disassembler processing a byte unit operation on the basis of an asynchronous transmission mode cell of 53 octet, with a module processing an operation of 32 bit on the basis of a module telecommunication cell of 56 octet; first to fourth and eighth bit buffers for storing data to be transmitted to the ATM cell disassembler, the first to fourth and eighth bit buffers being used as FIFO buffers; and a unit converting part for performing a proper buffer access by an empty flag signal from any one of the buffers.

Description

Interface device between 32-bit communication module and AMC M Disassembler

1 is an overall block diagram according to the present invention

2 is a block diagram of a unit conversion circuit according to the present invention.

3 operation timing diagram

According to the present invention, an ATM cell disassembler that performs byte-based operation processing based on a 53-octet asynchronous transfer mode (hereinafter referred to as ATM) cell and a 32-bit unit operating processing based on a 56-octet module communication cell is performed. The present invention relates to an interface device between an ATM cell disassembler and a 32-bit communication module for connection between modules.

The conventional technology has a problem in that the data rate clock is about 30 MHz and the data rate is limited to about 250 Mbps by processing in 8-bit units. In general, the upper three octets of the cell for module communication are frame synchronization associated with physical media connection of the physical layer. The remaining 53 octets are mapped to ATM cells. Therefore, the top three octets of the received 56 octet module communication cell need not be forwarded to the ATM cell disassembler.

Accordingly, the present invention devised to meet the above problem and needs is to provide a 53-octet ATM cell with a cell start signal at the same time that the first octet of the ATM cell is delivered to ensure 53-octet ATM cell operation of the ATM cell disassembler. It is an object of the present invention to provide an interface device for generating a valid cell display signal during a bit data transmission period.

In order to achieve the above object, the present invention provides an ATM cell disassembler that performs byte-based operation processing based on a 53-octet asynchronous transfer mode cell and a 32-bit unit based on a 56-octet module communication cell. A count means for operating as a 53-definition counter for connection between modules, first to fourth, 8-bit buffers for storing data to be transmitted to an ATM cell disassembler and acting as a first-in first-out buffer (FIFO), and a counter output value of the count means And unit converting means for performing appropriate buffer access by an empty flag signal from any one of the first to fourth buffers.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall block diagram according to the present invention, where 11 is a count circuit, 12 is a unit conversion circuit, and 13 to 16 are buffers, respectively.

As shown in the figure, the present invention provides 32-bit data from the communication module connected to the ATM cell disassembler to the most significant bit, that is, from bits 31 to 24 of the module communication cell data, from bits 23 to 16. 1st buffer 13, 2nd buffer 14, 3rd buffer 15, and 4th in order from bit 15 to bit 8, bit 7 to bit 0, the least significant bit. 32 bits are simultaneously input to the buffer 16 together with an associated input signal.

Here, the first buffer 13, the second buffer 14, the third buffer 15 and the fourth buffer 16 all operate as a FIFO.

At this time, when the value of the empty flag from any one of the four buffers from the first buffer 13 to the fourth buffer 16 changes from 0 to 1, the 53-definition counter of the counter circuit 11 is The 53-octet ATM cell by the unit change circuit 12 starts to be delivered to the ATM cell disassembler in bytes in accordance with the counter output value of the counter circuit 11 accordingly.

The unit conversion circuit 12 operates like a decoder circuit of a 10 bit output for a 7 bit input. That is, the appropriate buffer in the first buffer 13 to the fourth buffer 16 is accessed according to the empty flag and the 6-bit counter output value from an arbitrary buffer, and at this time, the ATM cell sequence integrity must be accessed. Should be ensured.

2 is a block diagram of a unit conversion circuit according to the present invention, in which 17 represents a counter decoder and 18 represents a frame synchronization control circuit.

As shown in the figure, the unit change circuit 12 decodes an output value of the counter circuit 11 to generate a frame synchronization signal and a cell start signal for converting a 56-octet module communication cell into a 53-octet ATM cell. And a frame synchronizer elimination circuit 15 for removing the upper three octets of the frame sync portion of the first four octets of the 56-octet module communication cell by the frame decoder signal.

If such an operation is described using the operation timing diagram of Fig. 3, access will always occur unless the buffer is basically empty, and the unit conversion circuit 12 has 56 octets of module communication cells when the counter output value is zero. Recognizes the 32 bits corresponding to the first 4 octets of the first < RTI ID = 0.0 > octet < / RTI > Only the first octet of the octet ATM cell is output to the ATM cell disassembler. To do this, access to each buffer is performed in two stages. First, data is read from the buffer, stored in a register, and output from the register in the next step. 4 buffers (13 to 16) Once one byte of data from four buffers is simultaneously input into the register by read signal 0, read signal 1, read signal 2 and read signal 3, the output is buffered by output signal 3. Only 1 byte from (16) is output. In addition, a cell start signal is generated and an effective cell display signal is also enabled.

While the counter output value is increased by 1 and goes to 52, it is read out from the corresponding buffer in the order of read signal 0 and output signal 0, read signal 1 and output signal 1, read signal 2 and output signal 2, read signal 3 and output signal 3. do. As soon as the counter output value of the counter circuit 11 changes from 52 to 53, the counter circuit 11 is reset to produce the counter output value 0, and the above-described operation is repeated as long as the empty flag is 1. If the counter output value is 0 and the empty flag is 0, all read signals and output signals of the unit conversion circuit 12 are disabled, and the output value of the counter continues to display 0, and the valid cell display signal is also disabled. Done.

As described above, the present invention provides a cell disassembler corresponding to an ATM layer receiving function processing unit in a subscriber access network of an ATM based broadband integrated information network, and a high speed physical medium access unit and shared medium access unit of 155Mbps, 622Mbps, or GbPs level. It can be used as an interface device with.

Claims (2)

A connection between an ATM cell disassembler that performs byte-based operation processing based on a 53-octet asynchronous transfer mode (hereinafter referred to as ATM) cell and a module that performs 32-bit operation processing based on a 56-octet module communication cell. A counting means (11) acting as a 53-definition counter for the first to fourth data buffers (13 to 16) for storing data to be transmitted to the ATM cell disassembler and operating as a first-in first-out buffer (FIFO). And unit conversion means (12) for performing appropriate buffer access by means of an empty flag signal from any one of the first to fourth buffers (13 to 16) and the counter output value of the counting means (11). An interface device between a 32-bit unit communication module and an ATM cell disassembler. The method of claim 1, wherein the unit conversion means (12); The counter decoder 17 for decoding the counter output value from the counting means 11 and the frame synchronization removing means 18 for removing three octets of frame synchronization from the 56-octet module communication cell according to the decoding result are provided. Interface device between a 32-bit unit communication module and an ATM cell disassembler.