KR0159671B1 - Output buffer type switch having common memory structure - Google Patents

Abstract

1. The field of technology described in the claims

The present invention relates to an ATM (Asynchrous Transfer Mode) switch of a high-speed broadband network, and more particularly, to an output buffer type ATM switch having a shared memory structure that allows the output buffer processing speed to operate M times faster by using M output buffers. It is about.

2. The technical problem to be solved by the invention

The switch structure is modularized into 4 × 4 units so that a large number of switch modules can be connected in multiple stages when necessary for large capacity.As a result, even if a malfunction occurs in some passages of the switch structure, it can be implemented through other passages. Provide a device to ensure that

3. Technical summary of the invention

In the ATM switch, the AMT cell is input and rearranged, and the routing information of the root table is read by referring to the cell ID, and the input unit 100 and four 10-bit (MSB: cell synchronization signals) Bit: data, LSB: port selection signal) The routing unit 200 interconnecting all input units in a parallel bus structure, and the cells received from the routing unit 200 are temporarily stored in an internal buffer and then sequentially read out. And an output unit 300 to control each device in the switch module through the VME bus under the control of the controller, and to update the root table of the corresponding port whenever a new service request is received from the user. Output buffer type switch with shared memory structure.

4. Uses of the Invention

ATM switch

Description

Output buffer type switch with shared memory structure

1 is a circuit diagram according to the present invention.

2 is a concrete circuit diagram of the input unit 100 of FIG.

3 is a concrete circuit diagram of the tag processing unit 202 of FIG.

4 is a detailed circuit diagram of the routing portion 200 of FIG.

5 is an exemplary cell header according to the present invention.

6 is a cell form and root table search example in accordance with the present invention.

Figure 7 illustrates an 8 × 7 three stage switch in accordance with the present invention.

8 is a detailed circuit diagram of the first output unit 300.

The present invention relates to an ATM (Asynchrous Transfer Mode) switch of a high-speed broadband network, and more particularly, an output buffer type having a shared memory structure that allows the output buffer processing speed to be operated at an M times faster by using M output buffers. It is about a switch.

In order to implement ATM (Asynchrous Transfer Mode), which is a technology of Broadband Integrated Services Digital Network, an ATM switch capable of processing ATM cells at high speed is essential.

Many switch structures have been proposed to configure the ATM switch, and can be largely divided into an input buffer type, an output buffer type, and a shared memory type. The input buffer type has a simple structure but is not suitable for a high performance structure because its maximum throughput is limited. The output buffer type that can give maximum throughput to 1 (theoretical maximum) is suitable as a high performance structure, but in case of M × M switch, the circuit located at the output part operates M times faster than the transmission speed of the input part. It is difficult to implement the same device technology because it must be.

Also, a problem that can occur when using multiple output buffers is that a particular buffer is empty, but if a cell is crowded in a buffer next to it, a cell may be lost at that port. It acts fatally. In addition, the capacity of the ATM switch is required to be large. At this time, if the switch structure is increased, the number of connector pins, a power problem, and a noise problem may occur. On the other hand, although the ATM switch is asynchronous, all cells generated in the network must be synchronized. When the distance between systems becomes far, it is very difficult to synchronize the synchronization because the delay time of each transmission path is different.

Accordingly, an object of the present invention is to consider a large number of output buffers as one large shared memory, and only a specific buffer becomes full, and the cell loss rate that can be generated when the remaining buffer is empty is significantly changed. An ATM switch can be reduced.

It is an object of the present invention to modularize the switch structure in 4 × 4 units to connect a large number of switch modules required in a large capacity in multiple stages, thereby increasing the capacity of the switch structure. To provide a switch that can be implemented.

Another object of the present invention is to provide a switch that can solve the problem that the speed of the output portion is M times the input portion by using the M output buffers.

Another object of the present invention is to provide a switch that can be easily implemented in general TTL or CMOS by reducing the overall operation speed to 20MHz or less by adopting an 8-bit parallel structure to satisfy the characteristics of ATM that should be operated at 155Mbps.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an ATM switch circuit diagram according to the present invention. The ATM switch module described in the present invention is configured in 4x4 class, and each module is composed of one board. The 4 × 4 output buffer ATM switch buffers ATM cells input from the input port (port 0-port 3) of the input unit 100 in the first to fourth buffers 111-115 and attaches them in front of the cells of the routing unit 200. By using the routing tag (Routing Tag) serves to deliver to the output port through the Fipo (FiFo0-FiFo3) and the multiplexer (MUX1-MUX4) of the output unit 300. The one module has a port of 4 × 4 units and is designed to increase the capacity of the switch by using a plurality of modules. Each port of the switch (port0-port3) is capable of processing data up to 155.52Mbps per port in 8-bit parallel form, but the switch can support a multicasting function in hardware, and a third memory A shared memory buffer is provided at the output to reduce the cell loss rate and minimize the delay. And a bus for connecting to the outside so that the internal register value can be changed in order to transfer information such as the state of the switch and error detection to the outside. Here, one module has four input ports port0-port3 and four output ports OP1-OP4 as shown in FIG. Each of the four input / output ports (port0-port3) and (OP1-OP4) has an 8-bit data structure, and can operate at 19.4 MHz, thus having a processing speed of up to 155.52 Mbps per port (actually 9-bit parallel In this case, the MSBs are used as synchronization signals with each other). As shown in FIG. 1, the switch module is largely composed of an input unit 100, a routing unit 200, an output unit 300, and a control unit (not shown) connected to the VME bus.

The input unit 100 receives cell information through an input port (port 0-port 3) and rearranges the first and fourth buffers 111 through 115, and routing information of the root table with reference to the cell ID. The routing unit 200 is composed of four root units 211-214, and has four bits (cell sync signal 1 bit, cell data 8 bits, and cell Belide data 1 bit). Input to the parallel bus. The routing unit 200 performs a function of interconnecting all of the input unit 100 and the output unit 300, and the port selection signal is information read by interpreting a cell ID from the input unit 100. The output unit 300 is composed of a fifo (FiFo0-FiFo3) and a multiplexer (MUX1-MUX4) to temporarily read the cells received from the routing unit 200 in an internal buffer, and then read them sequentially. The control unit controls each device in the switch module through the VME bus by the main processor, and updates the root table of the corresponding port whenever a new service request is made from the user. As shown in FIG. 2, the input unit 100 of the switch is composed of a receiving unit 201, a tag processing unit 202, and an SRAM 203 storing a root table.

The receiving unit 201 latches and rearranges the signal input at the TTL level to BCLK (19.44 MHz), and the tag processing unit 202 receives the ID tag at the head of the input cell to provide routing information necessary for the switch module (4). Bit) and transfers it to the routing unit 200, and delays the cell while searching for the SRAM 203 that holds the root table. The structure of the tag processing section 202 is shown in FIG.

Receives data of the receiving unit 201 from the delay unit 301 through the receiving unit 351 and delays the cell stream data to the 352 stages, and receives the data of the receiving unit 351 from the ID extracting unit 302. The ID of the received data is extracted and the routing information is retrieved and stored in the SRAM 203 under the control of the controller, and the 16-bit counter 303 is generated by the count read signal and the port selection signal generated from the SRAM 203. Each time the Belide cell passes, the value of the counter 303 is increased to generate a port selection signal 0-3. The output value of the counter 303 is periodically read by the main processor of the controller through the bus, and the main processor can measure the cell loss rate in the switch device based on this value. When the cell arrives at the input part of the switch, the ID tag of the input cell is examined to determine the output port, and the cells are sent to the first to fourth root parts 200 of the root part 200 while the corresponding output port is selected. Enable rooting. In the case of multicasting, a cell is exported with a number of output ports selected among the port selection signals 0-3, and received at each corresponding output port.

FIG. 4 is a circuit diagram of one root portion of the first-fourth root portions 211-214 of the routing portion 200 of FIG. 1. The fourth portion of the first-fourth buffer 111-115 of the input portion 100 is illustrated in FIG. As a configuration example in one buffer, cell data 0-8 and port selection signals 0-3 (V0-V3) output from the tag processing unit 202 of the buffer are generated. The cell data 0-8 are input to the first to fourth data and control signal generators 411, 413, 415, and 416 through the line 352, and are inverted by receiving the input via the input terminals V0-V3 to the port selection signals 0-3. A pointer 401 indicating a FiFo of a position to be finally stored for output data from each buffer of the input unit 100 through input to the 2-bit adder 403-406 through 407-410; A 2-bit adder 403-406 that adds the output of the inverters 407-410 and the output of the pointer 401 or the output of the previous 2-bit adder bit by bit, and the 2-bit adder 403-405 A first to fourth generation generating a control signal for storing the cell data and generating a control signal for read / write and data to be stored in the fifo 0-3 of the output unit 300 by receiving the output of The data and control signal generators 411-416 and the first to fourth data and control signal generators 411-416 are configured to be first. A is connected to the 1-4 encapsulated (FiFo0-FiFo3) of the output section 300.

5 shows the head form of a standard ATM cell, the cell input to the switch, and the form of a header. Currently, only a portion of (5A) VP1 and VC1 is used to route a cell. The transmission module (STM1: 155.52MHz) When the cell is exchanged with the outside, the ATM cell is converted into a standard ATM cell header type, and once the cell is inputted, the VP1 and VC1 are replaced with ID0 and ID1 and are input to the switch in the header form as shown in FIG. On the contrary, when it is output, it is output after changing to the standard form as shown in FIG. 5 (5A).

6 shows a process of selecting an output port of the switch. Each cell arriving at the switch has a tag indicating a cell ID of 2 bytes in the header of the cell. The output table is designated by reading the root table (width: 4 bits) having the address area of 64K by the ID, and the 4-bit data read out corresponds to the output port number. Only one bit is set in the array, but in case of point-to-multipoint, several bits can be set. The value of the root table is set in consideration of the routing path of the main processor when a call is connected. Since the switch module has a different value set in the root table according to its position in the switch network, the controller in the switch selectively accesses the root table when the main processor accesses the switch module using a board ID (3 bits) set in the back board. . Since the routing path in the switch network is determined by the ID tag attached to the cell, each service module is assigned a unique ID from the main processor when the call is connected and used for cell generation. In order to connect the call, a call connection request signal must first be sent from the service module to the main processor, and this signal must also be transmitted through the switch network. Therefore, several IDs are allocated to each service module for this purpose. 6, it can be seen that the width of the cell data is 9 bits. In this case, the MSB is used for indicating a synchronization signal of a cell. That is, MSB = 1 indicates the starting point of the cell, the cell of each port input to the switch is input at the same time when the synchronization signal of the cell is 1. The cell synchronizing signal is equally supplied from the clock board, and the ID extracting unit 302 monitors the flow of the cell and extracts 2 bytes of ID information from the time when the MSB becomes 1. Based on the above information, it is read which port to select in the root table. The ID extractor 302 also extracts an ID for determining whether a cell is valid and inputs it to the SRAM 203 as an address signal, thereby reading the stored value, thereby counting the counter for port selection of the counter 303. Generated as a control signal count read signal to increase the counting to generate port selection signals 0-3. Data input to each of the four buffers of the first to fourth buffers 111, 113, 114, and 115 of the input unit 100 is 10 bits. The 10-bit data is composed of 1 bit as a cell synchronization signal, 8 bits as cell data, and a total of 10 bits are input to each buffer in parallel for 1 cell read from the root table. Outputs of the first to fourth buffers 111, 113, 114, and 115 of the input unit 100 are input to the routing unit 200. One root of one of the first to four root units 211-214 of the routing unit 200 is formed. Although it can be shown in detail as shown in FIG. 4, in the end, one of the four buffers of the first to fourth buffers 111, 113, 114, and 115 of the input unit 100 is selected (4: 1), and the FiFo of the output unit 300 is selected. To send). That is, the root unit 200 selects which packet to transmit the cell stream from the input unit 100 to determine which packet to store the valid data input from each port, but the port selection signal 0 to 0 when the port input from each port is 0 to 0, and 0 to Idle if the cell input from each port is 0-3 (V0-V3). Is to be entered.

In FIG. 4, the pointer 401 indicates the final FiFo when the cells are written to the FiFo in the immediately preceding frame so that the FiFo can be used as the memory. In FIG. 4, for example, when Belide cell is input to port 0, port 2, and port 3 (V0, V2, V3), and the pointer 401 is 2, the last cell in the previous frame is Fipoo2 (FiFo2). ), The cells input from port 0 (V0) among the cells that are currently input are stored in FiFo3, and the cells input from port 2 (V2) are stored in FiFo0. Cells input from port 3 (V3) must be stored in FiFo1 to use four of them. By using the shared memory method as described above, when a specific cover is pulled, it is possible to prevent another cover from being empty, thereby preventing a cell loss rate and delay.

For example, when a Belize cell is input to the ports 0, 2, and 3 (V0, V2, and V3), the bead bits of the ports 0, 2, and 3, that is, the port selection terminals V0, V2, and V3 of FIG. 0, and port 1, that is, port selection terminal V1 in FIG. Therefore, the pointer 401 latches the last covered number of the previous frame, and the value inputted to the port 0 (V0) as the latched value is inputted to the adder 403 through the inverter 407 when the cell header of the next frame is input. do. The adder 403 received from the port 0 (V0) adds 1 to the value of the pointer 401 when the port 0 (V0) is 0. In this case, the adder 403 sets the inverter 407 to 1 at the port 0 (V0). ) Has an output of 3. 3 of the value of the adder 403 by 0 of port 0 V0 means that the cell now input at port 0 V0 should be written to FiFo3. That is, only PSA3 in the selection select-bits PSA0-3 of port 0 (V0) becomes 0 during one frame. The addition result of the adder 403 is inputted from the port 0 (V0) to the adder 404 by inverting the input of the port 0 (V0) from the inverter 408, where the bead of the port 1 (V1) is input. Since the bit is 1 (ie Idle), the adder 404 from port 1 (V1) has the same value as the adder 403 from port 0 (V0), and the select bit bits PSB0-3 of port 1 (V1) All 1's. As a result of the adder 404 from the port 1 (V1), the value inverted by the inverter 409 through the port 2 (V2) is input to the adder 405, and the bead bit of the port 2 (V2) is input. Since 0 is added, the output value of the adder 405 from port 2 (V2) is 0. That is, since the input cell of the port 2 (V2) should be written to the FiFo0, only PSC0 of the selection bits PSC0-3 becomes 0. The addition result of the adder 405 by the value inverted by the inverter 409 input from the port 2 (V2) is the value through the inverter 410 from the port 3 (V3) and the adder 406. Is entered. According to the input value from the port 3 (V3), the adder 406 adds 1 to the adder 406 by the port 3 (V3) because the bead bit of the port 3 (V3) is zero. Therefore, only PSD1 of the selection bit PSD0-3 becomes zero. All of the addition process is performed by the bit clock BCLK. The pointer 401 of FIG. 4 has a final added value, that is, 1 in the above case. The above functions are performed at every frame cell input. The root unit 200 is a 4: 1 selector and selects a cell of a port 0 among PSA0, PSB0, PSC0, and PSD0 to be written to FiFo0. If there is no cell, a dummy cell is provided, and the header is analyzed to determine whether or not the dummy cell. In the case of the dummy cell, the service module attaches a specific ID tag (Oxffff ') to the cell header. Therefore, the ATM switch can ignore the dummy cell by writing 4 bits of '1111' to the corresponding address of the specific ID tag ('Oxffff') at power-on. In the case where the pins are multicasted, for example, if they are to be multicasted to four ports, the input cell is written to port 0-3 by writing '0000' to the corresponding address of the ID tag of the cell in the SRAM 203 which is the root table. Can be printed as Today's ATM switches can be configured in a multi-stage structure in order to expand to 8x8 because one sheet is 4x4. In FIG. 7, the multistage structure is shown. As shown in FIG. 7, the three-stage structure can be expanded to a large capacity. In addition, the output unit 300 of FIG. 1 has a shared memory structure, and has a function of temporarily storing and sequentially outputting cells provided through the root unit 200 in the input unit 100. In FIG. 8, the configuration of the output unit 300 of the switch is shown in detail. In FIG. 8, the QS is a cell selection unit that performs a function of finding a cell to be sent to an output port in the memory. The QS unit selects a cell and sequentially outputs the cells to the output port by scanning round the envelopes in the protected memory unit at every cell cycle using a round robin method. At this time, the object to be scanned is limited to the bag containing the cell, and for this purpose, each bag is provided with a flag indicating the presence or absence of the cell. The cell output from the QS unit is transmitted to the service module or the switch module of the next stage.

As described above, a plurality of output buffers can be regarded as one large shared memory, so that a specific buffer becomes full and the cell loss rate that can occur when the remaining buffers are empty can be dramatically reduced. There is an advantage to this.

Claims (3)

An ATM switch having a control unit for controlling each device in a switch module through a VME bus and updating a route table of a corresponding port when a new service request is received from a user, wherein each of the four first to first ones is controlled by the control of the control unit. Receives ATM cell data of 10 bits (cell sync signal 1 bit, cell data 8 bit, cell belid data 1 bit) with 4 buffers 111, 113, 114, and 115, rearranges them in the respective buffers, outputs cell data, and extracts cell IDs. Receiving the cell data of the first to fourth buffers 111, 113, 114, and 115 of the input unit 100 under the control of the control unit and generating the port selection signal. Routing unit 200 interconnecting all the buffers of the input unit 100 in a parallel bus structure to determine the position of the empty FiFo to store and transmit, and An output buffer type switch having a shared memory structure, characterized by consisting of a output unit 300 to output by reading the cells received from the routing section 200 in sequence after temporarily stored in the buffer by. The at least one buffer of the first to fourth buffers 111, 113, 114, and 115 of the input unit 100 bit-clocks one bit of a cell sync signal, eight bits of cell data, and one bit of cell bead data. The receiving unit 301 latches and rearranges (BCLK) and the ID tag at the head of the input cell of the receiving unit 301 to receive the cell data and the port selection signal necessary for the switch module. An output buffer type switch having a shared memory structure, characterized in that it comprises a tag processing unit (200) to be transmitted to the 200, and the SRAM (203) that stores the route data under the control of the control unit. The inverter of claim 1, wherein the root of one of the first to fourth root parts 211-214 of the routing part 200 receives and inverts the input port V 0 through V 3 with respect to the port selection signal 0-3. 407-410, a pointer 401 for generating a signal indicating a FiFo of a position to be finally stored for output data from each buffer of the input unit 100, and a pointer 401 of the inverter 407-410. A 2-bit adder (403-406) for adding the output of the pointer (401) or the output of the previous 2-bit adder bit by bit, and the output of the 2-bit adder (403-405) to the cell data. 1-4 data and control signal generator 411-416 generating a control signal for storage and generating a control signal for read / write and data to be stored in Fifo 0-3 of the output unit 300. ), And an output having a shared memory structure, characterized in that the first to fourth data and the control signal generator (411-416) Peohyeong switch.