KR970002748B1 - Inner cell generator in atm switch - Google Patents

Abstract

The apparatus for generating inner cell transmitting ATM cell format which front side contains routing and synchronous informations includes a high speed memory(401) storing additive information, a register(402) determining length of the additive information, an address generator(404) transmitting corresponding message address according the length of the additive information to the memory when receiving effective data cell signal from cell matching circuit of outer absolute assembly language(AAL) chip, a register(405) storing corresponding message cell additive information as much as byte number, and a shift register(403) transmitting inner cell to ATM switch as shifting ATM standard cell data with unit of byte.

Description

Internal cell generator of ATM exchanger

FIG. 1 is a block diagram of a cell output unit of a general commercial Absolute Assembly Language (AAL) chip.

2 is a standard ATM cell format diagram,

3 is an internal cell format diagram in which additional information is added according to the present invention;

4 is a block diagram of an internal cell generating apparatus according to the present invention;

5 is a main logic timing diagram according to the present invention;

6 illustrates the function of an address generator in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

101: cell transmission unit 401: high speed dual access memory

402: additional information size register 403: shift register and matching unit

404: address generator 405: additional information storage register

The present invention provides routing information in front of an ATM cell format to be output when mutual message exchange between the input / output controllers and the call processing processor is performed through an ATM location in an automatic transfer mode (ATM) exchange based on self-routing. The present invention relates to an internal cell generating apparatus of an ATM switch which adds and transmits additional information such as synchronization information.

FIG. 1 is a block diagram of a cell disassembly unit of a conventional commercial AAL chip. The processor logic unit 103, the control memory and control memory logic unit 104, the packet memory and the packet, respectively, are connected to a system bus. A memory logic section 105, a message buffer 106 for receiving and storing packets from the packet memory and packet memory logic section 105, and a message buffer 106 upon receiving a read clock and a read valid signal from a cell matching section. A cell transmitter 101 for transmitting a cell valid signal and cell data to the cell matcher, the processor logic 103, the control memory and control memory logic 104, a packet memory and a packet memory The central controller 102 controls the logic unit 105 and the cell transmitter 101.

The cell decomposing unit of the commercial AAL chip configured as described above has a function of internally converting a packet message into an ATM standard cell form and transmitting it from the cell transmitter 101 to the ATM switch. The standard ATM cell format conforms to the ITU recommendation. , The user cannot add arbitrary information to the front of the cell.

2 is a standard ATM cell format diagram, which is output from the cell transmitter 101 of the commercial AAL chip, and the standard ATM cell format recommended by the Internatimahonal Telecommunications Union (ITU) is 53 bytes in total as shown in the figure. It consists of 5 bytes of cell header and 48 bytes of payload. In the cell head, Generic Flow Contro1 (GFC) is allocated for the mechanism for controlling cell flow on ATM connection. For purposes of internal use in exchanges, they are generally ignored if they do not have to be used for their original purpose.

The Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) are virtual path recognition and virtual channel recognition, respectively, and are fields that allow the ATM switch to recognize the virtual path group and the virtual channel group transmitted through the physical medium. In addition, PT (Payload Type) indicates a payload type, and when used as a field for distinguishing pay data, CLP (Cel1 Lo) s Ptiority (CLP) is a field indicating a cell that may give priority to congestion.

A standard ATM cell configured as described above is a commercial AAL chip that is transmitted in an ATM transmission environment but can only process a standard cell in an ATM switch that requires self-routing. Additional information such as additional routing information is provided in the standard cell. Can not process the inner cell added.

In other words, in case of using commercial AAL chip that converts packet type message into standard cell format, additional information for generating internal cell is not included because there is no built-in register or operation function that can process the above additional information. There was a difficult problem to add.

The present invention has been made to solve the problems of the prior art as described above, by storing the additional information to be added to the standard cell output from the commercial AAL chip in a separate external memory and easily extract the additional information of the desired size internal It is an object of the present invention to provide an internal cell generation device of an ATM switch that is configured as a cell and minimizes transmission delay.

In order to achieve the above object, the present invention provides a high-speed memory capable of bidirectional access and connected to a data system bus to store additional information such as routing information and synchronization information, and a length of the additional information connected to the data system bus. Upon receiving the data cell valid signal from the cell matching unit of the external AAL chip and determining the additional information size register to be determined, an address storing the additional information of the corresponding message is generated according to the length of the additional information provided by the additional information size register. An address generator for transferring to the memory, an additional information storage register for storing the corresponding message cell additional information output from the memory by the number of bytes, and an additional information storage register according to the length of the additional information provided by the additional information size register. Send additional information sequentially And a shift register and a matching unit for shifting the ATM standard cell data provided by the external AAL chip cell matching unit by a byte unit and transmitting the internal cell to the ATM switch.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is an internal format format diagram in which additional information is added to the standard ATM, according to the present invention, and the length of the additional information can be arbitrarily selected by the user.

4 is a block diagram of an internal cell generating apparatus to which additional information is added according to the present invention, and includes a high speed memory 401 capable of bidirectional access and connected to a data system bus to store additional information such as routing information and synchronization information; A data cell valid signal connected to the data system bus to determine the length of the additional information through a ATM cell interface from an AAL chip cell delimiter when using an internal self-routing of an ATM switch. When receiving the address information generator 404 for generating an address for storing the additional information of the message according to the length of the additional information provided by the additional information size register 402 to the memory 401 and the memory 401 Additional information storage registers # 1, # 2, ... # N (405) for storing corresponding message cell additional information output from According to the length of the additional information provided by the provisional information size register 402, the additional information input from the additional information storage register 405 is sequentially transmitted, and then the ATM standard cell data provided by the AAL chip cell matching unit is provided in byte units. A shift register and matching section 403 for shifting and transmitting to an ATM switch via an internal cell interface.

Referring to the operation of the internal cell generator configured as described above, the operating system (OS) of the host adapter first determines the number of additional information bytes (N) to be added to the standard ATM cell, and then the additional information size register 402 through the system bus. ) Sets the number of bytes (N) to add. At this time, the additional information size register 402 downloads the number of additional information bytes to the address generator 404, the shift register, and the matching unit 403, and generates a signal as necessary as the additional information number. Then, if there is a packet message sent from 0S, the additional information of the corresponding message is stored in the memory 401 capable of bidirectional access, and the additional information of the corresponding message is stored in the GFC bit located in the first byte of the standard ATM cell header. After storing the reference address of the memory 40l, the packet message to be transmitted is transmitted to the packet memory.

If the cell to be transmitted in the cell transmitter 101 of FIG. 1 is valid, the ATM standard cell first loads the first byte GRC bit and then holds the next data. Since the address generator 404 has no meaning in the GFC bit area in the standard cell format, the address generator 404 generates the address of the memory 401 in which the additional information of the corresponding message cell is stored by the number of additional information N using this bit area as a reference address. In addition, the additional information storage register 405 has to be provided by the maximum number of additional information bytes desired by the user, and temporarily stores additional information to be added to the ATM cell being processed before being transmitted to the shift register and matching unit 403. The corresponding message register additional information output from the memory 401 is stored in the additional information storage register 405 in the order of # 1, # 2, ... # N by the number of additional information bytes. Next, the shift register and matching unit 403 is shifted first by the number N of the additional information storage registers 405, and then the corresponding message standard cell data is shifted to finally output the additional information storage register # 1. After the information storage register # 2, the additional information register #N (# 5), 53-byte standard cell jumbo is output, and the 53 + N-byte internal cell format is transferred.

5 is a timing diagram of states of each additional information storage register, shift register, and matching unit according to the present invention, where 501 is a read clock, 502 is a cell valid signal input to the additional information storage register, 503 is a read valid signal, and 504 Denotes a cell data signal input to the shift register and matching section, and additional information bytes # 1, # 2, ... # N, 506 outputted by the R5 non-additional information storage registers # 1, # 2, ... The information # 1, # 2, ..., #N and internal cell data signals of ATM standard data are respectively shown.

6 is a schematic diagram of the address generator according to the present invention. When the cell data is valid from the cell transmitter 101, the GFC field is read and the address where the additional information of the corresponding message is stored with reference to GFC 4 bits. Generates. It is divided into two functions, and is divided into an address pointer generator for generating an additional information address pointer and an address incrementer for increasing the number of base addresses generated by the additional information address pointer by 1 and increasing it to N. 16 kinds of messages can be processed using 4 bits of GFC area, the first byte of a standard ATM cell.

If the cell data is valid from the cell transmitter 101, the address pointer generator reads 4 bits of the first byte of the ATM cell and generates a base address of the memory where the additional information is stored with reference to this value. The number N of additional information is increased by 1 with reference to the base address. That is, the address of the memory in which the additional information is stored is generated by increasing the base address + (N-1).

By 4 bits of the GFC area, the N-byte side information can be added simultaneously to up to 16 different message standard cells at the ATM cell output unit.

As described above, according to the present invention, by adding routing information to the front end of an ATM cell in an ATM switching system requiring self-routing, additional information can be added using an existing AAL chip, and continuous transmission is minimized. There is an effect that can transmit the inner cell.

Claims (3)

High-speed memory 401 capable of bidirectional access and connected to a data system bus to store additional information such as routing information and synchronization information, and an additional information size register connected to the data system bus to determine the length of the additional information. 402 and an address in which the message external information is stored according to the length of the additional information provided by the additional information size register 402 when receiving a data cell valid signal from a cell matching unit of an external Absolute Assembly Language (AAL) chip. An address generator 404 for generating and transmitting to the memory 401, an additional information storage register 405 for storing corresponding message cell additional information output from the memory 401 by the number of bytes, and the additional information size According to the length of the additional information provided by the register 402, the additional information input from the additional information storage register 405 is sequentially And a shift register and a matching unit 403 for shifting the ATM standard cell data provided by the external AAL chip cell matching unit by a byte unit and transmitting the inner cell to the ATMI switch. Cell generator. The apparatus of claim 1, wherein the additional information storage register (405) is provided by the number of additional information bytes output from the memory (401). The GFC 4 of claim 1, wherein the shift register and matching unit 403 divides an external separate dual access memory into six areas and variably configures a configuration map according to the size of additional information. An internal cell generating apparatus for an ATM switch characterized in that it is configured to output continuous internal cells by attaching additional information to 16 kinds of message standard cells at the same time by cyclically using bits.