KR100233241B1 - Hdsl interface apparatus in atm switching system - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a high speed digital subscriber line matching device.

2. The technical problem to be solved by the invention

The present invention provides a high-speed digital subscriber line matching device that configures an HDSL subscriber matching device having both an HDSL subscriber matching function and an HDSL central processing function in an ATM switching system, and is mounted in the switching system and controlled by a controller in the switching system. To provide.

3. Summary of Solution to Invention

The present invention provides an ATM processing unit for processing an operation maintenance function, a subscriber management unit and an ATM function, a local clock distribution unit for receiving a synthesized signal from a subscriber switching unit, synthesizing and dividing the clock, and supplying a clock to each module, and a subscriber line. And a high speed digital subscriber line processor for performing physical layer processing and central processing functions of the ATM cell.

4. Important uses of the invention

The present invention is used in an asynchronous delivery mode exchange.

Description

High-Speed Digital Subscriber Line Matching Device in Asynchronous Transfer Mode Switch

The present invention provides various ATM services, such as video conferencing, high-speed Internet access, and video on demand, to subscribers using high-bit-rate digital subscriber lines (HDSL) in an asynchronous delivery mode (ATM) switching system. The present invention relates to a high speed digital subscriber line matching device configured in an ATM switching system.

Conventional High Speed Digital Subscriber Line (HDSL) matching devices have HDSL central processing capabilities not mounted within an ATM switching system, but only outside the switching system in the form of bulky boxes. Therefore, the conventional HDSL matching device has to use a separate board having the HDSL subscriber matching function and the HDSL central processing function, so there is a problem in that the HDSL subscriber is not controlled or the state of the HDSL subscriber is not known in the exchange.

In order to solve the above problems, the present invention provides an HDSL subscriber matching device having both an HDSL subscriber matching function and an HDSL central processing function in an ATM switching system, but is mounted in the switching system and controlled by a controller in the switching system. Its purpose is to provide a high speed digital subscriber line matching device.

1 is a block diagram of an asynchronous delivery mode switching system to which the present invention is applied.

2 is a block diagram of an embodiment of a subscriber matching unit according to the present invention;

FIG. 3 is an exemplary view of the high speed digital subscriber line (HDSL) processing unit of FIG. 2; FIG.

* Explanation of symbols for main parts of the drawings

10: subscriber switching unit 21: asynchronous delivery mode layer processing unit

22: local clock distribution unit 23: high-speed digital subscriber line processing unit

24: alarm collecting unit

According to an aspect of the present invention, there is provided a high speed digital subscriber line matching device mounted in a local switching subsystem of an asynchronous delivery mode switching system having a subscriber switching unit. Local clock distribution means for providing a clock to the bus; It is connected to the subscriber switching unit through an internal module connection to transmit and receive differential signal serial data, and to transmit and receive with a plurality of high speed digital subscriber line processing means through a transmit / receive cell bus and a control signal bus, and distribute the local clock through a clock signal bus. Asynchronous delivery mode processing means for receiving a clock from the means; Alarm collecting means for receiving and collecting a hernia alarm signal and a function alarm signal from said asynchronous delivery mode processing means and said local clock distribution means; And the plurality of high speed digital subscriber line processing means for transmitting and receiving data to and from the asynchronous delivery mode processing means through the transmit and receive cell bus and the control signal bus, and receive a clock from the local clock distribution means through the clock signal bus. Include.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a block diagram of an asynchronous delivery mode switching system to which the present invention is applied, in which, "1" represents a local switching subsystem and "2" represents a central switching subsystem, respectively. It has a structure in which one central switching subsystem 2 and a plurality of local switching subsystems 1 are interlocked.

Each local switching subsystem 1 has a subscriber switching section 10, a subscriber matching section 20, a relay line matching section 30, and a subscriber control section 40, with the central switching subsystem 2 connected. The switching unit 50, the network synchronization unit 60, and the maintenance control unit 70 is provided.

Local switching subsystem 1 is subscriber matching section 20 that matches STM-1 (155 Mbps) subscribers, DS3 (45 Mbps) subscribers, DS1E (2 Mbps) subscribers, and HDSL (2 Mbps) subscribers to subscriber switching unit 10. The relay line matching unit 30 for matching the STM-1 (155 Mbps) relay line and the STM-4 (622 Mbps) relay line to the subscriber switching unit 10, and the subscriber matching unit 20 and the relay line matching unit 30. And a subscriber switching section 10 which is connected to the connection switching section 50 in the subsystem 2 and which provides a local timing signal interface (LTSI) to each functional section. It also includes a subscriber control unit 40 that collects alerts of each functional unit in the local switching subsystem 1 and controls maintenance control and call connection. Here, the connection between each functional unit and the central switching subsystem 2 is made through an inter module interface (IMI), and the number of IMIs connected depends on the speed of the subscriber or the relay line. And, subscriber matching section 20 becomes a high speed digital subscriber line matching section when matching with HDSL subscriber.

The central switching subsystem 2 interconnects each local switching subsystem 1 to control the entire system, and generates a network synchronization clock for synchronizing the entire switching system network to give the subscriber switching unit the same period. A network synchronizer that provides an internal module timing access (IMTI) clock of the controller and provides a central timing signal interface (CTSI) clock to the connection switching unit 50 and the maintenance control unit 70. 60, a connection switching unit 50 matching each subscriber switching unit 10 and the maintenance control unit 70, and a maintenance control unit 60 performing maintenance control and operation management functions of the entire switching system. It is provided. Here, the connection between each functional unit and the connection switch network is made through IMI.

2 is a block diagram of an embodiment of a subscriber matching unit according to the present invention.

Subscriber matching unit 20 according to the present invention is a subscriber switching unit 10, asynchronous delivery mode layer processing unit 21, local clock distribution unit 22, high-speed digital subscriber line processing unit 23, and alarm collecting unit 24 It is designed to accommodate 64 HDSL subscriber lines and process ATM cells to provide high speed ATM data service to HDSL subscribers.

The asynchronous delivery mode layer processing unit 21 transmits and receives 187.79 Mbps differential signal serial data to and from the subscriber switching unit 10 through an internal module connection (IMI), and maintains the control unit 70 in the central switching subsystem 2. Interlocked with central control.

Through the transmit / receive cell bus, the asynchronous delivery mode layer processor 21 transmits the 16-bit transmit cell data TCELL0 to TCELL15 and the transmit cell start signal TSOC * indicating the start of the transmit cell. And 16-bit receiving cell data RCELL0 to RCELL15 and a receiving cell start signal RSOC * indicating the start of the receiving cell from the high-speed digital subscriber line processing unit 23. In addition, the cell reception request signals CRREQ0 * to CRREQ15 * are received and polled from the 16 high speed digital subscriber line processing units 23, and the cells are received by the high speed digital subscriber line processing unit 23 which requests the reception of cells in a certain order. The cell reception permission signals CRACK0 * to CRACK15 * are transmitted. At this time, if the received cell is an OAM cell, it processes the operation and maintenance function and transmits the response OAM cell to the HDSL subscriber.

Through the control signal bus, the asynchronous delivery mode layer processor 21 indicates the validity of the address signals EA1 to EA11, the address signals for accessing the dual port RAM (DPRAM) in the high speed digital subscriber line processor 23. The valid signal EAS *, the data valid signal EDS * indicating the validity of the data signal, and the read / write signal ER * W specifying reading and writing of the data are transmitted, and the data signals ED0 to ED7 are transmitted. Send and receive). Also, the sixteen high speed digital subscriber line processing units 23 receive the function alarm signals FUNA0 to FUNA15 and the hernia alarm signals OFFA0 to OFFA15 of the high speed digital subscriber line processing unit 23 as logic high signals. At this time, the hernia alarm signal OFFA_A and the function alarm signal FUNA_A are transmitted to the alarm collection unit 24 as a logic high signal.

Through the clock signal bus, the asynchronous transfer mode layer processor 21 receives the main clock (23.4747 MHz) for clock synchronization in the module from the local clock distributor 22 and the cell bus clock (11.7373 MHz) for synchronization of the transmit / receive cell bus. Receive

The local clock distribution unit 22 receives a 46.9494 MHz local switching subsystem synchronization signal (LTSI) from the subscriber switching unit 10 at an emitter coupled logic (ECL) level, synthesizes and divides a clock, and then divides the clock. Provide the main clock (23.4747 MHz) and the cell bus clock (11.7373 MHz) to the asynchronous delivery mode layer processor 21 via the signal bus, and the main clock, cell bus clock, and 16 to the 16 high speed digital subscriber line processor 23; Provides a frame sync clock (16.386 MHz). In addition, the hernia alarm signal and the function alarm signal are transmitted to the alarm collection unit 24 as a logic high signal.

Through the transmit / receive cell bus, the high speed digital subscriber line processor 23 receives the 16-bit transmit cell data and the transmit cell start signal from the asynchronous delivery mode layer processor 21, and the 16-bit receive cell data and the receive cell start signal. Is transmitted to the asynchronous delivery mode layer processor 21. In addition, if there is a cell to be transmitted to the asynchronous delivery mode layer processor 21, the cell reception request signal for requesting the reception of the cell is transmitted to the asynchronous delivery mode layer processor 21, and the cell reception is allowed from the asynchronous delivery mode layer processor 21. Receiving the signal transmits the receiving cell and the receiving cell start signal to the receiving cell bus.

Through the control signal bus, the high-speed digital subscriber line processor 23 asynchronously transfers the mode layer processor 21 to transmit an address signal, an address valid signal, a data valid signal, and a read / write signal to match with a dual port RAM (DPRAM). Receives data from and transmits and receives data signals. In addition, the function alert signal and the hernia alert signal are transmitted to the asynchronous delivery mode layer processing unit 21.

Through the clock signal bus, the high speed digital subscriber line processing section 23 receives the main clock, the cell bus clock, and the frame synchronization clock from the local clock distributor 22.

3 is an exemplary diagram of a high speed digital subscriber line (ADSL) processing unit according to the present invention, where "31" is a central control unit, "32" is a transmitting cell processing unit, "33" is a receiving cell processing unit, and "34" Denotes a high speed digital subscriber line processor, " 35 ", a transmit / receive cell matcher, " 36 " a control signal matcher, and " 37 "

The transmit cell processor 32 includes a transmit cell controller 321, a virtual path identifier and a virtual channel identifier (VPI / VCI) table unit 322, a transmit cell first-in first-out (FIFO) unit 323, and an asynchronous delivery mode physical layer. A processing unit 324, the receiving cell processing unit 33 includes a receiving cell buffer unit 331, a test cell transmission first-in first-out 332, a reception cell control unit 333, a test cell reception first-in first-out unit 334, And a reception cell first-in-first-out unit 335.

The high speed digital subscriber line processor 23 according to the present invention interworks with the asynchronous delivery mode layer processor 21 via the transmit / receive cell bus and the control signal bus, and with the local clock distributor 22 via the clock signal bus.

The central control unit 31 having a 16-bit processor generates an address signal and various control signals, and transmits and receives data signals. In addition, a clock is supplied into the high speed digital subscriber circuit processing section 23, and a reset signal is generated and provided to each functional section.

The central control unit 31 combines the generated address signals and control signals to designate addresses for devices and registers belonging to each functional unit, a ROM storing a program, and a RAM storing various data ( RAM) to control the high speed digital subscriber circuit processing unit 23, and generates its own loopback test cell and transmits it to the test cell transmission first-in, first-out unit 332 in the transmission cell processing unit 33 via the local bus.

The transmit cell processor 32 is a transmit cell controller 321 for converting a transmit cell received from the transmit / receive cell matcher 35 through a local bus, and a virtual path identifier for storing a conversion table for a line of a point-to-multipoint transmit cell. And a parallel transmission received from the virtual channel identifier (VPI / VCI) table unit 322, the transmit cell first-in first-out unit 323 for temporarily storing the transmit cell input from the transmit cell control unit, and the transmit cell first-in first-out unit 323. An asynchronous transfer mode physical layer processing unit 324 converts the cells in series.

Through the local bus, the transmitting cell control unit 321 transmits and receives a control signal, and receives the 16-bit transmission cell from the transmission and reception cell matching unit 35 and converts it into an 8-bit transmission cell. One of the transmission cell first-in, first-out (323) of the transmission cell first-in, first-out (FIFO) of the transmission cell first-in, first-out (FIFO), and in the case of a point-to-multipoint transmission cell, the virtual path identifier and the virtual channel identifier (VPI / VCI): Virtual Path Identifier / Virtual Channel Identifier) After reading the contents of the table unit 322, the VPI and VCI values are converted and transmitted to one of four FIFOs.

The virtual path identifier and virtual channel identifier (VPI / VCI) table unit 322 stores a conversion table of VPI and VCI values for four lines of the point-to-multipoint transmission cell recorded by the central control unit 31 via the local bus. In the case of point-to-multipoint transmission, VPI and VCI are converted by referring to the transmission cell controller 321.

The transmission cell first-in first-out unit 323 is composed of four first-in first-out (FIFO) to temporarily store the transmission cell received from the transmission cell control unit 321, and then to the asynchronous delivery mode physical layer processing unit 324 composed of four ATM physical layers. To send).

The asynchronous delivery mode physical layer processing unit 324 is composed of four ATM physical layers, converts the parallel transmission cell received from the transmission cell first-in, first-out unit 323 into serial and transmits it to the high speed digital subscriber circuit processing unit 34. Further, serial data received from the high speed digital subscriber circuit processor 34 is converted into a parallel transmission cell and transmitted to the reception cell buffer unit 331 in the reception cell processor 33.

The high speed digital subscriber circuit processing unit 34 is composed of four high speed digital subscriber lines (HDSLs) to code the serial transmission data received from the asynchronous delivery mode physical layer processing unit 324 by a 2 Binary 1 Quarterly (2B1Q) scheme to the HDSL line. And decode the serial data received from the HDSL line by the 2B1Q method and transmit the decoded serial data to the asynchronous delivery mode physical layer processing unit 324.

The reception cell processing unit 33 stores a reception cell buffer unit 331 for buffering the reception cell, a test cell transmission first-in, first-out unit 332 for temporarily storing the self-loopback test cell generated by the central control unit 31, and the received reception. Receive cell control unit 333 for analyzing and converting a cell, test cell reception first-in, first-out unit 334 for temporarily storing a test cell for self-loopback test and then transmitting it to the central control unit 31, and temporarily storing the converted receiving cell. After that, it is composed of a first-in, first-out 335 receiving cell to be transmitted to the transmission and reception cell bus matching unit 35.

The receiving cell buffer unit 331 buffers each of the 8-bit receiving cells received from the asynchronous delivery mode physical layer processing unit 324 including four ATM physical layers and transmits the received cells to the receiving cell control unit 333.

The receiving cell controller 333 analyzes the 8-bit receiving cell received from the receiving cell buffer unit 331, converts the received 8-bit receiving cell into a 16-bit receiving cell, and transmits the received cell to the receiving cell first-in-first-out unit 335.

The reception cell first-in-first-out unit 335 temporarily stores the 16-bit reception cell received from the reception cell control unit 333 and transmits the received 16-bit reception cell to the transmission / reception cell bus matching unit 35.

The test cell transmission first-in, first-out unit 332 temporarily stores the test cell for the self-loopback test generated by the central control unit 31 via the local bus and transmits the test cell to the reception cell control unit 333.

The test cell reception first-in-first-out unit 334 temporarily stores the self-loopback test cell received from the reception cell control unit 333 and transmits the test cell to the central control unit 31 via the local bus.

When the transceiver cell bus matching unit 35 performs its own loopback test under the control of the reception cell control unit 333 in the reception cell processing unit 33, the test cell received from the reception cell first-in-first-out unit 335 is a transmission cell processing unit. A loopback path is formed to be transmitted to the transmission cell control unit 321 in the 32. If the loopback test is not performed, the 16-bit transmission cells TCELL0 to TCELL15 are transferred from the asynchronous transfer mode layer processing unit 21 via the transmission / reception cell bus. It receives and transmits it to the transmission cell control unit 321, and receives the 16-bit reception cells RCELL0 to RCELL15 from the reception cell first-in, first-out 335 and transmits them to the asynchronous delivery mode layer processor 21. In addition, control signals TSOC *, RSOC *, CRREQ *, and CRACK * for transmitting and receiving cells are transmitted and received with the asynchronous delivery mode layer processor 21.

The control signal matching unit 36 is interlocked with the asynchronous transfer mode layer processing unit 21 through the control signal bus to provide 11-bit address signals EA1 to EA11 and various control signals EAS *, EDS *, and ER * W. Receive and transmit and receive the 8-bit data signals ED0 to ED7. In addition, the dual port RAM is configured to communicate with the asynchronous delivery mode layer processor 21, and the function alarm signal FUNA and the hernia alarm signal OFFA are transmitted to the asynchronous delivery mode layer processor 21.

The clock signal matching unit 37 combines the main clock (23.4747 MHz), the cell bus clock (11.7373 MHz), and the frame synchronization clock (16.384 MHz) from the local clock distributor 22 through the clock signal bus. After receiving at the ECL (Emitter Coupled Logic) level, the signal is converted to a transistor-transistor logic (TTL) level and transmitted to the transmit cell processor 32 and the receive cell processor 33 via a local bus.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains, and the above-described embodiments and accompanying It is not limited to the drawing.

As described above, the present invention can be directly controlled through a maintenance control unit in an ATM switching system by connecting a plurality of HDSL subscriber lines (64 in the above-described embodiment) to a high-speed digital subscriber line matching device. It is effective to provide high speed data service in both directions to HDSL subscribers.

Claims (7)

A high speed digital subscriber line matching device mounted in a local switching subsystem of an asynchronous delivery mode switching system having a subscriber switching unit. Local clock distribution means for receiving a synchronization signal from the subscriber switching unit and providing a clock to a clock signal bus; It is connected to the subscriber switching unit through an internal module connection to transmit and receive differential signal serial data, and to transmit and receive with a plurality of high speed digital subscriber line processing means through a transmit / receive cell bus and a control signal bus, and distribute the local clock through a clock signal bus. Asynchronous delivery mode processing means for receiving a clock from the means; Alarm collecting means for receiving and collecting a hernia alarm signal and a function alarm signal from said asynchronous delivery mode processing means and said local clock distribution means; And The plurality of high speed digital subscriber line processing means for transmitting and receiving data to and from the asynchronous delivery mode processing means via the transmit and receive cell bus and the control signal bus and receive a clock from the local clock distribution means via the clock signal bus. A high speed digital subscriber line matching device of an asynchronous delivery mode switch comprising a. The method of claim 1, The high speed digital subscriber line processing means, Central control means for generating an address signal and various control signals, transmitting and receiving data signals, generating a test cell for a loopback test, and transmitting the test signal to each functional unit via a local bus; Transmission cell processing means for converting and temporarily storing the transmission cells received via the local bus and converting the received parallel transmission cells into serial; High speed digital subscriber circuit processing means for coding serial transmission data received from said transmission cell processing means and transmitting them to a line, decoding the serial data received from the line, and transmitting the decoded serial data to said transmission cell processing means; Receiving cell processing means for buffering the received cell and the self-loopback test cell received through the local bus, converting the predetermined number into predetermined bits, and temporarily storing the received cell; Transmission / reception cell matching means for forming a loopback path of a transmission / reception cell or transmitting / receiving with the asynchronous delivery mode processing means via a transmission / reception cell bus; Control signal matching means for constructing a dual port RAM to communicate with said asynchronous delivery mode processing means via a control signal bus, and to transmit a function alarm signal and a hernia alarm signal to said asynchronous delivery mode processing means; And Clock signal matching means for converting the clock received from the local clock distribution means via the clock signal bus and then transmitting the clock signal to the transmission cell processing means and the receiving cell processing means via a local bus. A high speed digital subscriber line matching device in an asynchronous delivery mode switch comprising a. The method of claim 2, The transmission cell processing means, Transmission cell control means for transmitting and receiving a control signal through the local bus and converting a transmission cell received from the transmission and reception cell matching means into a predetermined bit; Virtual path identifier and virtual channel identifier table means for storing a virtual path identifier and a virtual channel identifier value for a line of a point-to-multipoint transmission cell recorded via a local bus; Transmission cell first-in, first-out means for temporarily storing a transmission cell received from the transmission cell control means; And Physical layer processing means for converting the parallel transmission cell received from the transmission cell first-in first-out means into serial A high speed digital subscriber line matching device in an asynchronous delivery mode switch comprising a. The method of claim 2, The receiving cell processing means, Receiving cell buffering means for buffering a receiving cell received from said asynchronous delivery mode physical layer processing means; Receiving cell control means for analyzing the received cell received from the receiving cell buffering means and converting the received cell into a predetermined bit; Receiving cell first-in, first-out means for temporarily storing the transformed receiving cell received from the receiving cell control means; Test cell first-in, first-out means for temporarily storing a test cell for a self-loopback test generated by the central control means via the local bus; And Test cell reception first-in, first-out means for temporarily storing the test cell for self-loopback test received from the reception cell control unit and then transmitting the test cell to the central control unit via a local bus. A high speed digital subscriber line matching device in an asynchronous delivery mode switch comprising a. The method of claim 2, The central control means, A high speed digital subscriber line matching device in an asynchronous delivery mode switch comprising a 16-bit processor. The method of claim 3, wherein The transmission cell converted by the transmission cell control means, A high speed digital subscriber line matching device in an asynchronous delivery mode switch, characterized in that it is 8 bits. The method of claim 4, wherein The receiving cell converted by the receiving cell control means, An asymmetric digital subscriber line matching device in an asynchronous delivery mode switch characterized in that it is 16 bits.

Images