KR100407694B1 - Transmission Performance Tester Of Digital Subscriber Lines Based On ATM - Google Patents

Abstract

The present invention relates to a test device for testing the performance of the network-side signal processing device and the subscriber-side signal processing device interconnected by a virtual line tester, the matching unit for exchanging test signals with the signal processing device of the network and subscriber side ; After generating a predetermined test signal by an external control signal and delivering it to the matching unit, the matching is performed through the virtual line tester first through the signal processing device to be tested, either the signal processing device on the network side or the signal processing device on the subscriber side. A signal controller for comparing the test signal with the signal received through the unit; And a signal processing unit for supplying a control signal to the signal control unit and receiving a comparison result from the signal control unit to analyze the performance of the signal processing apparatus. Since the test can be performed, it is possible to analyze the basic functions and transmission performance of the developed digital subscriber line processing device, which is directly utilized as a development tool of the digital subscriber line processing device.

Description

Transmission Performance Tester of Digital Subscriber Line Processor and Test Method {Transmission Performance Tester Of Digital Subscriber Lines Based On ATM}

The present invention relates to a test apparatus and a test method for testing the performance of the circuit processing apparatus, and in particular, a test that can test the performance of each of the network side and subscriber-side digital subscriber line processing apparatus through one test apparatus It relates to an apparatus and a test method.

Referring to FIG. 1, a schematic configuration diagram for a transmission performance test of a conventional symmetric digital subscriber line processor is shown. As illustrated in FIG. 1, two transmission performance test equipments 100A and 100B are provided in a conventional test device. ), The network side digital subscriber line processor (10A) and the subscriber side digital subscriber line processor (10B) are tested with two frame configurations and signal matchers (11A, 11B) and a virtual line tester (20).

Looking at a specific procedure for testing the performance of the conventional digital subscriber line processing apparatus shown in Figure 1, the network-side transmission performance test equipment (100A) and the frame configuration and signal matching to the transmission data (Tdata_n + /-) of the differential signal level When the transmission data clock (Tclk_n +/-) is input, the frame configuration and the signal matcher 11A receive the signal to form a frame, convert it to the TTL level, and then transmit data (TxD_n), transmission data clock (TxC_n), and transmission. The synchronization signal TxFS_n is sent to the network-side digital subscriber line processing apparatus 10A, where digital subscriber line transmission protocol processing is performed and output as an analog signal.

The virtual line tester 20 simulates and outputs a condition of a line to be tested for an input signal.

The subscriber side symmetric digital subscriber line processing apparatus 10A performs symmetrical digital subscriber line reception protocol processing on the input analog signal to frame the received data RxD_n, the received data clock RxC_n, and the received synchronization signal RxFS_n at the TTL level. If the configuration and signal matcher 11A are given, a frame is formed here, and the data is converted to the differential signal level, and the received data Rdata_n +/- and the received data clock Rclk_n +/- are output to the transmission performance tester.

The transmission performance tester 100A compares this data with a designated bit string, determines whether there is an error, and outputs the result.

Similarly, in the reverse direction, when the transmission data Tdata_s +/- and the transmission data clock Tclk_s +/- of the differential signal level are input to the subscriber side 10B from the test equipment to the frame side and the signal matcher 11B, the output is output here. The TTL-level transmit data (TxD_s), transmit data clock (TxC_s), and transmit synchronization signal (TxFS_s) are input to the test equipment as receive data (Rdata_s +/-) and receive data clock (Rclk_s +/-) through a similar process. Examine this data and print the result.

However, in using the conventional test apparatus as shown in FIG. 1, since general transmission performance test equipment transmits and receives data of a certain frame type at a differential signal level, frame configuration and signal matching between the digital subscriber line processing device and the test equipment Groups 11A and 11B are required.

In addition, the existing digital subscriber line processor test equipment has a differential signal matching structure having a constant frame structure and transmits and receives data at a symmetrical or asymmetrical speed, so that the digital subscriber line processor under test has a constant frame structure and a differential signal. It must be matched, or it must be connected to the test equipment by adding a differential signal matching circuit having a constant frame structure to the outside, and does not provide an environment for testing at various different speeds.

In addition, it was difficult and inconvenient to test because the test configuration was complicated because the test equipment had to have two test equipments, one at each end of the network and one subscriber, and had to be tested using an external test equipment.

In order to solve the problems of the prior art of the present invention, a transmission error in accordance with the data transmission between the network side and the subscriber side of the digital subscriber line processing apparatus in order to enable a high-speed multimedia application service by the digital subscriber line. The purpose of this study is to provide a performance tester and test method for digital subscriber line processing devices that can analyze the basic functions and transmission performance of digital subscriber line subscriber processing devices. .

1 is a block diagram of a transmission performance test of a conventional digital subscriber line processing apparatus.

2 is a transmission performance test configuration diagram of a digital subscriber line processing test apparatus according to the present invention.

* Explanation of symbols for the main parts of the drawings

10A: Digital subscriber line processing device (network side)

10B: Digital subscriber line processing device (subscriber side)

11 processor 12 clock and reset circuit

13: address decoding unit 14: memory unit

15A: AT cell transmission / reception control unit (network side)

15B: AT cell transmission / reception control unit (subscriber side)

16A: Utopia matching unit (network side) 16B: Utopia matching unit (subscriber side)

20: virtual line tester

According to a preferred embodiment of the present invention, a test apparatus for testing the performance of a network-side signal processor and a subscriber-side signal processor interconnected with a virtual line tester is braked. A matching unit for exchanging a test signal with a signal processor; Generates a predetermined test signal by an external control signal and transmits it to the matching unit, and then, through the signal processing device to be tested, first through the virtual line tester through the network line signal processing device or the signal processing device on the subscriber side. A signal controller for comparing the test signal with the signal received through the unit; And a signal processor for supplying a control signal to the signal controller and receiving a comparison result from the signal controller to analyze the performance of the signal processor.

Further, according to another suitable embodiment of the present invention, a test method for testing the performance of the network-side signal processing device and the subscriber-side signal processing device interconnected by a virtual line tester is provided, wherein the test method is a predetermined test signal Generating a test signal; A network signal receiving step of transmitting the test signal generated in the test signal generating step to the network side signal processing device and then receiving the signal through the virtual line tester and the subscriber side signal processing device; A network signal comparing step of comparing a test signal generated in the test signal generating step with a signal received in the network signal receiving step for the network signal receiving step; A subscriber signal receiving step of transmitting the test signal generated in the test signal generating step to the subscriber side signal processing apparatus and then receiving the signal through the virtual line tester and the network side signal processing apparatus; A subscriber signal comparison step of comparing a test signal generated in the test signal generation step with a signal received in the subscriber signal receiving step for the subscriber signal receiving step; And analyzing the performance of the network-side signal processor or the subscriber-side signal processor based on a predetermined criterion based on the network signal comparison step or the subscriber signal comparison step result.

Hereinafter, preferred embodiments of the present invention will be described by way of example only with reference to the accompanying drawings. In the following description, a detailed description of well-known functions and configurations substantially unrelated to the gist of the present invention will be omitted.

2, there is shown a test apparatus 100 in accordance with a suitable embodiment of the present invention. As can be seen from Figure 2, the test apparatus 100 according to the present invention is connected to the network-side and subscriber-side line processing apparatus (10A, 10B), respectively. This embodiment assumes that the circuit processing apparatus 10A, 10B is a digital subscriber line processing apparatus operating on an ATM basis.

The test apparatus according to the present invention is to test the network-side and subscriber-side digital subscriber line processing devices (10A, 10B) through a single test device in order to solve the conventional problems described above, the bidirectional data transmission rate is the same symmetry In addition to digital subscriber line processors, the transmission performance of asymmetric digital subscriber line processors with different up and down data rates can be tested.

As shown in FIG. 2, the test apparatus 100 performs a clock supply and reset function used in the test apparatus around the processor unit 11 to test the ATM cell error rate on the line of the digital subscriber line processing apparatus. There is a clock and reset circuit section 12, an address decode section 13, a memory section 14, which is connected to the local system bus and stores ATM cell data and application programs to be transmitted for testing, ATM from network side to subscriber side There is an AT cell transmitting / receiving control unit 15A and a utopia matching unit 16A for transmitting a cell, and likewise an AT cell transmitting / receiving control unit 15B and a Utopia matching unit 16B for transmitting an ATM cell from a subscriber side to a network side. There is.

In a suitable embodiment according to the present invention, since the circuit processing apparatus 10A, 10B is a digital subscriber line processing apparatus operating on an ATM basis, the physical layer and the upper layer in the ATM protocol are widely known in the art. Connect via

Accordingly, the AT cell transmission / reception control units 15A and 15B and the Utopia matching units 16A and 16B for transmitting and receiving the test ATM cell in both directions by the command of the processor unit 11 are digital subscriber line processing apparatuses 10A and 10B. It is connected to the Utopia bus and transmits and receives high-speed ATM cells to test the transmission performance.

In the present invention, the ATM generates a variable rate ATM cell to test the transmission performance of the digital subscriber line processor, and the receiver receives the total number of received ATM cells, the number of error cells, the number of lost cells, the number of duplicate cells with the same data repeated, And the cell transmission delay.

Referring back to FIG. 2, a test apparatus for a transmission performance test of an ATM-based digital subscriber line processing test apparatus is provided between a digital subscriber line processing apparatus 10A on the network side and a digital subscriber line processing apparatus 10B on the subscriber side. In the same way as the actual digital subscriber line environment, the copper wires are connected, and a line tester 20 is installed at the center of both ends to test transmission performance. The line tester 20 is adjusted to test the line environment such as length, thickness, noise environment and bridge tap of the subscriber line.

The digital subscriber line processing unit 10A on the network side and the digital subscriber line processing unit 10B on the subscriber side are Utopia transmission signals (TxClav, TxEnb, TxSOC, TxData, TxClk) and Utopia reception signals (RxClav, RxEnb, RxSOC, RxData). RxClk) is connected to the test apparatus 10 according to the invention.

The processor unit 10 may use a general-purpose processor, generates data signal lines, address signal lines, and control signal lines, supplies them to the local bus, controls the entire test apparatus using the monitor program of the memory unit 14, and tests Test the transmission performance using the program.

The clock and reset circuit unit 12 supplies a clock for transmitting and receiving an ATM cell in a test apparatus and a clock used by the processor 11, and generates a reset signal for resetting the entire test apparatus at power input and by a reset switch. Supply it to the local bus.

The serial communication port of the processor unit 11 provides a terminal connection function for debugging.

The address decode unit 13 receives an address signal from the processor unit 11 and generates a selection control signal for operation of the corresponding area, and the memory unit 14 stores a basic monitor program and a program for testing. It consists of a ROM for performing data processing and a RAM for storing various data to perform a function of reading or writing data from another controller.

The ATM cell transmission / reception control unit 15A on the network side generates an ATM cell to be transmitted from the network side to the subscriber side for the transmission performance test of the digital subscriber line processing test apparatus 10A by the command of the processor unit 11, thereby producing a utopia matching unit ( 16A) and transmits the transmission data TxD_n and the transmission clock signal TxClk_n.

The network-side utopia matching unit 16B is connected to the digital subscriber line processor 10A and the utopia transmission signals TxClav_n, TxEnb_n, TxSOC_n, TxData_n, and TxClk_n, and receives the ATM cell from the ATM cell transmission / reception control unit 15A. The ATM cell received at the subscriber side through the network-side digital subscriber line processor (10A), the virtual line tester (20), and the subscriber-side digital subscriber line processor (10B) is a Utopia reception signal (RxClav_n, RxEnb_n). , RxSOC_n, RxData_n, RxClk_n) are transferred to the subscriber side utopia matching section 16B of the test apparatus, and the subscriber side utopia matching section 16B is initially networked by the received data RxD_n and the received clock RxClk_n signals. Transfers the ATM cell from the network side to the subscriber side by comparing the transmitted ATM cell with the received ATM cell. Analyze the performance of the digital subscriber line processor against the data.

Similarly, the performance of the digital subscriber line processing apparatus 10B can be analyzed for data from the subscriber side to the network side, and the description of the transmission flow of the ATM cell from the subscriber side to the network side is omitted because it is performed by the same procedure.

The transmission performance test apparatus of the digital subscriber line processing apparatus configured as described above performs a transmission performance test function for data of various speeds.

The test apparatus according to the preferred embodiment of the present invention is a device for analyzing the transmission performance of the digital subscriber line processing apparatus using a test apparatus operating on an ATM basis, and is connected to the digital subscriber line processing apparatus through a utopia interface. The data cell generated by the ATM cell transmitter is transmitted to the digital subscriber line processing device through the utopia interface, and the data cell received through the virtual line tester is connected to the utopia interface through the digital subscriber line processing device and received. By analyzing the transmission performance of the digital subscriber line processing device can be identified.

As described above, the transmission performance test apparatus of the digital subscriber line processing apparatus according to the present invention is directly connected between the network side and the subscriber side of the processing apparatus, and has a variable speed at the transmitter for bidirectional ATM cell transmission performance analysis. Generates ATM cells and allows the receiver to test the total number of received ATM cells, the number of error cells, the number of lost cells, the number of duplicated cells with the same data repeated, and the cell transmission delay. By analyzing the performance, it can be directly utilized as a development tool of a digital subscriber line processor.

The description so far is directed to the preferred embodiments for the understanding of the invention, and the invention is not limited thereto, and is intended to those skilled in the art without departing from the scope and spirit of the appended claims. It is obvious that various modifications and variations are possible.

Claims (10)

In the test apparatus for testing the performance of the network-side signal processing device and the subscriber-side signal processing device interconnected by a virtual line tester, A matching unit for exchanging a test signal with a signal processor of the network side and the subscriber side; After generating a predetermined test signal by an external control signal and delivering it to the matching unit, the matching is performed through the virtual line tester first through the signal processing device to be tested, either the signal processing device on the network side or the signal processing device on the subscriber side. A signal controller for comparing the test signal with the signal received through the unit; And And a signal processor for supplying a control signal to the signal controller and receiving a comparison result from the signal controller to analyze the performance of the signal processor. The method of claim 1, The matching unit includes a first matching unit for exchanging a test signal with the network-side signal processor and a second matching unit for exchanging a test signal with the subscriber-side signal processor. The signal controller generates a first test signal based on a control signal supplied by the signal processor and transmits the first test signal to the first matching unit, and then compares the first signal control unit with the test signal received through the second matching unit. And a second signal controller configured to generate a second test signal according to a control signal additionally supplied, transmit the second test signal to the second matching unit, and compare the test signal with the test signal received through the first matching unit. The method of claim 2, The first and second matching unit is a utopia interface device that provides an interface between the ATM layer and the physical layer, And the first and second test signals are ATM cells transmitted as transmission data (TxD_n) and transmission clock (TxClk_n) signals among utopia transmission signals. The method of claim 3, wherein And the signal processor and the first and second signal controllers are connected by a local bus. The method of claim 4, wherein A clock and reset circuit unit configured to generate a clock for transmitting / receiving an ATM cell and a signal processing unit and a reset signal for resetting a test apparatus, and supplying the reset signal to the local bus; An address decoder which receives an address signal from the signal processor and generates an operation selection control signal for a corresponding area and transmits the selected control signal to the local bus; And And a memory unit configured to store the test program and various data, and to read and write the test program in a test unit. The method according to any one of claims 1 to 5, The virtual line tester is characterized in that the line environment, such as subscriber line thickness, subscriber line length, noise environment and bridge tap can be set arbitrarily. In the test method for testing the performance of the network-side signal processor and subscriber-side signal processor interconnected by a virtual line tester, A test signal generation step of generating a predetermined test signal; A network signal receiving step of transmitting the test signal generated in the test signal generating step to the network side signal processing device and then receiving the signal through the virtual line tester and the subscriber side signal processing device; A network signal comparing step of comparing a test signal generated in the test signal generating step with a signal received in the network signal receiving step for the network signal receiving step; A subscriber signal receiving step of transmitting the test signal generated in the test signal generating step to the subscriber side signal processing apparatus and then receiving the signal through the virtual line tester and the network side signal processing apparatus; A subscriber signal comparison step of comparing the test signal generated in the test signal generation step with the signal received in the subscriber signal receiving step for the subscriber signal receiving step; And And analyzing the performance of the network-side signal processor or the subscriber-side signal processor based on a predetermined criterion based on the network signal comparison step or the subscriber signal comparison step result. The method of claim 7, wherein The test signal generating step is characterized in that the test signal supplied to the network-side signal processing device and the test signal supplied to the subscriber-side signal processing device are generated through separate means. The method according to claim 7 or 8, The test signal is a test method, characterized in that the ATM cell transmitted as a utopia transmission signal. The method of claim 9, And a line environment setting step of arbitrarily setting a line environment such as subscriber line thickness, subscriber line length, noise environment, and bridge tap in the virtual line tester.