RU2269154C1 - Telecommunication multi-functional multiplexer - Google Patents

Abstract

FIELD: computer science, in particular, engineering of device for input-output of information in electronic computing machine, transferred along communication channels for transferring information; in particular, device is meant for acting as an intellectual multi-port telecommunication port of personal computer, used in mode of central transport station in data transfer networks for specialized use.

SUBSTANCE: multiplexer has system block, wherein four-channeled telegraph one-polar and two-polar modules are positioned, as well as four-channeled standard-joint C2 module, bi-impulse one-channeled and two-channeled modules, one-channeled telephone module, m modules of four-channeled asynchronous adapter, group control electronic board, and also block for adjustment and control, and combination board.

EFFECT: expanded functional capabilities, possible increase of number and types of connected input-output channels, possible synchronization with several types of specialized equipment.

4 cl, 4 dwg, 1 tbl

Description

Technical field

This technical solution relates to the field of computer technology, namely, input-output devices in an electronic computer information transmitted through the communication channels of data transmission systems.

State of the art

An analogue of this technical solution is the well-known device Group complex for increasing the reliability of GKPD-16M TU1.700.025, which converts information during its transfer between the electronic computer of the Unified System (EU) of the computer (via the input / output interface of the EU computer) and communication channels (via a multi-channel device signal conversion telephone ШС126 РЮ2.008.016, a multi-channel signal conversion telegraph signal ШС127 РЮ2.008.018 and a device for interfacing with special equipment ШУ129 РЮ2.008.020).

A disadvantage of the known analogue is its bulkiness and the impossibility of pairing special data channels with a personal computer compatible with IBM PC / AT.

The closest analogue (prototype) of the claimed device is also the input / output controller BT01-204 of the personal computer system unit (for example, from the composition of the product 1В563-11 YuKSU.466225.002) containing two RS232 channels (see, for example, the operation manual of YuKSU. 466225.002 OM, section 5, table 5.8 (RS-232 interface)) and performing sequential input-output information.

The disadvantages of the known device are limited functionality, insufficient number of input / output channels, lack of interfacing with special equipment having a C2-SPEC interface (with an expanded set of lines and an algorithm compared to RS-232). The implementation of the required number of input channels by increasing the number of I / O controllers used is limited by the capabilities of the PC slot.

Similar disadvantages from the point of view of interfacing with numerous data transmission channels are also inherent in other PCs compatible with IBM PC / AT and having serial ports (COM1, COM2) with RS-232 interface (see, for example, the motherboard "FS10-ATX") .

SUMMARY OF THE INVENTION

The well-known multifunctional telecommunication multiplexer is built on a modular basis and contains a system unit in which a four-channel telegraphic unipolar (M4TGO) module is located for interfacing the multiplexer with four dedicated or switched four-wire communication channels and converting the logic signals of the multiplexer into current telegraphic packages when transmitting data to communication channels and converting current telegraph packages to logic signals adapted for the multiplexer, when data from the communication channel, a four-channel interface module С2 (М4С2) for electrical matching of single-pole circuits of an internal serial interface (VPI) of a multiplexer with four two-pole circuits of a standard interface С2 (RS-232C), the first group of inputs and outputs of which are connected to buses C2 connecting to physical line, four-channel telegraph bipolar module (M4TGD) for pairing the multiplexer with four dedicated or switched four-wire communication channels when transmitting bipolar current packages mi, the first group of inputs and outputs of which is connected to the C1-TG buses for connecting to telegraph communication channels, a two-channel bi-pulse module (M2BI) for pairing the multiplexer with two dedicated four-wire bi-pulse communication channels and converting logical signals from the multiplexer into a bi-pulse signal when transmitting data to the channel communication and inverse transformation when receiving data from a communication channel, the first group of inputs and outputs of which are connected to buses C1-I connecting to pulse channels, the module is single-channel bi pulse (М1БИ) for pairing the multiplexer with a four-wire dedicated bi-pulse communication channel and converting the logical signals received from the multiplexer at the RS-232C interface into a bi-pulse signal when transmitting data to the communication channel and inverse transformation when receiving data from the communication channel, the first group of inputs the outputs of which are connected to the C1-I bus connecting to the bi-pulse channel, a single-channel telephone module (M1TCH / TF) for pairing the multiplexer with leased and switched telephone communication channels from two wire and four-wire termination and conversion of logic signals of the multiplexer into frequency-modulated signals in accordance with CCITT v 23 recommendations when transmitting data to a communication channel and in converting frequency-modulated signals to logical signals of a multiplexer when receiving data from a communication channel, the first group of inputs and outputs which is connected to the bus C1-PM connecting to the telephone communication channel, as well as the adjustment and control unit (DBK) for regulating the signal level in the communication channel and monitoring its status in a single form factor, the first group of outputs whose input is connected with the first group of four-input module outputs a unipolar telegraph (M4TGO) and the second group with a C1-TGO tires input-output connection to the wire communication channels.

The purpose of this technical solution is to expand the functionality to increase the number and types of connected input-output channels (communication channels), to be able to interface with several types of special equipment, to use personal computers compatible with IBM PC.

The inventive telecommunication multiplexer multifunctional further comprises m four-channel asynchronous adapter modules (MA4A) m structurally located in the multiplexer system unit for implementing channel layer protocols and performing interaction procedures with four communication channels in asynchronous duplex or half-duplex data transmission mode, the first groups of input-output of which are connected via internal serial interface (VPI) with a second group of inputs and outputs of the four-channel module unipolar telegraph (M4TG0), or a module of four channel joints C2 (M4C2), or a four-channel bipolar telegraph module (M4TGD) or a two-channel bi-pulse module (M2BI), a single-channel bi-pulse module (M1BI) and a single-channel telephone module (M1ТЧ / Т) control system (CCGT) for the formation of group trunk signals and special control signals of the internal parallel interface (SPRI) and the implementation of procedures for establishing connections, converting and monitoring data in information reception, the first group of inputs and outputs of which is connected via the internal parallel interface bus (VPRI) with the groups of second inputs and outputs m of the four-channel asynchronous adapter modules (MA4A), an interface card (PS) for matching the CCGT signals of the multiplexer with the ISA control bus PC, structurally located in the PC system unit, the first group of inputs and outputs of which are connected to the second group of inputs and outputs of the group control board (CCGT), and the second group of inputs and outputs is connected to the system ISA bus for personal computer compatible with IBM PC.

The interface card (PS) contains the first register (RG), the input of which is connected to the ISA bus (A [0-19]), and the output with the first input of the group control board (CCGT), the first decoder (DS), the first and second inputs of which connected to the first (CS MEM) and second (CS 10) inputs of the CCGT unit, the first bus driver, the first group of inputs and outputs of which are connected to the ISA bus (D [0-15]), the CS input with the output of the first DS decoder, and the group outputs D [0-15] with the corresponding inputs of CCGT, the second bus driver ShF, the first group of five inputs connected to the bus ISA (MEM (R), MEM (W), IOR, IOW, AEN), the sixth input with the IRQ output [10] of the group control board, five outputs are connected to the inputs of the MEM (R), MEM (W), IOR, IOW, AEN of the group control board, and the sixth output with the ISA IRQ bus [10], the I / O CH RDY signal circuit from the CCGT is connected to the corresponding ISA bus circuit.

The group control board (CCGT) contains a third bus driver, the two inputs of which are connected respectively to the outputs A [0-19], AEN of the interface card (PS), and the first output with the bus AID A [13-19], the fourth bus driver, four the inputs of which are connected respectively to the outputs MEM R, MEM W, IOR, IOW of the interface card (PS), a second decoder, three inputs of which are connected respectively to the first output of the third bus driver and two outputs of the fourth bus driver, and two outputs, respectively, to the bus [0-7], PB_RS / RU [0-7], t there is a decoder, two inputs of which are connected respectively to the first ША [0-19] and second AEN outputs of the third bus driver, and three outputs, respectively, to the ВПРИ ДДП bus and the CS MEM and CS I / O outputs of the PS interface card, the first CRC interrupt controller, the two inputs of which are connected respectively to the third output of the second decoder and the VPRI IRQ bus [0-7], the fifth bus driver (BF), the first input of which is connected to the VPRI MEM W bus, the sixth bus driver (BF), the two inputs of which are connected respectively to output of the first controller and with the output I / O CH RDY, and two outputs, respectively, with the inputs IRQ [10] and I / O CH RDY of the interface board, the second WG interrupt register, the three inputs of which are connected respectively to the second output of the first interrupt controller D [0-7 ], the output of the fifth bus driver D [0-15] and the MEM W VPRI circuit, the fourth output of the fourth bus driver and the MEM R VPRI MA4A, and the output with the input D [0-15] of the interface card PS.

The four-channel asynchronous adapter module (MA4A) contains a pulse generator G, a central processor, the first input of which is connected to the output of the pulse generator, a buffer register, two inputs of which are connected respectively to bus A [0-19] and the second output of the central processor, the eighth bus driver, two inputs of which are connected respectively to the D bus [0-13] and the second output of the central processor, and the input-output with the VPI bus of the four-channel asynchronous MA4A adapter module, a pulse shaper whose input and output connected respectively to the second output of the central processor and the RRPA bus STB_BR, a bus amplifier, the two inputs of which are connected respectively to the RRPA bus A [0-16] and the second output of the central processor, and the output is connected to the output of the BR buffer register, random access memory, first input which is connected to the output of the buffer register A [1-11], and the output to the VPI bus of the four-channel asynchronous adapter module, the fifth interrupt vector decoder, the input of which is connected to the output of the buffer register A [0, 12, 19], and the first output to the second m input of random access memory, read-only memory ROM, the input of which is connected to the second output of the fifth decoder of the interrupt vector, and the output is connected to the VPI bus of the four-channel asynchronous adapter module, the fourth DS decoder, the two inputs of which are connected respectively to output A [4-6] and the third output of the central processor, asynchronous serial ports (АПП 0-3), two inputs of which are connected respectively to the first output of the fourth decoder and the VPI bus D [0-7], and the first output with one of the input in the samples of the multichannel asynchronous adapter module, the seventh bus driver, whose two inputs and outputs are connected respectively to the VPRI and VPI output and input, and the input with the third input of the central processor, the input-output register, three inputs of which are connected to the VPRI D bus [0- 7] and RV_RS / RU and the first output of the fourth DS decoder, the first input-output with the VPI bus of the four-channel asynchronous adapter module, the second interrupt controller, six inputs of which are connected respectively to the second and third outputs of the I / O register a, the second output of the asynchronous serial port, the third and fourth outputs of the fourth decoder and the third output of the central processor, and the output with the second input of the INT of the central processor, an address setting circuit, an address comparison circuit, the three inputs of which are connected respectively to the VPRI PDP bus and A [13 -15] and the output of the address setting circuit, the BUF buffer, the two inputs of which are connected respectively to the EXTR bus MEM (R) and MEM (W), the first trigger (T), the two inputs of which are connected respectively to the outputs of the address and buffer comparison circuits, the second tr gger, two inputs of which are connected respectively with the output of the first flip-flop and the output of the pulse generator, and two outputs respectively to the third input HOLD CPU and bus VPRI I / O CH RDY.

List of drawings

Figure 1 shows the structural diagram of a multiplexer telecommunications multifunctional.

Figure 2 shows the structural diagram of the interface board.

Figure 3 shows the structural diagram of the group control board.

Figure 4 shows the structural diagram of the module adapter four-channel asynchronous.

An example embodiment of the device

The telecommunication multiplexer multipurpose (Fig. 1) contains a interface card (PS) 1, a system unit that houses a group control board (CCGT) 2, four-channel asynchronous adapter modules (MA4A) 3, a four-channel telegraph unipolar module (M4TG0) 4, a four-channel module interface С2 (М4С2) 6, four-channel telegraph bipolar module (М4ТГД) 7, two-channel bi-pulse module (М2БИ) 8, single-channel bi-pulse module (М1БИ). 9, a single-channel telephone module (М1ТЧ / ТФ) 10 and an adjustment and control unit (DBK) 5 in a separate construct, the ISA PC system bus 11, the internal parallel interface of the system module 12, as well as the following buses for connecting to communication channels (КС): bus C1-TG0 connecting to telegraph communication channels 13, bus C2 14 connecting to a physical line, bus C1-TG connecting to telegraph channel 15, bus C1-I connecting to pulse channel 16, bus C1-TCH connecting to telephone communication channel 17.

The interface card (PS) (Fig. 2) contains the first register (WG) 18, the first decoder (LH) 19, the first bus driver (BF) 20, the second bus driver (BF) 21, the ISA 11 bus and the interface bus with the group card Management (CCGT) 22.

The group control board (CCP) (Fig. 3) contains a third bus driver (BF) 23, a fourth bus driver (BF) 24, a first interrupt controller (CRC) 25, a fifth bus driver (BF) 26, a sixth bus driver (BF) 27, the second and third decoders (LH) 28, 29, the second register (WG) 30.

The four-channel asynchronous adapter module (MA4A) contains a pulse generator (G) 31, a central processor (CPU) 32, a bus amplifier (ШУ) 33, a seventh bus driver (ШФ) 34, an input-output register (RVV) 35, an address setting circuit ( SZA) 36, address comparison circuit (SSA) 37, buffer (BUF) 38, pulse shaper (FI) 39, buffer register (BR) 40, eighth bus shaper (BF) 41, fourth decoder (DS) 42, second interrupt controller (CRC) 43, first trigger (T) 44, random access memory (RAM) 45, fifth interrupt vector decoder (DSWP) 46, post memory accessory (ROM) 47, asynchronous serial ports (APP) 48, second trigger (T) 49, internal serial interface (VPI) 50.

The multifunctional telecommunication multiplexer (hereinafter referred to as the multiplexer) is designed to operate as an “intelligent” multi-input telecommunication port of a personal electronic computer (PC) used in the mode of a nodal transport station in special-purpose data networks.

The multiplexer provides, together with the control PC, interaction with communication channels in accordance with the protocols of information exchange of the physical, channel, network and transport levels. In this case, the transport and network levels are implemented by the control PC software. The physical and channel levels of interaction with communication channels are implemented by the hardware and internal software of the multiplexer.

The multiplexer in combination with a PC and software forms a transport station, providing:

- the formation of special application files with routing and address information;

- establishment of physical and logical connections in data transmission networks;

- file transfer between host and subscriber computers in the message switching mode using control points (recovery in case of communication channel failures);

- automatic transition to the backup communication channel in case of failure of the main channel;

- background forwarding of service messages in any of the directions with the issuance of an audio signal about incoming correspondence without stopping the main information exchange;

- compression and decompression (archiving and dearchiving) of transmitted information;

- control of file transfer by checksum and cyclic numbers of messages (frames);

- maintaining static information (log) with documenting the names and parameters of the transmitted and received files and information about the process of their transportation.

Telecommunication software TS_NET RDPI.00261-02 (certificate of official registration of the computer program No. 2000610629) can be used as a software tool for controlling the operation of the multiplexer, and the multiplexer is tested by the test software TS_NET RDPI.00324-01 (certificate No. 2000610625).

To fulfill the specific requirements for the organization of communication, the multiplexer can be delivered in various versions, differing in the number of system units, the method of connection to a PC, the number of communication directions and the types of channels served.

The main technical characteristics of the multiplexer are given in the table.

Parameter Name Specifications Type of connected PC IBM PC compatible Type of interface with a PC ISA 16 (8) bit bus PC exchange mechanism Two-input random access memory in a personal computer memory grid, a group of exchange registers, two-way interrupt mechanism PC interrupt number used by the multiplexer IRQ10 PC address space used by the multiplexer D0000 - DFFFF Address space I / O PC used by the multiplexer 1C0 - 1CF, 1B0 - 1BF Communication channel data mode Synchronous, asynchronous Total number of duplex communication lines organized 4-32 Type of linear joints of data transmission equipment Joint C1-I (bipolar packages with excessive transcoding into a bi-pulse signal); joint C1-TG (unipolar telegraphic packages of direct current); joint C1-TG (bipolar telegraph) Line rate provided by line adapters 50 to 9600 bps

The multiplexer includes:

- a system unit (s) designed to install modules, power supply boards;

- built-in modules and boards 2-4, 6-10 designed for hardware and software implementation of telecommunications exchange procedures and ensure physical interaction with signals in accordance with the types of connected joints;

- interface card (PS) 1;

- adjustment and control unit (DBK) 5.

The range of embedded modules and boards includes:

- group management board (CCGT) 2;

- four-channel asynchronous adapter module (MA4A) 3;

- module single-channel bi-pulse (M1BI) 9;

- module four-channel telegraph unipolar (M4TG0) 4;

- single-channel telephone module (M1TCH / TF) 10;

- module four-channel telegraph bipolar (M4TGD) 7;

- module four-channel standard joint C2 (M4C2) 6;

- module two-channel bi-pulse (M2BI) 8.

The number of directions of information exchange implemented in the system unit, as well as the number of system units used (no more than three) are determined by the version of the multiplexer.

The multiplexer structure is implemented in accordance with the modular construction principle and provides the maximum possibility of configuration and adaptation of the device to the conditions of a specific application. The set of functional modules included in the multiplexer includes group modules (general purpose modules), linear control modules (linear adapters) and signal conversion modules.

The functional basis for constructing a multiplexer is a multi-level microprocessor structure, focused on the implementation of multi-channel information exchange via communication channels and consisting of functional electronic modules interconnected by interface connections.

The hardware-software interaction of the multiplexer with the control PC is organized through the standard system bus ISA PC IBM PC AT. Information communication is carried out both through the RAM of the multiplexer, located in the address grid of the computer processor, and through a set of independent I / O ports accessible from the PC side. Information service requests coming from the multiplexer are processed by the standard PC priority interrupt mechanism.

The CCGT group control board and the interface board between the PC and the PC system trunk provide the multiplexer to interact with the control PC and are unchanged in any configuration when connected to the PC via its internal parallel interface.

Group modules are the main "intelligent" elements of the multiplexer and are intended for hardware-software implementation of procedures for establishing connections, converting and monitoring data in the process of transmitting and receiving information.

Signal conversion modules provide physical pairing of linear adapters (LA) with linear joints of connected data transmission equipment.

The multiplexer structure involves interface communications of the following types:

- system bus ISA PC PC 11;

- RS-232C PC PC AT interface;

- internal parallel interface of the system module (SPRI) 12;

- internal serial interface of the system module (VPI) 50;

- linear joints of data transmission equipment 13-17.

The signals of the PC system bus are transmitted to the group control board, which on their basis generates signals of the internal parallel interface (VPRI). VPRI is a system of electrical circuits and signals, including data, address, control and power lines, combining typical installation locations (interface connectors) of the system board switching board.

The Internal System Interface Parallel Interface (VLSI) is a simplified version of the ISA system bus for a PC compatible with IBM PC AT.

1. Group trunk signals:

D [0-15] - data highway;

A [0-19] is the address highway;

OUT - permission to transmit the high byte of data, which, together with the least significant bit of address A [0], determines the format of the data transmitted over the bus.

2. Control signals of operations of access to memory and input-output ports:

IOR - Read Port command;

IOW - "Record Port" command;

MEMR - Read Memory command;

MEMW - "Write Memory" command.

3. General control signals are relayed from the PC system bus:

AEN - resolution of the address of the RAP. In this case, the sources of the address and system bus commands are logically disconnected in order to allow data transmission over the RAP channel;

PDP - direct memory access (PDP);

RESET - reset;

I / O CHR DY - system bus availability.

4. Special control signals ARE:

IRQ LA - interrupt the logical adapter;

PRQ LA - confirmation of interrupt processing from a logical adapter;

PNU LA - forced initial installation of the logical adapter;

PV LA - forced selection of the logical adapter;

T - transmission direction;

EZ - transmission permission.

The electrical and logical interaction of the adapter modules with the signal conversion modules is carried out through the communication system of the internal serial interface (VPI), similar to the RS-232 interface with a reduced set of circuits.

The internal serial interface of the system module (VPI) is a simplified version of the RS-232C interface.

VPI contains a set of signals corresponding to the minimum (9-pin) nomenclature of RS-232C interface signals:

Chain number Name one 102 Signal Ground 2 103 Transmitted data 3 104 Received Data four 105 Transfer request 5 106 Ready to transfer 6 107 ADF (data transmission equipment) is ready 7 108.1 Connect the ADF to the line 8 109 Received Linear Data Detector 9 125 Call indicator

The group control board (CCGT) is designed to form group trunk signals and special control signals of the internal parallel interface.

The interface card (PS) is designed to coordinate the signals of the group control board (CCGT) of the multiplexer with the ISA 11 system trunk of the host PC.

Main characteristics of the interface board:

- address bus - twenty-bit;

- The data bus is sixteen-bit.

The MS board relays trunk signals (data highway D [0-15], address highway A [0-19]), control signals for accessing memory and input / output ports ("MEMW", "MEMR", "IOW", " IOR "), common control signals (" AEN ") and interrupt request (" IRQ10 ").

The four-channel asynchronous adapter module (MA4A) is a specialized microprocessor controller designed for the implementation of data link protocols and procedures for interacting with communication channels.

The main characteristics of the module:

- number of served communication channels - four; - data transfer mode - asynchronous; - transmission rate in the communication channel - 50, 100, 200, (bps) 300, 600, 1200,   2400, 4800, 9600; - type of work - duplex,   half duplex

The internal software of the module is stored in a program located in the ROM, and consists of two main parts:

- module test;

- communication channel maintenance programs.

The test program includes:

- microprocessor check;

- RAM check;

- checking the interrupt controller;

- check the asynchronous serial port on four channels.

The communication channel maintenance program provides:

- transmission (reception) of information blocks to (from) the communication channel (a) via asynchronous serial ports;

- implementation of procedures for establishing a physical connection;

- synchronization of the processes of information exchange of the lower and upper levels of the software of the transport system with the organization of input and output information buffers;

- implementation of algorithms for anti-interference coding and error correction in information coming from the communication channel.

The four-channel interface module C2 M4C2 6 is designed for electrical coordination of circuits of the internal serial interface with two-pole circuits of the standard interface C2 (RS-232C).

The main characteristics of the module:

- the number of external devices connected at the junction C2 - 4;

- the number of chains formed at each junction is 9;

- the parameters of the module in terms of pairing with the joint C2 - according to GOST 23675-79.

The module is a set of amplifier-transmitters and amplifier-receivers that provide the conversion of single-pole TTL levels into bipolar (plus 12 V, minus 12 V) interface levels C2.

Logical level “1” at junction C2 corresponds to minus 12 V, and logic level “0” corresponds to plus 12 V.

The single-channel telephone module M1TCH / TF 10 is designed to interface the multiplexer with leased and switched telephone communication channels with a two-wire and four-wire end.

The main characteristics of the module: - connection to the multiplexer - at the junction of the serial interface (RS-232C); - speed of work - 600, 1200 bit / s; - type of communication channel - switched telephone with a two-wire end, rented with a two-wire end, rented with a four-wire end; - a method of transmitting information in a communication channel - asynchronous, synchronous duplex over a four-wire communication channel, asynchronous half duplex over a switched telephone and leased communication channel; - method for modulating a discrete signal - frequency according to CCITT v23 - transmission level - in a switched telephone channel from minus 15 to 0 dB, in a rented four-wire channel from minus 43 to minus 15 dB; - reception level - in a switched channel from minus 43 to 0 dB, in a rented four-wire channel from minus 30 to minus 0 dB; - dialing method in a switched telephone channel - pulse; - operating modes - operating mode "DATA", control modes "LINE" (loop control from the RS-232C interface) and "Loop US" (loop control from the line side).

The principle of operation of the module is to convert the logic signals of the multiplexer into frequency-modulated signals in accordance with CCITT v23 recommendations when transmitting data to the communication channel and to convert the frequency-modulated signal to logical signals adapted for the multiplexer when receiving data from the communication channel.

Structurally, the module consists of the following functional blocks:

- interface unit at the junction C2;

- a transmitter unit of a frequency-modulated signal;

- receiver unit of a frequency-modulated signal;

- a unit for interfacing with a telephone channel.

The structure of the interface unit at the junction C2 includes:

- receivers that convert the signals along the circuits "108", "105", "103", having the parameters of TTL circuits, into signals with the parameters of circuits with a power supply of 12 V, transmitters that convert signals with parameters coming from the module into signals with parameters TTL circuits in the circuits "107", "106", "104", "109", "114", "115", "125".

The frequency-modulated signal transmitter consists of a crystal oscillator, a modulator, a step signal shaper and a low-pass filter that suppresses by-products of the data signal. The crystal oscillator generates a highly stable signal with a frequency of 2400 kHz. The modulator is a switch based on the value of information (circuit "103"). The division ratio of the switchable divider, in addition to the information value, is determined by the state of the circuit "111". So in the “ON” state of the “111” circuit, the information “0” corresponds to the division coefficient 143, the information “1” - 231. The division coefficient of the switchable divider is changed for a period 88 times less than the period of the data signal, which is equivalent to phase-wise modulation by an angle from 0 to 4. Thus, a "phase-free" phase of the frequency-modulated signal during transmission is ensured.

The stepwise formation of the data signal is carried out at an accelerated frequency. This allows sufficient suppression of formation by-products using a relatively simple low-pass filter. The state "OFF" in the circuit "105" blocks the operation of the driver, and therefore the entire transmitter.

The frequency-modulated signal receiver consists of a band-pass filter, an amplifier-limiter, a frequency detector of a post-detector filter with a threshold device, a 250 divider with a control circuit, a level detector, and a filter at a frequency of 2600 Hz. The band-pass filter separates the data signal from the noise of the communication channel. The frequency detector generates a logic signal "1" of a given duration after any change in the polarity of the signal at the output of the amplifier-limiter and the signal of a logical "0" until the next polarity change. The duration of the logical 1 signal is selected in such a way that when a signal is received with an average frequency of 1700 Hz, a signal with a duty cycle of 2 will be generated at the output of the frequency detector, and with a frequency of “pressing” and “squeezing”, the duty cycle will decrease and decrease, respectively.

A post-detector filter with a threshold device extracts a constant component from the signal from the output of the frequency detector and generates asynchronous reception information.

The level detector generates a signal in the circuit "109". The state "ON" in the circuit "109" is maintained until the level of the received signal is more than minus 43 dB.

The unit for interfacing with communication channels at the junction C1 consists of two adjustable amplifiers - transmission and reception, four keys, two matching transformers, a line holding and dialing unit, a relay for connecting to a communication channel, a station response signal receiver, a CALL signal receiver, switches, s with the help of which various operating modes are set.

The call signal, with a frequency of 16 to 50 Hz, is processed by the module, forming a signal along the "125" circuit. If necessary, make a call from this module, the circuit "108" is transferred to the state "ON". At the same time, the signal “Station Response” begins to arrive at the input of the receiver, putting the circuit “109” into the “ON” state. After that, you can start dialing, which is carried out on the chain "103". The operation of the transmitter and receiver is controlled by a signal in the circuit "105". When the circuit "105" is turned on, the transmitter works, and the signal from its output through the key, an adjustable amplifier and a transformer enters the communication channel. When the "105" circuit is off, the transmitter’s operation is blocked, and through the opened key the communication channel is connected to the input of an adjustable reception amplifier.

When working on a leased channel with a four-wire end, an amplifier is included in the transmission circuit, the transmission is through a T1 transformer, and reception is through a T2 transformer.

The single-channel bi-pulse module (M1BI) 9 is designed to interface the multiplexer with a dedicated four-wire bi-pulse communication channel, including closed special equipment.

The single-channel bi-pulse module converts the logical signals received from the multiplexer into a bi-pulse signal when transmitting data to the communication channel and converts the bi-pulse signal into logical signals adapted for the multiplexer when receiving data from the communication channel.

The main technical characteristics of the module: - connection to the multiplexer - at the junction of the serial interface (RS-232C); - speed of work - 1200, 2400, 4800, 9600 bps; - type of communication channel - dedicated with a four-wire termination; - a method of transmitting information in a communication channel - synchronous four-wire duplex; - method for modulating a discrete signal - bipolar packages with excessive transcoding into a bi-pulse signal; - the nominal amplitude value of the bi-pulse signal during transmission - 0.5 V; - the amplitude value of the bi-pulse signal when receiving - 0.05 V

Structurally, the module consists of the following blocks:

- a block of pairing receivers;

- block transmitter pairing

- block buffer;

- a clock generator unit with a divider;

- block encoder bi-pulse signal;

- block decoder bi-pulse signal;

- line transmitter unit;

- line receiver unit.

The composition of the buffer block includes:

- receivers and interface transmitters at the junction C2 along the circuits "Ts103", "Ts104", "Ts106";

- input registers with controls for "re-linking" asynchronous information to a synchronous clock frequency.

The clock generator is a highly stable crystal oscillator with a divider. At different operating speeds, different frequencies are required, which are obtained at the output of the divider. The division ratio of the divider is set using the switch.

In the encoder block of the bi-pulse signal, the data signal is converted into a bi-pulse signal. Symbols "0" and "1" of the data signal are transmitted in the clock interval by two pulses of equal duration and opposite polarity. The alternation order of the polarity of the pulses compared to the previous clock interval does not change when transmitting the character "1" and changes when transmitting the character "0". The bi-pulse signal passes through a digital filter in order to form the edges of the pulses transmitted in the line to exclude high-frequency components of the signal spectrum. Depending on the speed of operation, the switch selects correcting capacitors.

The linear parts of the receivers and transmitters provide galvanic isolation and symmetry of the input and output circuits of the module.

The bi-pulse signal received from the channel from the output of the comparator, normalized to logical levels, is fed to the decoder of the bi-pulse signal.

For proper decoding, the tuning clock frequency is used. It is formed using phase adjustment of the frequency for the edges of the received signal. The decoded information is input to the buffer transmitter.

The two-channel bi-pulse module (M2BI) 8 represents two independent sub-modules for converting signals similar to the single-channel bi-pulse module (M1BI) and serves to convert logical signals coming from the multiplexer at the RS-232C interface into bi-pulse signals when transmitting data to one of two communication channels and conversion of bi-pulse signals into logical ones adapted for the multiplexer when receiving data from communication channels.

The four-channel telegraph bipolar M4TGD 7 module or the four-channel telegraph unipolar M4TGO 4 module is designed to interface the multiplexer with four dedicated or switched four-wire communication channels.

The main characteristics of the module: - connection to the multiplexer - at the junction of the RS-232C serial interface; - speed of work - from 50 to 200 bit / s; - number of communication channels - four; - type of communication channel - dedicated or switched four-wire; - method for modulating a discrete signal - bipolar packages with parameters corresponding to GOST 22937-78, or unipolar current and non-current packages; - a method of transmitting information to each communication channel - asynchronous duplex; - current value with currentless packages - no more than 2 mA; - current value for current transmissions - no more than 50 mA

The principle of operation of the module is to convert the logic signals of the multiplexer into current telegraphic packages when transmitting data to communication channels and to convert the current telegraphic packages to logical signals adapted for the multiplexer when receiving data from communication channels.

Functionally, the module consists of the following blocks:

- communication unit with telegraph channels;

- a unit for converting C2 interface signals (RS-232C) to standard TTL levels and vice versa.

The module is controlled by the input logic signals "Ts105" and "Ts108". The combination of the states of these signals determines the following three modes of operation of the module:

1) "Ts105" - "1", "Ts108" - "1". This is the initial mode in which only reception of information from the channel is allowed, there is no operating current in the transmission line, information is prohibited;

2) "Ts105" - "1", "Ts108" - "0". This is the mode of readiness for transmission, in which, along with the permission to receive information from the channel, a working current flows in the transmission circuit, although transmission itself is still prohibited;

3) "Ts105" - "0", "Ts108" - "0". This is the operating mode of duplex communication with channels, in which reception and transmission are simultaneously allowed.

The operation of the module with telegraph channels is possible in two versions:

1) unipolar - with current and non-current packages;

2) bipolar - bipolar pulses in accordance with GOST 22938-78.

Changing the operation option is carried out by soldering the jumpers in the module board.

The module consists of the following parts:

- switching power supply;

- four similar transceiver circuits for channels 0, 1, 2, 3;

- a communication node with the MA4A module;

- a communication node with a channel for the implementation of a unipolar version.

The switching power supply of the module is designed to generate eight constant voltages of 20 V, providing independent power supply to the four nodes of formation and stabilization of the reception current and four nodes of formation and stabilization of the transmission current.

The transceiver paths for channels 0, 1, 2, 3 are used for receiving from the telegraph line and transmitting information packets to the adapter and vice versa. The transceiver paths for all channels are the same.

The transmitter unit consists of the following functional units:

- schemes for generating input signals of shapers of parcels;

- schemes for the formation of positive premises;

- schemes for the formation of negative premises;

- pairing circuitry for the shapers of the parcels with the line;

- circuits for limiting the short circuit current in the line.

The receiver unit consists of the following functional units:

- schemes for receiving and generating input signals;

- registration schemes for received data;

- schemes for generating output signals.

The communication node with the MA4A module is designed to convert unipolar TTL levels of the group adapter signals to bipolar pulses plus / minus 12 V transceiver paths and vice versa.

The transmitter-receiver circuit for operation in a unipolar channel mode consists of the following nodes:

- linear transmit and receive filters;

- linear diode rectifiers for transmitting and receiving, ensuring the insensitivity of the circuit to the polarity of the line connection;

- schemes for the formation and stabilization of transmission and reception currents, providing a potential separation of logical and linear circuits, control of current conditioners and stabilization of the established current values.

The multiplexer works as follows.

Functioning is carried out in two modes:

- transmission of information from the PC to the communication channel;

- receiving information from a communication channel in a PC.

Broadcast.

For each channel of the multiplexer in the RAM random access memory of the four-channel asynchronous MA4A 3 adapter module, two transfer buffers and two receive buffers are allocated. The information block in the PC is prepared on the ISA 11 bus.

From the PC, the information block is placed in the transmission buffer as follows. The address on A [0-19] of the ISA bus is set, which passes to the interface board PS 1 through the first register of RG 18, the third bus driver ShF 23, bits A [16-19] are analyzed by the third decoder DSH 29. If the address matches the memory area D0000 produces CSMEM and DMA signals. The CSMEM signal is fed to the first DSh 19 decoder in the interface card and enables the first bus driver SHF 20. The DMA signal is sent to MA4A 3 in the SSA 37 address comparison circuit. In SSA 37, signals A [13-15] together with the DMA signal are compared with the values defined in the circuit for setting the address of SZA 36. When comparing the input D of the first trigger T 44 receives an enable signal. The PC sets the recording signal MEMW, which passes through the second bus driver ShF 21, the fourth bus driver ShF 24, the buffer BUF 38 and is fed to the input from the first trigger T 44. At the second trigger T 49, synchronization with the internal frequency MA4A 3 is made, a request is generated for direct access HOLD, which enters the central processor of the CPU 32. The CPU 32 completes the current cycle, puts its outputs in an inactive state, sets the signal HLDA - confirmation of the permission of direct access, which translates the buffer register BR 40, seventh oh the bus driver ShF 41 in an inactive state and allows the passage of signals A [0-16] through the bus amplifiers SHU 33. Address A [0,12,19] in the fifth decoder of the interrupt vector DShVP 46 generates a cell selection of random access memory RAM 45, address And [1-11] selects a memory cell. Data D [0-15] passes from the ISA 11 bus through the BF 20, BF 26, the VPRI interface 12, the sixth bus driver ShF 34 and is written to RAM 45. Thus, the whole block is transferred sequentially from the PC to MA4A 3. Then, the central processor CPU 32, under the control of a driver located in the read-only memory ROM 47, selects one byte one by one and writes it to the APP 48 asynchronous serial port. The APP 48 issues a byte in the serial code, assigns START and STOP bits. This byte arrives at one of the signal conversion modules (M4TG0 4, adjustment and control unit BRK 5, M4S2 6, M4TGD 7, M2BI 8, M1BI 9, M1TCH / TF 10), where a linear signal of a certain type 13-17 is formed for transmission to link.

Reception

Information from the KS communication channels is fed into one of the modules 4-10, where a linear signal of the form 13-17 is converted into an RS-232 interface signal and fed into the asynchronous serial port of the APP 48, which receives bytes, issues an interrupt request to the second CRC interrupt controller 43. CRC 43 generates an interrupt request INT, which is sent to the central processor CPU 32. CPU 32 completes the current cycle, issues two INTA signals, through which CRC 43 sets the number to the asynchronous serial port of the APT 48, from which the interrupt came. After that, the CPU 32 takes the byte of data from the APP 48 via the VPI 50 internal serial interface, the seventh bus driver ShF 41. After receiving the entire data block, the CPU 32 exposes the address of the input-output register RVV 35 on the fourth decoder DS 42 and writes the address into it, determining that the unit is ready for transfer to a PC. RVV 35 generates an IRQ signal [10], which through the fifth and sixth bus drivers 27, 21 enters the PC. A PC polls the first KPR 25 interrupt controller, reading the MA4A 3 number from which the interrupt came. After that, the PC reads the contents of the I / O register RVV 35 and starts receiving the data block.

The PC sets the address to bus A [0-19] ISA 11, which passes through the first register of WP 18 and the third bus driver ShF 23. Analyzes the state A [16-19] in the third decoder DS 29. When the address matches the contents of the D0000 area, SCMEM and DMA signals. The SCMEM signal enters the first decryptor DSH 19 and enables the first bus driver SHF 20. The LDP signal is sent to MA4A 3 in the SSA 37 address comparison circuit. The contents of the address A bus [13-15] are compared in the SSA 37 using the RMA signal with the values specified in the circuit for setting the address of SZA 36. When comparing the input D of the first trigger T 44, an enable signal is received. The PC sets the read signal MEMR, which passes through the second bus driver ShF 21, the fourth bus driver ShF 24, the buffer BUF 38 and enters the input From the first trigger T 44. At the second trigger T 49, the clock is synchronized with the internal frequency from the pulse generator G 31 MA4A 3. From the output of the trigger T 49, I / O signals CHRDY and HOLD are generated. The signal CHRDY through the sixth bus driver ShF 34 enters the PC and delays the reading cycle. The CPU 32 completes the current cycle, sets the HLDA signal, which puts the buffer register BR 40, the seventh bus driver ShF 41 in an inactive state. The HLDA signal permits the passage of bus address A [0-16] through the bus amplifier SHU 33. Address A [0,12,19] in the fifth decoder of the interrupt vector DSHVP 46 generates a selection of RAM cells 45. Address A [1-11] selects the desired cell memory. Data D [0-15] from RAM 45 through the sixth bus driver ShF 34 is recorded in the second register of the WG 30 according to the signal STB BR, which is generated by the pulse shaper FI 39. From WG 30 data D [0-15] through the first bus driver ShF 20 enter the PC, and the reading cycle ends. Similarly, a PC reads the entire data block from the adapter module of the four-channel asynchronous MA4A 3.

Industrial applicability

The proposed device is industrially feasible, has wider functionality, allowing you to connect to a personal computer compatible with IBM PC, a large number of communication channels of various types, including those equipped with special equipment.

Claims (4)

1. Telecommunication multiplexer multipurpose, built on a modular basis and containing a system unit, which houses a four-channel telegraph unipolar (M4TGO) module for interfacing the multiplexer with four dedicated or switched four-wire communication channels and converting the logic signals of the multiplexer into current telegraphic packages when transmitting data to channels communication and conversion of current telegraphic packages into logical signals adapted for the multiplexer, when receiving data from the communication channel, a four-channel interface module С2 (М4С2) for electrical matching of single-pole circuits of an internal serial interface (VPI) of a multiplexer with four two-pole circuits of a standard interface С2 (RS-232С), the first group of inputs and outputs of which are connected to physical connection buses C2 lines, four-channel telegraph bipolar module (M4TGD) of the multiplexer interface with four dedicated or switched four-wire communication channels when transmitting by bipolar current packages, the first group of inputs and outputs of which is connected to the C1-TG buses connecting to telegraph communication channels, a two-channel bi-pulse module (M2BI) for pairing the multiplexer with two dedicated four-wire bi-pulse communication channels and converting logical signals from the multiplexer into a bi-pulse signal when transmitting data to the communication channel and the inverse transformation when receiving data from a communication channel, the first group of inputs and outputs of which are connected to the C1-I buses connecting to pulse channels, a single-channel bi-impulse module the second (M1BI) for pairing the multiplexer with a four-wire dedicated bi-pulse communication channel and converting the logical signals received from the multiplexer at the RS-232C interface into a bi-pulse signal when transmitting data to the communication channel and inverse transformation when transmitting data from the communication channel, the first group of inputs the outputs of which are connected to the C1-I bus of connection and the bi-pulse channel, a single-channel telephone module (M1TCH / TF) for pairing the multiplexer with leased and switched telephone communication channels with two water and four-wire termination and conversion of logic signals of the multiplexer into frequency-modulated signals in accordance with CCITT v 23 recommendations when transmitting data to a communication channel and in converting frequency-modulated signals to logical signals of a multiplexer when receiving data from a communication channel, the first group of inputs and outputs which is connected to the bus C1-PM connecting to the telephone communication channel, as well as the adjustment and control unit (DBK) for regulating the signal level in the communication channel and monitoring its status in a separate construct, the first group of inputs and outputs of which is connected to the first group of inputs and outputs of the four-channel telegraph unipolar (M4TGO) module, and the second group of inputs and outputs - with C1-TGO buses connecting to telegraph communication channels, characterized in that the multiplexer additionally contains four m channel asynchronous adapter modules (MA4A) located in the system unit of the multiplexer for implementing channel level protocols and performing interaction procedures with four communication channels in a synchronous duplex or half-duplex data transmission mode, the first groups of inputs and outputs of which are connected via an internal serial interface (VPI) to the second group of inputs and outputs of the four-channel telegraph unipolar module (M4TGO), or the four-channel interface module C2 (M4C2), or the four-channel telegraph bipolar module (M4TGD), or a dual-channel bi-pulse module (M2BI), a single-channel bi-pulse module (M1BI) and a single-channel telephone module (M1TCH / TF), a group control board (CCGT) for of group trunk signals and special control signals of the internal parallel interface (VPRI) and the implementation of procedures for establishing connections, converting and monitoring data in the process of transmitting and receiving information, the first group of inputs and outputs of which are connected via the internal parallel interface bus (VPRI) to the groups of second inputs - outputs of m four-channel asynchronous adapter modules (MA4A), interface card (PS) for matching the CCGT signals of the multiplexer with the ISA control trunk A PC, structurally located in the PC system unit, the first group of inputs and outputs of which is connected to the second group of inputs and outputs of a group control board (CCGT), and the second group of inputs and outputs is connected to the ISA system bus of a personal electronic computer compatible with IBM PC. 2. The multiplexer according to claim 1, characterized in that the interface card (PS) contains a first register (RG), the input of which is connected to the ISA bus (A [0-19]), and the output is with the first input of the group control board (CCGT) ), the first decoder (LH), the first and second inputs of which are connected respectively to the first (CS MEM) and second (CS I0) inputs of the CCGT unit, the first bus driver, the first group of inputs and outputs of which are connected to the ISA bus (D [0-15 ]), the input CS is with the output of the first DS decoder, and the group of outputs D [0-15] with the corresponding inputs of the CCGT unit, the second bus driver SHF, the first load one of the five inputs is connected to the ISA bus (MEM (R), MEM (W), IOR, IOW, AEN), the sixth input is with the IRQ [10] output of the group control board, five outputs are connected to the inputs MEM (R), MEM (W), IOR, IOW, AEM of the group control board, and the sixth output is with the ISA IRQ bus [10], the I / O CH RDY signal circuit from the CCGT is connected to the corresponding ISA bus circuit. 3. The multiplexer according to claim 1, characterized in that the group control board (CCGT) contains a third bus driver, the two inputs of which are connected respectively to the outputs A [0-19], AEN of the interface board (PS), and the first output to the bus AREA [13-19], the fourth bus driver, the four inputs of which are connected respectively to the outputs MEM R, MEM W, IOR, IOW of the interface card (PS), the second decoder, the three inputs of which are connected respectively to the first output of the third bus driver and two outputs of the fourth bus driver, and two outputs respectively Respectively, with the SPIR bus PNU_LA [0-7], РВ_РС / РУ [0-7], the third decoder, the two inputs of which are connected respectively to the first ShA [0-19] and second AEN outputs of the third bus driver, and three outputs, respectively - with the VPRI PDP bus and the CS MEM and CS I / O outputs of the PS interface card, the first CRC interrupt controller, the two inputs of which are connected respectively to the third output of the second decoder and the VPRI IRQ bus [0-7], fifth bus driver (BF), the first the input of which is connected to the VPRI bus MEM W, the sixth bus driver (BF), the two inputs of which are connected to respectively, with the output of the first interrupt controller and with the I / O CH RDY output, and two outputs, respectively, with the IRQ [10] and I / O SP RDY inputs of the interface card, the second RG interrupt register, the three inputs of which are connected respectively to the second output of the first controller interrupts D [0-7], the output of the fifth bus driver D [0-15] and the MEM circuit of the WPR, the fourth output of the fourth bus driver and the MEM R of the WMA MA4A, and the output with the input D [0-15] of the interface board. 4. The multiplexer according to claim 1, characterized in that the four-channel asynchronous adapter module (MA4A) contains a pulse generator G, a central processor, the first input of which is connected to the output of the pulse generator, a buffer register, two inputs of which are connected respectively to the bus A [0- 19] and the second output of the central processor, the eighth bus driver, two inputs of which are connected respectively to the bus D [0-13] and the second output of the central processor, and the input-output is connected to the VPI bus of the four-channel asynchronous adapter module, a pulse generator, the input and output of which are connected respectively to the second output of the central processor and the SRB bus STB_BR, a bus amplifier, the two inputs of which are connected respectively to the BPR bus A [0-16] and the second output of the central processor, and the output is connected to the output of the BR buffer register , random access memory, the first input of which is connected to the output of the buffer register A [1-11], and the output is connected to the VPI bus of the four-channel asynchronous adapter module, the fifth interrupt vector decoder, the input of which is connected to the output of the buffer about register A [0, 12, 19], and the first output is with the second input of random access memory, a read-only memory ROM, the input of which is connected to the second output of the fifth decoder of the interrupt vector, and the output is with the VPI bus of the four-channel asynchronous adapter module, fourth DS decoder, the two inputs of which are connected respectively to the output A [4-6] and the third output of the central processor, asynchronous serial ports (APP 0-3), the two inputs of which are connected respectively to the first output of the fourth decoder and w VPI D [0-7], and the first output with one of the sampling inputs of the multichannel asynchronous adapter module, the seventh bus driver, whose two inputs and outputs are connected respectively to the VPIR and VPI output-input, and the input to the third CPU input , an input-output register, three inputs of which are connected to the VPRI bus D [0-7] and РВ_РС / РУ and the first output of the fourth DS decoder, the first input-output - to the VPI bus of the module of the four-channel asynchronous adapter, the second interrupt controller, six inputs of which connected respectively the second and third outputs of the I / O register, the second output of the asynchronous serial port, the third and fourth outputs of the fourth decoder and the third output of the central processor, and the output with the second input of the central processor INT, an address setting circuit, an address comparison circuit, the three inputs of which are connected respectively with a VPRI bus DAP and A [13-15] and an output of the address setting circuit, a BUF buffer, two inputs of which are connected respectively to a VPRI bus MEM (R) and MEM (W), the first trigger (T), two inputs of which are connected respectively with out given the schemes for comparing the address and buffer, a second trigger, the two inputs of which are connected respectively to the output of the first trigger and the output of the pulse generator, and the two outputs, respectively, to the third HOLD input of the central processor and the I / O CH RDY bus.

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