CN1115019C - High-speed universal serial communication controller - Google Patents
High-speed universal serial communication controller Download PDFInfo
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- CN1115019C CN1115019C CN 00114085 CN00114085A CN1115019C CN 1115019 C CN1115019 C CN 1115019C CN 00114085 CN00114085 CN 00114085 CN 00114085 A CN00114085 A CN 00114085A CN 1115019 C CN1115019 C CN 1115019C
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Abstract
The present invention relates to a universal high-speed serial communication controlling device which is composed of a receiving part and a transmitting part, wherein the receiving part comprises a time sequence generator, a serial data receiver, a data buffer, a counter of an unread data packet, two multiple-path apparatuses and a data controller; the structure of the transmitting part is similar to that of the receiving part. Under the condition that multiple-path serial data code flow is received simultaneously, the present invention can complete the receiving or the transmission of the data by reasonably distributing time sequence and reasonably distributing and using storage space of external, and the present invention has the requirements of fewer peripheral parts and simple structure. Thus, the present invention realizes high-speed and multi-path serial communication with low cost.
Description
The invention belongs to data communication field, is a kind of high-speed universal serial communication control device.
More existing serial communication control device, as the SAB82538 that introduces among SIEMENS company product data handbook " the ESCC8 SAB 82538 Enhanced Serial Communication Controller " TB01.94, comprise: Bus Interface Unit, parallel interface, the serial line interface 0～7 of internal data bus and oscillator and 8 same structures.Serial line interface comprises FIFO again, timer, protocol processes part (HDLC, SDLC) and DMA interface, DPLL etc.Bus Interface Unit is used for carrying out the transmission of various data and Control Parameter with the data processor of outside, and parallel interface is finished some controlled function.Serial line interface is the most important parts of this chip.The data of receive direction deposit in through resume module such as protocol processes in the middle of the FIFO of inside in serial line interface inside afterwards, by the outside recording controller of interrupt signal notice, data are taken away by the recording controller of outside by Bus Interface Unit then.The processing procedure of sending direction is opposite.This device is the transceiving device of 8 tunnel serial HDLC forms, and the serial data rate maximum that product manual is introduced its each port support can reach 10Mbps.It receives, sends storage in the FIFO of inside.The maximum of distributing to the FIFO that sends and receive is 32byte.Adopt 8/16 parallel-by-bit data-interface between FIFO and the peripheral control unit, the read-write clock rate is up to 10M.In actual applications, the reception of each data and transmission all need outside control appliance to carry out the analysis and the control of data, and the time overhead of its execution has a strong impact on message transmission rate on the actual serial ports.There is following problem in this device: the FPDP that chip is supported is few, and perhaps the data rate of each port support is limited; Need more peripheral components cooperating, the scheme of some realizations also needs the stronger external chip of disposal ability to cooperate; Thereby the overall cost of realizing is higher.
The object of the present invention is to provide a high speed, multichannel has flow control, high-speed universal serial communication control device simultaneously with low cost.
High-speed universal serial communication controller of the present invention is made of receiving unit and transmission part,
Described receiving unit comprises: timing sequencer, control whole receiving unit work; 1～8 Gbps serial receiver, 1～8 data buffer, 1～8 read data package counting facility not constitutes 1～8 group of identical Data Receiving and processing unit; Port Multiplier A; Recording controller is inquired about the state of described data buffer, and whether the data of described data buffer is write outside data storage by described Port Multiplier A and bus L1 with data according to the state decision of described data buffer; Port Multiplier B, outside data processing equipment is by its state with the described not read data package counting facility of bus L2 judgement.
Described sending part branch comprises: timing sequencer, and control whole sending part and divide work; 1～8 serial data transmitter, 1～8 data buffer, 1～8 does not send the packet counter, constitutes 1～8 group of identical data and sends and processing unit; Port Multiplier C; Port Multiplier D; The described packet counter that do not send is by described Port Multiplier D, bus L4 and outside the mutual of various states that carry out; Recording controller, under the control of timing sequencer, inquire about the described state that does not send the packet counter, from the data storage of outside, extract data by Port Multiplier C, bus L3, put into described data buffer, and data are sent by data buffer.
Described high-speed universal serial communication controller, Gbps serial receiver in the receiving unit, data buffer, not the number of read data package counting facility and described transmission part serial data transmitter, data buffer, do not send the number of packet counter, can be by 8 multiple multiplication.
Describe the present invention below in conjunction with accompanying drawing.
Fig. 1 is the schematic diagram of receiving unit of the present invention.
Fig. 2 is the schematic diagram that sends part of the present invention.
Fig. 3 is a kind of actual application scheme of the present invention in the middle of fast packet switching network.
As Fig. 1, receiving unit 101 comprises: timing sequencer 102; 301～308,1～8 in 201～208,1～8 data buffer of 1～8 Gbps serial receiver is read data package counting facility 401～408 not, constitutes 1～8 group of identical Data Receiving and processing unit; Port Multiplier A103; Recording controller 110; Port Multiplier B104.Gbps serial receiver 201～208, data buffer 301～308, read data package counting facility 401～408 is corresponding one by one according to last numeral of label, as Gbps serial receiver 201 with data buffer 301, read data package counting facility 401 is not corresponding.Described not read data package counting facility is a forward-backward counter.
Under the control of timing sequencer 102, receiver 101 writes data by Port Multiplier A103, bus L1 to the data storage (not shown), and packet carries out the mutual of various states by Port Multiplier B104, bus L2 and external data processing device.Gbps serial receiver 201 receives serial data according to the sequential that timing sequencer 102 produces, when receiving the data bit of some, the state of judgment data buffer 301, judge whether that according to state the serial data that will receive writes data buffer 301, whether data buffer 301 bases have data to write is upgraded oneself state.Recording controller 110 is at the state of the control lower whorl continuous query data buffer 301～308 of timing sequencer 102.Suppose to inquire data buffer zone 301 constantly at t0.Whether it passes through Port Multiplier A103 by the state decision of judgment data buffering area 301, and bus L1 writes entry data memory with the data in the data buffer 301.When the state representation of data buffer zone 301 has received a complete packet, the state of the packet that recording controller 110 will just receive, as packet length, accepting state or the like is by Port Multiplier A103, bus L1 writes certain position of data storage area, and notify corresponding not read data package counting facility 401, make it upgrade oneself state.Recording controller 110 is inquired about next data buffer zone under the control of timing sequencer 102 then.This process moves in circles under the control of clock generator 102.
For multichannel data, the storage that every road receives is in the data buffer of an inside, the situation of the data buffer on each road of clock generator control data controller wheel continuous query, discovery has data to write at once in the outside data storage area, adjusts the address pointer of its data storage area simultaneously.By a kind of like this structure, avoided when the data buffer of inside is expired issuable situation about can't in time handle.Simultaneously,, utilize serial code stream to convert the time difference of parallel data to, both guaranteed can or not make the frequency of timing sequencer work too high again owing to poll causes loss of data by the degree of depth and the width of well-designed internal data buffer.
Respectively the read data package counting facility can not be an asynchronous forward-backward counter.The up-down signal of counter is respectively by independent signal input.The number of the packet that this counter records is not read away, outside data processing equipment can be by its state, and whether know has new packets need to handle at present.This counter can be exported different states according to some values that sets in advance, and represents the present available degree in data storage area, uses for inner recording controller, to reach the function that realizes flow control.
All data of receiving of receiving unit are kept in the data storage, if outside data processing equipment need know whether that the data of receiving need to handle, then by Port Multiplier B104, bus L2 judges the not state of read data package counting facility 401～408, whether know has new packet to exist, according to the address assignment of the data storage of making an appointment, to pass through simple computation, automatically obtain the position of new packet, can carry out the analysis or the processing of packet then.
Send part 501 as shown in Figure 2, comprising: timing sequencer 502; 701～708,1～8 in 601～608,1～8 data buffer of 1～8 serial data transmitter does not send packet counter 801～808, constitutes 1～8 group of identical data and sends and processing unit; Port Multiplier C503, Port Multiplier D504.Serial data transmitter 601～608, data buffer 701～708, not send packet counter 801～808 corresponding one by one according to last numeral of label, as serial data transmitter 601, data buffer 701, do not send packet counter 801 correspondences.The described packet counter that do not send is a forward-backward counter.
Under the control of timing sequencer 502, transmitter 501 is by Port Multiplier C503, bus L3 reads in data from the data storage (not shown), does not send packet counter 801～808 by Port Multiplier D504, bus L4 and outside the mutual of various states that carry out.The packet that outside recording controller will need to send deposits in the data storage, by Port Multiplier D504, bus L4 notifies corresponding of not sending in the packet counter 801～808, and notified does not send the packet counter according to the signal update oneself state that receives.Recording controller 510 is under the control of timing sequencer 502, and inquiry does not send the state of packet counter 801～808 successively.Suppose that the state table that does not send packet counter 801 is shown with the packets need transmission, then under the control of timing sequencer 502, by Port Multiplier C503, bus L3 takes out data from data storage.Judge then and the state of the corresponding data buffer 701 of serial link that can admit data as its expression, then data are put into data buffer 701.Serial data transmitter 601 sends the data bit-by-bit in the data buffer 701 under the control of timing sequencer 502.After the data transmission that sends finishes, upgrade the state of data buffer zone 701.After recording controller 510 judgements ran through a complete packet, notice did not send packet counter 801 accordingly, did not send packet counter 801 and upgraded oneself states.So far finish a complete data transmission procedure.
As required, Gbps serial receiver among the present invention in the receiving unit, data buffer, not the number of read data package counting facility and described transmission part serial data transmitter, data buffer, do not send the number of packet counter, can be by 8 multiple multiplication.
In the data communication system of reality, the serial data input and output side links to each other with the data communications equipment or the communication terminal of far-end, and both sides use identical communication protocol.Using more agreement at present in serial communication is the HDLC agreement.Realization of the present invention also can be used this agreement.In design example, finish 8 tunnel serial communications, the stream rate on every road is 10Mbps.
Fig. 3 is a kind of actual application scheme of this invention in the middle of fast packet switching network.
At receiving terminal, serial data enters after the receiving unit, and according to the agreement of both sides' serial communication agreement, the receiving unit of this equipment converts serial data to parallel data, deposits in the data buffer zone.Whether recording controller writes data in the data storage area according to the significance level of these data and how many decisions of data storage area remaining space at present.When receiving a complete correct frame, send the state update signal to read data frame counter not.The state of read data frame counter judges whether that new Frame arrives needs and handles to data processor according to inquiring about not.
The processing procedure of transmitting terminal is opposite.At first, judge whether data are write by the data processor of outside significance level according to the number and the required frame of sending of the vacant data buffer zone in the current transmission data storage area.After writing, do not send the state update signal to sending data frame counter.Send the recording controller inquiry and do not send data frame counter, finding has the Frame that needs transmission, then data is read from the data storage area, delivers in the data buffer zone.Transmit control device sends the communications protocol format by appointment of the data in the data buffer zone with data then.
In actual applications, for good testability is arranged, between transmission part and receiving unit, can increase the path that is used for carrying out loopback test.When needs are tested, this equipment is changed to inner self-looped testing state, self-test controller writes the self check data to the data storage that sends part, notice sends the not transmission data frame counter of part, self-test controller is checked the not read data frame counter of receiving terminal then, read the data of the data storage of corresponding receiving terminal again according to the state of read data frame counter not, judge whether correctly to receive data.Whether like this, just can detect whole transmission and receiving unit can operate as normal.
Among the present invention, all reception storage are in a data memory, and all transmission storage are in the another one data storage.According to the speed of serial code stream and the disposal ability of external data processing device, reasonably distribute data memory.By reasonably distributing sequential and to the reasonable distribution and the use of the memory space of outside, receive at the same time under the situation of serial data bit stream of multichannel 10Mbps, the reception that can finish data is (from the serial link receiving data, write the external data storage district) or send (from external data storage district reading of data, send), and without any need for the participation of other control devices.Peripheral circuit only needs a receive data buffer, and a transmission data buffer gets final product.Can also be with the corresponding increase of serial data port, and not only be defined as certain number.Because of peripheral components is few and simple in structure, thereby can reduce cost.In a word, the present invention has realized at a high speed at low cost, the serial communication problem of multichannel.
Claims (3)
1. a high-speed universal serial communication controller is made of receiving unit (101) and transmission part (501),
Described receiving unit (101) comprising: timing sequencer (102), control whole receiving unit work; 1～8 Gbps serial receiver (201～208), 1～8 data buffer (301～308), 1～8 read data package counting facility (401～408) not constitutes 1～8 group of identical Data Receiving and processing unit; Port Multiplier A (103); Recording controller (110) is inquired about the state of described data buffer, and whether the data of described data buffer is write data by described Port Multiplier A (103) and bus L1 the data storage of outside according to the state decision of described data buffer; Port Multiplier B (104), outside data processing equipment is by its state with the described not read data package counting facility of bus L2 judgement;
Described transmission part (501) comprising: timing sequencer (502), and control whole sending part and divide work; 1～8 serial data transmitter (601～608), 1～8 data buffer (701～708), 1～8 does not send packet counter (801～808), constitutes 1～8 group of identical data and sends and processing unit; Port Multiplier C (503); Port Multiplier D (504);
The described packet counter that do not send is by described Port Multiplier D (504), bus L4 and outside the mutual of various states that carry out; Recording controller (510), under the control of timing sequencer (502), inquire about the described state that does not send the packet counter, from the data storage of outside, extract data by Port Multiplier C (503), bus L3, put into described data buffer, and data are sent by data buffer.
2. the described high-speed universal serial communication controller of claim 1, it is characterized in that: the Gbps serial receiver in the described receiving unit, data buffer, not the number of read data package counting facility and described transmission part serial data transmitter, data buffer, do not send the number of packet counter, can be by 8 multiple multiplication.
3. the described high-speed universal serial communication controller of claim 1 or claim 2 is characterized in that: the not transmission packet counter in not read data package counting facility in the described receiving unit and the described transmission part is a forward-backward counter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00114085 CN1115019C (en) | 2000-03-01 | 2000-03-01 | High-speed universal serial communication controller |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 00114085 CN1115019C (en) | 2000-03-01 | 2000-03-01 | High-speed universal serial communication controller |
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| CN1306357A CN1306357A (en) | 2001-08-01 |
| CN1115019C true CN1115019C (en) | 2003-07-16 |
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| CN 00114085 Expired - Fee Related CN1115019C (en) | 2000-03-01 | 2000-03-01 | High-speed universal serial communication controller |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100505689B1 (en) * | 2003-06-11 | 2005-08-03 | 삼성전자주식회사 | Transceiving network controller providing for common buffer memory allocating corresponding to transceiving flows and method thereof |
| CN102999458A (en) * | 2011-09-09 | 2013-03-27 | 中国航天科工集团第三研究院第八三五七研究所 | High-speed intelligent serial port chip |
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