KR100211065B1 - Circuit for transmitting/receiving multiple cbr data - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of high-speed data transmission and reception circuits and methods, wherein a plurality of user information is paralleled to a high-speed data bus unit separated from a system bus in a broadband ISDN or private communication network using an asynchronous transfer mode (ATM). A system for connecting and communicating with a single data transmission unit, comprising: a target circuit pack (1) having a plurality of high speed data transmission circuit units (3) for transmitting a plurality of high speed data; An ATM network matching circuit pack (2) having a plurality of fast data receiving circuits (7) for receiving a plurality of fast data from said plurality of fast data transmitting circuits (3) and a multiplexed ATM cell receiver (9); Characterized in that.

Description

Circuit capable of transmitting and receiving multiple fixed bit rate data

1 is an exemplary configuration of an ATM network matching device to which the present invention is applied.

2 is an overall configuration diagram of a data transmission and reception circuit to which the present invention is applied.

3 is an exemplary configuration of a high speed data transmission circuit according to the present invention.

4 is an exemplary configuration of a high speed data receiving circuit according to the present invention.

5 is an exemplary configuration of a multiplexed ATM cell receiver.

6 is a diagram illustrating a configuration of connection lines of a high speed data bus.

7 is a plurality of transmission timing diagrams.

* Explanation of symbols for the main parts of the drawings

1: purpose circuit pack 2: ATM network matching circuit pack

3: a plurality of high speed data receiving circuits 4: a plurality of high speed data receiving circuits

The present invention relates to a circuit capable of transmitting and receiving a plurality of fixed bit rate data.

In the past, the bus coordination technique used in most system buses is utilized. To enable the transmission and reception of a large number of channels, a token chain, which means a bus right, is configured in a daisy chain form. To continue to rotate the token so that it only communicates with the token, and a number of devices wishing to access the bus apart from the arbitration logic that regulates the bus have received approval from the bus. In the case of transmitting and receiving a plurality of fixed bit rate information requiring high-speed real-time communication, a large number of devices are required due to the variable time delay caused by the change in the number of devices requiring a bus right for processing. There is a problem that it is difficult to guarantee the real-time transmission of the fixed bit rate information.

The present invention devised to solve the above-mentioned problems with the prior art, the invention is a broadband ISDN using asynchronous transfer mode (ATM) a plurality of terminal equipment used in narrowband ISDN and NTSC video signal as in the case of a plurality It is an object of the present invention to provide a high-speed data transmission / reception circuit capable of combining a plurality of fixed bit rate information with a circuit pack providing a connection function with an ATM network at a high speed, and capable of transmitting and receiving a plurality of fixed bit rate data in real time.

In order to achieve the above object, the present invention provides a single device by connecting a plurality of user information in parallel to a high-speed data bus separated from a system bus in a broadband integrated information network or a private communication network using an asynchronous transfer mode (ATM). A system for communicating with a data transmission unit, comprising: a target circuit pack having a plurality of high speed data transmission means for transmitting a plurality of high speed data, a first-in first-out (FIFO) memory and a control means; An ATM network matching circuit pack having a plurality of fast data receiving means for receiving a plurality of fast data from said plurality of fast data transmitting means and a multiplexed ATM cell receiving means; And a high speed data bus connected between the target circuit pack and the ATM network matching circuit pack.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is an exemplary configuration diagram of a representative ATM network matching device. FIG. 1 illustrates a configuration of an ATM network matching device capable of matching a narrowband ISDN terminal device and a codec for encoding and decoding a NTSC video signal at a 45M bit rate per second to a wideband ISDN. In consideration of such integrated network characteristics, two fixed bit rate information are transmitted and received in real time to an ATM network constant speed circuit pack as in the case of voice and video information.

As illustrated in the drawing, a narrowband ISDN matching circuit pack and a video codec matching circuit pack are embedded in the video codec matching circuit pack through the system bus 10 so that the target circuit packs are matched and controlled, and a plurality of fixed bit rate information is provided. (Information transmitted and received at the same ratio in an amount of information at regular time intervals) can communicate in real time via the high-speed data bus 20.

According to the present invention, one information source of the plurality of information sources is a rising edge of a clock based on a clock continuously supplied from one receiving device so that the plurality of information sources can transmit and receive information to one device in real time. At the edge, another information source detects the other party's busy information at the falling edge and recognizes the availability, and if there is a transmission request, it outputs its own busy information and notifies the other party of valid data. After the transmission is completed, the in-use information of the user is inactive (Inactive) so that there is no collision of data transmission according to timing, and the plurality of received complex information is sequentially stored in the FIFO memory and the identification number set in the first 4 bytes of ATM cells. It is configured to be delivered to the network according to (VPI; Virtual Path ID, VCI; Virtual Circuit ID).

FIG. 2 is a block diagram of an overall data transmission / reception unit to which the present invention is applied. The high-speed data bus shown in the drawing is an extended bus defined by using a user area of a system bus. , And defined in column C, the details of which will be described in FIG.

The object circuit pack 1 shown in the drawing includes a plurality of high speed data transmission circuit sections 3, loopback buffer means 4, FIFO memory and control circuits 5, and counterpart transmission clock recovery circuits 6, and ATMs. The network matching circuit pack 2 includes a plurality of high speed data receiving circuits 7 which receive transmission data, a transmission data valid clock, a transmission valid interval signal, a transmission cell start signal, and the like from the plurality of high speed data transmission circuits 3; Multiplexed ATM cell which provides the received data and the received data valid clock, the received valid interval signal and the received cell start signal to the same loopback buffer means 8 and the FIFO memory and control circuit 5 as the loopback buffer means 4 And a clock recovery unit 10 of a physical layer that provides a recovery clock to the receiver 9 and the counterpart transmission clock recovery circuit 6.

In the target circuit pack 1, as a preferred embodiment, among the 52 bytes of ATM cell, it is checked that its own access number (VPI; Virtual Path ID, VCI; Virtual Circuit ID value) promised in advance is received only from its own. Discard.

3 is a block diagram of a high-speed data transmission circuit according to the present invention. For convenience of explanation, one of a plurality of information sources is referred to as A and another as B, and each case is configured to have the same configuration. Explain. The * mark in the signal's name indicates that the signal is active at the negative signal level. The D flip-flop (hereinafter referred to as FF) 11 of A is connected to the B input busy signal * of the high-speed data bus and the transmission data valid clock is connected through the clock division unit 12 ( Hereinafter referred to as a clock). At this time, B must be connected to the effective data transmission clock (hereinafter referred to as B clock) whose phase is inverted by 90 degrees. The test clock is a clock that is provided by itself so that the test clock can be tested even in the absence of a valid clock for transmission data. The clock segment 12 can be selected by manual jumper or software control.

D ff (11) of A is set to a positive level upon a reset signal so that A is always available, and b is always available unless it is in use.

The DFF 13 of A indicates that there is an A transmit request when the D input is connected to the transmit cell ready signal of its own information source and the A clock is connected to the clock input so that the Q output is at a positive level. When the reset signal is applied, it becomes negative level and maintains no transmission request. In the embodiment, the state of the transmission FIFO memory is detected by the program element and output. The D FF and the peripheral circuits are all Pa7140 program element of ICT of USA. If A's FF (11, 13) are both active at the positive level, then B is not using the high-speed data bus, so the sublevel activates the busy signal A, which is the active level, and A and B are mutually connected via the high-speed data bus. The connected A busy signal is forwarded to b to prevent B's data transmission until a's data transmission is complete. Based on the busy signal and the clock a, the program element reads data of a certain size from the transmission FIFO memory and transmits the data to the high speed data bus together with the transmission valid period and the transmission cell start signal with timing adjustment. When the transmission is completed, the output level of the FF part 1 of A is added at the rising edge of the clock A, and the B signal is deactivated so that B can use it. A case where A and B simultaneously request data transmission in this detailed timing example is shown in FIG. 7 to be described later. In addition, since the method of B is the same as A, it abbreviate | omits.

4 is a configuration diagram of an embodiment of a high speed data receiving circuit according to the present invention. The latches 28 and 29 receive and latch transmission data from a high speed data bus, and the fixed bit rate information transmission control program element unit 27 The transmission valid interval signal and the transmission cell start signal from the high speed data bus are input and the transmission data valid clock is transmitted.

A transmission FIFO section 25, 26 is connected to the fixed bit rate transmission control program element section 27 and to the latch 28, and the data buffer sections 23, 24 are fixed bit rate information transmission control program element sections ( 27) and the respective transmission FIFO sections 25 and 26 to output transmission storage memory data.

An AAL and ATM layer transmitter 22 is connected to the data buffers 23 and 24 to provide a transmit storage memory address and memory access information to the fixed bit rate information transmission control program element unit 27 and to transmit a fixed bit rate information transmission signal. Receive a complete signal.

To further explain the operation by the above configuration, the information received via the high-speed data bus is connected to the latches 28 and 29 in parallel, respectively, and the output data of the latch element is transmitted and received set by the number of integer multiples to increase the data width. FIFO memories 25 and 26, respectively, and the output data of the FIFO memory elements are connected to the transmit and store memory data buses of commercial AAL and ATM layer transmitters 22 through data buffers 23 and 24.

The timing of the latches 28 and 29, the reading and writing of the FIFO memory elements, and the activation of the data buffer section are controlled by a program element, the program element being a 19.44M clock, a transmission data valid clock connected to the high speed data bus, and a transmission validity. The control signal is connected to the interval signal, the transmission cell start signal, and the control signals of the AAL and ATM layer transmitters 22 to input and output the control signals. An embodiment of the present invention uses a 74F574 latch device, a 7204 FIFO memory device with a 15n access time of US IDT, 74F541 device, and a PA7128 program device of ICT, USA to convert 8-bit information into 16-bit information. Implemented.

5 is a block diagram of an embodiment of a multiplexed ATM cell receiver according to the present invention. When receiving the fixed bit rate information from a commercialized AAL and ATM layer receiver, the data buffer unit and the timing adjustment program element are used as a high-speed data bus. After the width is converted, the reception data, the reception data valid clock, the reception valid section information, and the reception cell start signal are transmitted to the plurality of devices in the broadcast type through the high speed data bus as described above.

In addition, the loopback buffer unit for easily performing the function check during the test and operation using the same signal system between the transmission and reception in the method via the high-speed data bus devised in the present invention, the received data, the received valid interval signal, The reception cell start information is designed to be returned to the transmission data, the transmission valid interval signal, and the transmission cell start signal by using the buffer unit. Each buffer unit is activated only when the loop enable signal output from the destination circuit pack and the ATM network matching circuit pack shown in FIG. In the embodiment, the 74F541 buffer is used to configure the output to be in an open state with high impedance when inactivated so as to prevent normal data flow. At this time, the transmission and reception data clocks of the transmitter, receiver, and high-speed data bus are supplied with 19.44M clocks of the same phase.

In addition, in the case of the fixed bit rate device, the fixed bit rate information transmission and recovery clock divider unit provides a part which must faithfully restore the clock of the transmitting end connected to the opposite end of the network. The reconstruction clocks in the same phase are divided to provide the reconstruction clocks required by the desired circuit pack. 8KHz, DS3 class NTSC for narrowband ISDN device using a program element from the 155,520MHz clock recovered from the data received from the network by the physical layer recovery unit on the ATM network matching circuit pack of FIG. It is designed to divide and supply 44.736MHz clock for Vidioncodec. An example of the signal line is shown in FIG. 6 as R8K and R45M signals, and TD0-7 information is transmitted data transmitted from the target circuit pack to the present invention, GND signal is signal ground, and TDEN * signal is a valid valid section signal. , TDCLK is a transmission data valid clock, and TSOC * is a transmission cell start signal. Here, * indicates that the corresponding signal is activated at the negative signal level. The signal in column C is defined as signals identical to those of the above-mentioned transmission information group signal, and the direction of information is opposite to that of transmission except for the valid data received signal.

The transmission of information between the transmitting circuit and the plurality of high-speed data receiving circuits is performed by the plurality of destination circuit packs transmitting the BUSYA *, BUSYB * signals and their own transmission data preparation signals defined in columns 24 and 25 and increasing the effective data clock. Sample at the reduced edge and then transmit the transmit data synchronized with the transmit validity interval signal and the transmit data valid data clock unless another circuit pack is in use, and activate the transmit cell start information in the first transmit data interval. In this case, the 52-byte cell information is transmitted, and then the validity section information is invalidated.

FIG. 7 is a plurality of transmission timing diagrams. In the case where preparation of transmission cells is completed in two circuit packs at the same time, a transmission process is illustrated using a timing diagram. One information source (hereinafter referred to as A) selects a valid clock on the rising or falling edge of the input transmission data so that even when a transmission request occurs, the request is separated in time to output a usable signal. (Hereinafter referred to as B) can obtain a usable signal and transmit valid transmission data after A busy signal is deactivated. Here, * denotes a signal that is activated negatively, and // denotes that an intermediate signal section may be extended in time. In the embodiment, 52 bytes of information consisting of 4 bytes of ATM cell header pointer, 1 byte of serial number, and 47 bits of fixed bit rate user information are transmitted in one transmission validity interval signal. At this time, the transmission valid interval information and the transmission cell start information are adjusted so that valid transmission data always exists in the range satisfying the setup time and hold time at the rising edge of the transmission data valid clock using the timing adjustment element. In the embodiment, the control signal is implemented by using the PA7128 program element of ICT Corporation.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The following effects can be obtained by the above circuits and methods.

First, it provides real-time and integrated ATM network matching for multiple fixed bit rate circuit packs for one broadband ISDN access point. This can be effectively applied to a multimedia terminal device that must simultaneously transmit audio and video information in real time.

Second, a loopback unit is provided for both fixed bit rate circuit packs and ATM network matching circuit packs for matching signals with high-speed data buses to facilitate the testing of original circuit packs during development and functional tests during operation. do. This is due to the fact that each circuit pack can be designed as the same signal group for transmission and reception, and the received signal can be returned to the transmission signal using the high speed data bus local loopback signal, which is 1 bit of the buffer unit and control command information. .

Third, when a plurality of pieces of data are received, the data is latched using the latch unit, and then the write signal timing of the FIFO memory is adjusted and stored, thereby converting the data width of the byte, word, or long word. This makes it possible to access a long data width for information of a fixed bit rate circuit pack having a plurality of short data widths, thereby shortening the time for reading this information.

Claims (3)

In order to communicate with a single data transmission unit by connecting a plurality of user information in parallel to a high-speed data bus separated from the system bus in a broadband integrated information network or a private communication network using asynchronous transfer mode (ATM) A system comprising: a target circuit pack having a plurality of high speed data transmission means for transmitting a plurality of high speed data, a first-in first-out (FIFO) memory and control means; An ATM network matching circuit pack including a plurality of fast data receiving means for receiving a plurality of fast data from said plurality of fast data transmitting means and a multiplexed ATM cell receiving means; And a high-speed data bus coupled between the target circuit pack and the ATM network matching circuit pack. 2. The apparatus of claim 1, wherein the plurality of high speed data transmission means comprises: a 1D flip-flop connected to a high speed data bus, the one being always available, the other being always in use when the other is not in use; A clock divider configured to receive a test clock and select the jumper by manual jumper or software control; A 2D flip-flop that receives a transmit cell ready signal and receives a clock; A transmission control signal generation program element section configured to receive the clock and output a transmission first-in first-out memory control signal and a transmission valid period and transmission cell start signal through first and second elements; A first buffer unit which receives the first-in first-out memory data and buffers the first-in first-out memory data to output transmission data to a high speed data bus; A second buffer unit coupled to the transmission control signal generation program element unit to buffer transmission data from the first buffer unit to output received FIFO memory data; A NAND gate connected to an output terminal of the 1D flip-flop and an output terminal of the 2D flip-flop to perform a negative logic product to output a busy signal of an information source in use among a plurality of information sources; And a clock buffer connected to the high-speed data bus to generate a valid data transmission clock and provide the clock division unit to the clock division unit, providing a normal transmission data valid clock and a clock signal through an inverter to select the clock unit. A plurality of high speed data transmission and reception circuit, characterized in that. 2. The apparatus of claim 1, wherein the plurality of high speed data receiving means comprises: first and second latch portions for receiving and latching transmission data from a high speed data bus; A fixed bit rate information transmission control program element section receiving a transmission valid period signal and a transmission cell start signal from the high speed data bus and transmitting a transmission data valid clock; First and second transmission FIFO sections coupled to the fixed bit rate information transmission control program element section and coupled to the first latch; First and second data buffer sections coupled to the fixed bit rate information transmission control program element section and coupled to the respective first and second transmission FIFO sections for outputting transmission storage memory data; And an AAL and ATM layer transmitter coupled to the first and second data buffers to provide a transmit storage memory address and memory access information to the fixed bit rate information transmission control program element unit and receive a fixed bit rate information transmission signal and provide a completion signal. A plurality of high-speed data transmission and reception circuit comprising a.