KR100248548B1 - A creation and capturing circuit for asynchronous transfer mode date cell using cubit chip and ali-25c chip - Google Patents

Abstract

The present invention relates to a circuit capable of generating and capturing an asynchronous transfer mode (ATM) data cell using a CUBIT chip and an ALI-25C chip.

The present invention basically provides a cell capture processing unit and a control logic unit in addition to a conventional subscriber board using ALI-25C and ALI-25C and CUBIT to implement a cell generation circuit and a capture circuit, and UTOPIA. It configures the data cell to be automatically written to the FIFO while implementing the receiving cell generation circuit using the interface signal, and configures the transmission of arbitrary data cells to the UTOPIA interface automatically using the control logic. In principle, the captured data is stored using a microprocessor and backup memory, and then edited when necessary.

According to the present invention, developers of asynchronous transfer mode (ATM) switches can easily execute various types of tests and experiments, and operators can control traffic data, so that they can be applied to error recovery, system management, etc. in network operation. Instrument manufacturers have significant breakthroughs, including the ability to implement protocol capture capabilities when developing asynchronous transfer mode (ATM) protocol analyzers using CUBIT chips.

Description

Generation and Capture Circuits of Asynchronous Transfer Mode Data Cells Using Qubit Chip and Ali25C Chip

The present invention relates to a circuit for implementing a function capable of generating and capturing an asynchronous transfer mode (ATM) data cell using a CUBIT chip and an ALI-25C chip.

Generally, the subscriber board of the asynchronous transmission mode (ATM) is a cell switching processing unit 11 and an ali25C (ALI-25C), which are largely composed of a CUBIT chip, as shown in the configuration diagram of FIG. 1. It consists of the physical layer processing part 12 comprised.

In the subscriber board having the above configuration, the reception operation of the asynchronous transmission mode (ATM) data cell is as follows.

First, the physical layer processing unit 12 enables the RDval signal to send an asynchronous transmission mode (ATM) data cell to the cell switching processing unit 11 to inform that there is data to be sent. Then, the cell switching processor 11 receives the RDval signal from the physical layer processor 12 and prepares to receive data, and sends an RLoad signal and a CBClk signal to the physical layer processor 12 to inform that it is ready. Thereafter, the physical layer processing unit 12 starts to transmit data CID0 to CID7 in byte units at the rising edge portion of the CBClk clock received from the cell switching processing unit 11. Then, the cell switching processor 11 sends an asynchronous transfer mode (ATM) data cell received in bytes to the cell bus CellBus.

On the other hand, the transmission operation of the asynchronous transmission mode (ATM) data cell is as follows.

First, when there is data to transmit the asynchronous transmission mode (ATM) data cell to the subscriber network, the cell switching processor 11 first enables the TDval signal to inform that there is data to transmit. Then, the physical layer processor 12 receives the TDval signal and prepares to receive data, and supplies the TBClk clock to the cell switching processor 11. Thereafter, the cell switching processor 11 starts to transmit data COD0 to COD7 in byte units at the rising edge portion of the TBClk clock. Thereafter, the physical layer processing unit 12 sends the received data in units of bytes to the subscriber network.

On the other hand, in designing an asynchronous transfer mode (ATM) switch, a developer or operator of an asynchronous transfer mode (ATM) switch needs to develop a 25 Mbps subscriber board using a CUBIT chip and ALI-25C. Asynchronous transfer mode (ATM) data cells can be intercepted and controlled to reduce development time, and asynchronous transfer mode (ATM) data cells can be edited for use in many different applications. It is necessary to implement the interception function on the (ATM) subscriber board.

In the related art, in designing an asynchronous transfer mode (ATM) switch as described above, Ali25C (ALI-25C) and CUBIT were directly connected without additional logic.

By the way, the conventional configuration does not interfere with the operation of the asynchronous transfer mode (ATM) switch, the asynchronous transfer mode (ATM) data cell, control data cell, and loopback of the functions provided by the CUBIT chip Among the loop back data cells, the control data cell and the loopback data cell can be controlled by a microprocessor, whereas the asynchronous transfer mode (ATM) data cell is designed by a CUBIT chip so that the microprocessor cannot control it. Since the CUBIT chip is configured to bypass the internal chip to the asynchronous transfer mode (ATM) data cell with the ALI-25C, the asynchronous transfer mode (ATM) Traffic data cells, called Asynchronous Data Mode (ATM) data cells, that are transmitted through the Analysis and editing are not possible in the middle. Therefore, asynchronous transfer mode (ATM) switch developers cannot easily execute various types of tests and experiments, and asynchronous transfer mode (ATM) switch operators cannot control traffic data. Therefore, error recovery, system management, etc. can be performed. Not only is this difficult, but instrument manufacturers have been unable to apply asynchronous transfer mode (ATM) protocol capture capabilities when developing an asynchronous transfer mode (ATM) protocol analyzer using a CUBIT chip.

The present invention has been made to solve the above problems, by devising a circuit between the Ali25C (ALI-25C) and the CUBIT chip, it is possible to capture or generate asynchronous transfer mode (ATM) data cells in the middle It aims to provide a generation and capture circuit for asynchronous transfer mode (ATM) data cells using a CUBIT chip and an ALI-25C chip.

1 is a block diagram of a conventional subscriber board (Subscriber Board)

2 is an overall configuration diagram of a subscriber board of the present invention

3 is a detailed configuration diagram of a reception cell generation unit of the present invention;

4 is an operation timing diagram of a reception cell generator;

5 is a detailed configuration diagram of a transmission cell capture unit

6 is an operation timing diagram of a transmission cell capture unit.

<Description of the code | symbol about the principal part of drawing>

11: Cell Switching Processing Unit

12: physical layer processing unit

13: microprocessor

14: Backup Memory section

20: cell capture processing unit

21: Cell Storage

30: Control Logic Part

In order to achieve the above object, the present invention basically implements the functions of the present invention on a conventional subscriber board using ALI-25C (ALI-25C) and CUBIT as shown in the overall configuration diagram of FIG. In addition, a cell capture processing unit 20 and a control logic unit 30 are installed to implement a cell generation circuit and a capture circuit, and a reception cell generation circuit using a universal test and operation physical interface for ATM (UTOPIA) interface signal. Configure data cells to be automatically written to the FIFO and implement control logic so that any data cells are automatically transferred to the UTOPIA interface, and the captured data is stored in the microprocessor and backup memory. It is based on the principle that users can make edits when they need them after saving them.

The configuration of the present invention as described above is largely shown in the configuration diagram of Figure 2 cell switching processing unit 11, physical layer processing unit 12, microprocessor unit 13, backup memory unit 14, cell capture processing unit 20 and the control logic section 30. Here, the cell switching processor 11 is in charge of a CUBIT chip, the physical layer processor 12 is in charge of an ALI-25C chip, and the cell capture processor 20 is a synchronous FIFO. Was used.

The cell capture processing unit 20 is largely composed of a reception cell generation unit and a transmission cell capture unit, and the reception cell generation unit reads and reads signals from the microprocessor as shown in the configuration diagram of FIG. 3. The control logic unit 30 to control, the cell storage unit 21 for generating and storing the cell of 53 bytes, the microprocessor unit 13 and the cell switching processing unit 11, the transmission cell capture unit is shown in FIG. As shown in the block diagram of the microprocessor, the control logic unit 30 controls the read and write signals of the microprocessor, a cell storage unit 21 for generating and storing cells of 53 bytes, and the microprocessor. The unit 13 includes a backup memory unit 14 and a cell switching processor 11.

Hereinafter, the operation of the present invention having the configuration as described above.

First, the cell switching processor 11 converts a 53-byte asynchronous transmission mode (ATM) data cell converted into a virtual path identification (VPI) / virtual channel identification (VCI) value of a destination. It functions to deliver on the bus (CellBus) to allow virtual exchange of data. In addition, the physical layer processing unit 12, the cell capture processing unit 20 and the UTOPIA interface are connected to transmit and receive the asynchronous transmission mode (ATM) data cell.

On the other hand, the physical layer processing unit 12 converts the 25 Mbps asynchronous transmission mode (ATM) cell data received from the subscriber network into a UTOPIA interface form and transfers it to the cell switching processing unit 11, and conversely, the cell switching processing unit ( It transmits 53 bytes of cell transmitted in 11) to subscriber network.

The microprocessor unit 13 generates various control signals such as an RD / WR signal and provides them to the control logic unit 30, and writes an asynchronous transfer mode (ATM) data cell to the cell capture processing unit 20. Or, it reads and stores the data in the backup memory unit 14.

The backup memory unit 14 also stores asynchronous transfer mode (ATM) data cells read by the microprocessor unit 13.

Meanwhile, the cell capture processing unit 20 performs a capture function of sequentially writing an asynchronous transfer mode (ATM) cell received from the cell switching processing unit 11 through a UTOPIA interface to a memory, and micro The processor unit 13 may read the corresponding data. It also functions to transfer arbitrary asynchronous transmission mode (ATM) cell data to the FIFO and transfer it to the cell switching processor 11 via the UTOPIA interface.

The control logic unit 30 receives a control signal from the microprocessor unit 13 and the utopia signal, generates a control signal for enabling the cell switching processor 11, and transmits a TLoad and RLoad signal to the cell switching processor 11. to provide.

Hereinafter, the operation of the cell capture processing unit 20 will be described in more detail.

The role of the reception cell generation unit of the cell capture processing unit 20 allows the user to arbitrarily create an asynchronous transmission mode (ATM) data cell, so that the contents of the traffic data queue of the cell switching processing unit 11 can be determined. Function to freely control.

3 illustrates the connection of various control signals related to the reception cell generation unit. First, the microprocessor stores the / WEN signal generated by the control logic unit 30 to generate an arbitrary cell. Assert to (21) to make the state possible to write. The / WEN signal is made of a combination of the signals A0 to A14 and the RD / WR signal from the control logic unit 30 by a memory mapped method, and is assigned an arbitrary address accordingly. Thereafter, when the microprocessor enables the / WCLK signal to write a value to the cell storage unit 21, the values D0 to D7 are sequentially stored from the first address of the cell storage unit 21 in bytes. Is recorded. The / WCLK signal is made of a combination of the RD / WR signal and the TTL logic in the control logic unit 30.

The microprocessor asserts the RDval signal generated by the control logic unit 30 to the cell switching processor 11 to send the stored value to the cell switching processor 11. Then, the RDval signal makes the RBClk clock provided from the cell switching processor 11 in the control logic unit 30 to maintain the state of '1' for 53 clocks in synchronization with the / OE signal. The RDval signal is a signal that the cell switching processing unit 11 recognizes that the values CID0 to CID7 are ready to be input. Here, the / OE signal serves as an ON / OFF flag in order to output a value CID0 to CID7 by assigning an arbitrary address from the microprocessor unit 13, and the signals A0 to A14 and the signals D0 to D7. It is made in the control logic unit 30 by the combination of.

The cell switching processor 11 automatically receives the RDval signal and automatically asserts the RLoad signal to the / REN signal of the cell storage 21. The signal is transmitted from the cell switching processor 11 to the asynchronous transmission mode (ATM) data. Signal indicating that the cell is ready to receive. At this time, while the / REN signal is enabled, the cell storage unit 21 transfers the values already written according to the RBClk to the cell switching processor 11 in the lines CID0 to CID7.

The operation of the various signals related to the reception cell generator as described above is shown in time in the timing diagram of FIG. 4.

Meanwhile, referring to the operation of the transmitting cell capture unit of the cell capture processing unit 20, the role of the transmitting cell capture unit is UTOPIA when an asynchronous transmission mode (ATM) data cell is transmitted from the cell switching processing unit 11 to the subscriber network. ) It intercepts the values (CID0 to CID7) in the interface so that the user can freely analyze or control the contents. Connection of various control signals related to the transmission cell capture unit is shown in the configuration diagram of FIG. 5.

First, the asynchronous transfer mode (ATM) data cells transmitted from the cell switching processor 11 to the physical layer processor 12 through the UTOPIA interface are simultaneously input to the cell storage 21. First, the cell switching processor ( 11), if there is an asynchronous transmission mode (ATM) data cell to be transmitted, generates a TDval signal to indicate that the / WEN signal of the cell storage unit 21 is ready for transmission. The TDval signal is simultaneously input to the control logic unit 30, and the control logic unit 30 combines the TBClk and the TDval signals provided from the physical layer processing unit 12 so that the cell switching processing unit 11 recognizes the two clocks. Delay to generate the TLoad signal.

The cell switching processor 11 transmits an asynchronous transfer mode (ATM) data cell to the cell storage unit 21 in units of bytes at the same time as the input of the TLoad signal through the signal lines COD0 to COD7, and the cell storage unit according to the TBClk signal. Writing starts automatically from the first address of (21). The cell storage unit 21 sequentially stores data in the FIFO according to the TBClk signal, and the microprocessor unit 13 enables the / REN signal from the control logic unit 30 to read the stored ATM data cell. The / REN signal is made of a combination of the signals A0 to A14 and the RD / WR signal in a memory mapped manner.

On the other hand, the / OE signal is made of a combination of the signals A0 to A14 and the signal D0 from the microprocessor unit 13, and receives an arbitrary address to the microprocessor unit 13 through the signal lines D0 to D7. It is a signal for outputting data and serves as ON / OFF flag. Here, the microprocessor unit 13 reads the data according to the RCLK signal by enabling the / OE signal to read the data of the cell storage unit 21, stores the data in the backup memory unit 14, and reads it when necessary. The RCLK signal is generated in the control logic unit 30 by the combination of the RD / WR signal and the TTL signal.

The operation of the various signals related to the transmission cell capture unit as described above is indicated in time in the timing diagram of FIG. 6.

Therefore, according to the present invention, the asynchronous transfer mode (ATM) switch developer can easily execute various types of tests and experiments, and the asynchronous transfer mode (ATM) switch operator can control the traffic data so that an error occurs when operating the network. Not only can it be applied to recovery, system management, etc., instrument manufacturers can use it to implement asynchronous transfer mode (ATM) protocol capture function when developing an asynchronous transfer mode (ATM) protocol analyzer using a CUBIT chip. It works.

Claims (3)

A circuit for implementing a function of generating and capturing an asynchronous transfer mode (ATM) data cell using a CUBIT chip and an ALI-25C chip, the cell switching processor 11 and a physical layer processor. 12, the microprocessor unit 13, the backup memory unit 14, the cell capture processing unit 20 and the control logic unit 30, the cell switching processing unit 11 is composed of a CUBIT chip The physical layer processing unit 12 is an asynchronous transmission mode data cell generation and capture circuit using a qubit chip and an Ali25C chip, characterized in that composed of an Ali25C (ALI-25C) chip The control circuit of claim 1, wherein the cell capture processor 20 includes a receiver cell generator and a transmitter cell capture unit, and the receiver cell generator controls read and write signals of a microprocessor. And a cell storage unit 21, a microprocessor unit 13, and a cell switching processor 11 for generating and storing cells of 53 bytes. The transmission cell capture unit reads the microprocessor. ), A control logic unit 30 for controlling the write signal, a cell storage unit 21 for generating and storing cells of 53 bytes, a microprocessor unit 13, a backup memory unit 14, and cell switching Generation and capture circuit of asynchronous transmission mode data cell using a qubit chip and Ali25C chip, characterized in that the processor 11 The generation and capture circuit of an asynchronous transmission mode data cell using a qubit chip and an Ali 25C chip according to claim 2, wherein the receiving cell generating unit and the transmitting cell capturing unit are implemented using a UTOPIA interface signal.

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