KR100197431B1 - Multi protocol realization method of atm virtual channel switch - Google Patents

Abstract

In the ATM virtual channel exchanger, the present invention uses three APCA boards for IPC functions between main processors (MPs) (OMP and CCCP) while maintaining compatibility with the existing high-level operating system (CROS). The present invention relates to a multi-protocol implementation method of an ATM virtual channel switch suitable for implementing a message transmission / reception function in firmware. In the present invention, an operating system is modified to fully consider compatibility with an existing operating system. Without this, only the firmware of ATM matching IPC board is modified to enable IPC and ATM signaling message processing.

Description

Multiprotocol Implementation Method of ATM Virtual Channel Switch

1 is a diagram illustrating an embodiment of a message structure between an upper operating system and an APCA firmware according to a multi-protocol implementation method of an ATM virtual channel exchange of the present invention.

2 shows an embodiment of the form of a signaling message according to FIG.

3 illustrates another embodiment of a signaling message according to a multi-protocol implementation method of an ATM virtual channel exchange of the present invention.

Figure 4 is a flow chart showing step by step an embodiment of a specific classification / transmission algorithm according to the multi-protocol implementation method of the ATM virtual channel exchange of the present invention.

5 is a flowchart showing step by step an embodiment of a signaling message processing routine according to FIG.

6 is a diagram illustrating a type-5 CPCS-PDU of an ATM SAR layer according to a method for implementing multiple protocols of an ATM virtual channel exchange of the present invention.

FIG. 7 is a flowchart illustrating a step-by-step embodiment of a process of processing a packet received through an interrupt service routine according to a method of implementing a multi-protocol of an ATM virtual channel exchange.

The present invention relates to a method for implementing a multi-protocol of an Asynchronous Transfer Channel (VC) virtual channel (VC) switch, and more particularly, in a ATM virtual channel switch, The APCA board, which handles the IPC function between the main processor (MP) (OMP, CCCP), supports three types of message sending / receiving functions while maintaining compatibility with the existing high-level operating system (CROS). The present invention relates to a multi-protocol implementation method of an ATM virtual channel switch suitable for implementation.

In this regard, the electronic switch according to the prior art used only a single type of IPC message for communication between main processors, and the medium used a serial line in the form of a high level data link control (HDLC). The lost protocol is recovered through a sliding window of the same protocol as that of all main processors to be communicated, that is, a selective repeat method.

Accordingly, in the present invention, the main processor of the ATM virtual channel exchanger must perform IPC communication with the main processor and the subscriber matching device (SIMC), and ATM signaling messages different from the IPC type used in the existing electronic switching system. Message) should also be handled together.

Accordingly, an object of the present invention is to provide an ATM virtual channel exchanger capable of processing IPC and ATM signaling messages by modifying only firmware of an ATM matched IPC board without modification of an operating system in order to fully consider compatibility with an existing operating system. The present invention provides a method for implementing multiple protocols.

Hereinafter, embodiments of the present invention for achieving the above object will be described in detail with reference to FIGS. 1 to 7.

First of all, the main repeater of the ATM virtual channel exchanger is an IPC-type message exchange with error recovery by applying the sliding window protocol of the selective repeat method, which is used previously, and between the main processor and the subscriber matching device (SIMC). Message exchange should take place in the form of IPC with no protocol applied.

In addition, processing of ATM signaling messages must be performed separately from IPC.

These three types of messages do not need to be distinguished by higher operating systems, they only need to be processed with the same IPC that was used.

Referring to FIG. 1, FIG. 1 is a diagram illustrating an embodiment of a message structure exchanged between an upper operating system and an APCA firmware according to a multi-protocol implementation method of an ATM virtual channel exchange according to the present invention. The only difference is that the maximum length of the actual message part is increased to 496 bytes.

Next, the APCA receives the same type of message from the upper operating system and processes the same message into three message types according to the signal ID and the destination address.

First, since the signaling message is an initial signal using only a specific signal ID, the signal ID of the message received from the upper operating system should be compared and classified into a signaling message type as shown in FIG.

A detailed division / transmission algorithm is shown in FIG.

First, by using the Tx Buffer Pointer of DPRAM to be processed currently, the message to be transmitted is read into the internal buffer (400), and whether such a message is an IPC or signaling message (401). Case goes to the signaling message processing routine as shown in FIG.

That is, one descriptor number is obtained from the free queue of the SARA-S control memory (the queue in which the number of available descriptors is stored) (500).

Here, the biggest difference in processing the signaling message and the IPC message is that in case of the IPC message, information about the virtual path identifier (VPI) / virtual channel identifier (VCI) is transmitted to the destination address and source address (IPC header) of the IPC header. While the signaling message is calculated from the source address, the signaling message is delivered in the real message directly by the upper application software in the form of FIG. 3, so that the virtual path identifier / virtual channel identifier is separately added as in IPC. You don't need to calculate it, just use the value from the top.

Therefore, the virtual path identifier / virtual channel identifier value obtained from the actual message portion is written into the descriptor obtained from the descriptor number (501,502). Unlike the IPC message, the header portion is not required, so the actual message portion except for the IPC header portion is shown in FIG. AAL-5 layer type message format is created and written in the packet memory of SARA-S.

At this time, if the actual message length and the CPCS-trailer length are added up to a multiple of 48 bytes (the length of the header except the header of the ATM cell), the length of the packet is the message length + CPCS_trailer length. The length of the packet is obtained according to the equation int (message length / 48) * 48) and the calculated value is written in the CPCS trailer length portion of FIG. 6) (503, 504).

Next, by writing the descriptor number to the ready queue of SARA-S, the packet is segmented into a cell form and transmitted to the receiving main processor. The descriptor number used for the segmentation is the transmit complete queue. Queue may be returned to be used for the transmission of the next packet (505).

On the other hand, as shown in FIG. 4, if the signal ID is not for the signaling message, the destination address is compared (403), and if the address of the main processor, the process goes to step 404 to apply the sliding protocol, and if the address of the SIMC goes to step 409. .

That is, the protocol control block (Window) of the main processor is found to check the communication possible state, and if the state of the main processor is in the DEAD state, the corresponding IPC is discarded and the next IPC is processed (404, 405).

On the other hand, in the communication enabled states (READY, WAIT, IDLE), a queue node having a structure similar to that of FIG. 2 is obtained from a free queue having a linked list structure (Get_node). Copy the IPC header portion and the actual message portion without the overhead for the queue to the queue node (406).

Such a node is linked to a window of the corresponding main processor, put into a slide according to a sliding protocol procedure, and then sequentially transmitted, and a lost message is entered into a recovery process by a retransmission request method (407 and 408).

In this case, the sliding window protocol is a rather complicated content, but since it is a well-known general concept, detailed description thereof will be omitted.

The IPC, which has undergone the protocol procedure, calculates the virtual path identifier from the destination address, calculates the virtual channel identifier from the source address, and writes it in the descriptor obtained in the same manner as in processing the signaling message. The protocol is applied to the packet memory in the form of an AAL-5 layer message in the form of IPC to which it is applied (409, 410, 411, 412).

If the destination address is SIMC in step 403, the sliding window protocol processing step 408 is omitted, and steps 409 to 412 result in a protocol such as FIG. Sent in IPC format not applied.

Packets transmitted in this way are reached through the ATM switch in the form of ATM cells to the destination processor, and the ATM cells that have been divided by the SARA-R chip on the receiving side are collected and reconstructed into the original packet form.

This reconstruction is called reassembly.

The reassembled packet is accumulated in the packet memory of the SARA-R, and the information is recorded in the descriptor of the control memory to provide the upper firmware with information for processing the packet.

In order to refer to the descriptor in which the packet information is recorded, the descriptor number written to the packet complete queue by SARA-R must be read. For this purpose, SARA-R writes the descriptor number to PCQ and interrupts it. As such, the firmware can be recognized.

Processing of the packet received through the interrupt service routine is the same as the seventh.

First, when an interrupt from SARA-R is detected (700), the descriptor number is read from the PCQ, the values are compared, and if it is 0, an error (Error) is returned. Therefore, the processor immediately returns without processing any more (701, 717).

In step 701, the descriptor number is read from the PCQ, the value is compared, and if it is not 0, the descriptor is found using the descriptor number, and the virtual channel identifier value is read from the descriptor to distinguish between the IPC and the signaling message (702, 703). .

To this end, a range of virtual channel identifiers to be used by the IPC and signaling message must be defined in advance, and a virtual channel identifier value must be allocated at the transmitting side according to such a rule.

If the virtual channel identifier value of the signaling message in step 703 above, the length of the packet is read (709, 710) by subtracting the offset value of the CPCS trailer from the end of the packet by referring to the DMA completion address from the descriptor.

In this case, in order to deliver the signaling message to the upper operating system, a process of converting the signaling message into an IPC type message is required as opposed to the transmission.

Therefore, a buffer of the form shown in FIG. 2 is obtained (711), the data of the packet length starting from the start address of the packet is read and copied into the actual message area of the buffer (712), and the virtual channel identifier value previously read from the descriptor. And the virtual path identifier value and the packet length into the corresponding element of the buffer (713). In the IPC header, the destination address and source address are their IDs, and the message length is the packet length + 8 (virtual path). Identifier, Virtual Channel Identifier, Routing Tag, and Real Length), and the Signal ID forms a complete IPC form by writing a predetermined initial signal value to the upper operating system through the DPRAM area. (714, 715).

If the virtual channel identifier is for IPC in step 703 above, the IPC header portion can be read directly from the start address of the packet (704).

Therefore, if the source address of the received IPC is the address of the main processor, error detection and recovery are performed through a sliding window protocol process, and protocol overhead (IPC type, sequence number, and Fiji as shown in FIG. 3). Piggyback) is transmitted to the upper operating system in the form of FIG. 1 with the exclusion (steps 705, 707, and 708).

In this case, if the received packet is received from the SIMC in step 705, the packet is delivered directly to the upper operating system without undergoing a protocol process (706).

As described above, the present invention may allow IPC and ATM signaling message processing by modifying only the firmware of the ATM matching IPC board without modifying the operating system in order to fully consider compatibility with the existing operating system.

Claims (3)

Reading the message to be transmitted to the internal buffer by using the transmission buffer pointer of the DPRAM to be processed currently, and distinguishing whether such a message is an IPC or signaling message and performing a signaling message processing routine in the case of a signaling message (400, 401). , 402); Comparing the destination address if the signal ID is not for a signaling message (403); In step 403, if the address of the main processor is found, the protocol control block of the main processor is searched for and the communication status is checked. )Wow; Obtaining a queue node from a free queue having a link list structure therein when the communication is possible in step 405, and copying the IPC header portion and the actual message portion without the overhead for the protocol to the queue node ( 406); In step 406, the node is linked to a window of the corresponding main processor, put into a slide according to a sliding protocol procedure, and transmission is sequentially performed. The lost messages are entered into a recovery process by a retransmission request method (407 and 408); ; The IPC, which has undergone the protocol procedure, calculates the virtual path identifier from the destination address, calculates the virtual channel identifier from the source address, writes it in the descriptor obtained in the same manner as processing the signaling message, and applies the protocol, which is the actual packet data, to the IPC type. Steps 409, 410, 411, and 412 that are inserted into the packet memory in the form of an AAL-5 layer message of the message; If the destination address is SIMC in step 403, the sliding window protocol processing step 408 is omitted, and in steps 409 to 412, the protocol that excludes 6 bytes of the protocol overhead is not applied to the IPC form. A method of implementing a multi-protocol of an ATM virtual channel exchanger comprising the step of transmitting. The method of claim 1, wherein the signaling message processing routine of the step (400, 401, 402) comprises: (500) obtaining one descriptor number from a prequeue of a SARA-S control memory; The virtual path identifier / virtual channel identifier value obtained from the actual message portion is written into the descriptor obtained from the descriptor number (501,502), and the actual message portion excluding the IPC header portion is written in the AAL-5 layer message format to form a packet of SARA-S. Writing to memory (503, 504); A method of implementing a multi-protocol of an ATM virtual channel switch comprising the step (50) of writing a descriptor number to a ready queue of SARA-S. In the process of processing the packet received through the interrupt service routine, if it detects the interrupt from SARA-R (700), it reads the descriptor number from the PCQ, compares the values, and returns 0 without any further processing because it is an error. 701, 717; In step 701, the descriptor number is read from the PCQ, the value is compared, and if it is not 0, the descriptor is found using the descriptor number, and the virtual channel identifier value is read from the descriptor to distinguish between the IPC and the signaling message (702, 703). Wow; Reading (709, 710) the length of the packet by subtracting the offset value of the CPCS trailer from the end of the packet with reference to the DMA completion address from the descriptor if the virtual channel identifier value of the signaling message in step (703); Obtain a buffer (711), read the packet length data from the start address of the packet, copy it to the actual message area of the buffer (712), and store the virtual channel identifier value, virtual path identifier value, and packet length previously read from the descriptor. Write it in the corresponding element (713) and in the IPC header, complete the IPC form by writing the destination address and source address as its ID, the message length as the packet length + 8, and the signal ID as the predefined initial signal value. Configuring 714 and 715 and delivering the upper operating system through the DPRAM area; Reading (704) the IPC header portion directly from the start address of the packet if the virtual channel identifier is for IPC in step (703); If the source address of the received IPC is the address of the main processor, error detection and recovery are performed through a sliding window protocol process, and steps 705, 707, and 708 are delivered to the upper operating system without the protocol overhead. ; And if the received packet is received from SIMC in step 705, forwarding the received packet directly to a higher operating system without going through a protocol process.